Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a preparation method thereof, comprising: a substrate, including a substrate and an insulating dielectric layer, wherein the substrate has a plurality of grooves extending along a first direction, the substrate on both sides of the grooves forms a semiconductor column, and the insulating dielectric layer is located on the sidewall and top of the semiconductor column; a doping region, located in the substrate at the bottom of the semiconductor column, wherein the doping region has a plurality of mutually spaced first bit line grooves, and the substrate below the first bit line groove has a second bit line groove extending along a second direction, wherein the second direction and the first direction have an angle, and the second bit line groove connects the plurality of first bit line grooves; and a bit line, located in the first bit line groove and the second bit line groove. The method of forming the bit line in the first bit line groove and the second bit line groove by etching the doping region at the bottom of the groove to form the first bit line groove and the second bit line groove reduces the contact resistance between the bit line and the semiconductor column and increases the performance of the vertical full surround gate.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, the size of transistors is getting smaller and smaller, and vertical gate-all-around (VAGG) has been widely used due to its advantages in integration and wiring.

[0003] In the existing VAGG, the bit line is embedded using an embedding method. First, ions are doped into the groove at the bottom of the semiconductor column, and then the groove at the bottom of the semiconductor column is hollowed out and filled with bit line metal to form the bit line. Since the doped ions are dug out, the contact effect between the bit line and the semiconductor column is poor, which affects the use of the VAGG. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem of poor ohmic contact between bit lines and semiconductor pillars in the prior art.

[0005] In order to achieve the above object, on the one hand, the present invention provides a semiconductor structure, comprising:

[0006] A base, comprising a substrate and an insulating dielectric layer, wherein the substrate has a plurality of grooves extending along a first direction, and semiconductor pillars are formed on both sides of the substrate of the grooves, and the insulating dielectric layer is located on the sidewalls and top of the semiconductor pillars;

[0007] a doped region located in the substrate at the bottom of the semiconductor column and the bottom of the trench, wherein the doped region has a plurality of first bit line grooves spaced apart from each other, and the substrate below the first bit line groove has a second bit line groove extending along a second direction, wherein the second direction and the first direction have an included angle, and the second bit line groove is connected to the plurality of first bit line grooves;

[0008] The bit lines are located in the first bit line grooves and the second bit line grooves.

[0009] In one embodiment, the first bit line trench is a bottom portion of the trench between the semiconductor pillars.

[0010] In one embodiment, the doping region is an ion implantation region; the doping region includes a first doping region and a second doping region arranged vertically, the second doping region is located on both sides of the first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the second doping region; the bottom of the first bit line groove is located in the first doping region.

[0011] In one embodiment, a top of the second bit line trench is located in the first doped region.

[0012] In one embodiment, the semiconductor structure further comprises:

[0013] The passivation protection layer is located on the sidewall of the first bit line groove.

[0014] In one embodiment, the passivation protection layer includes a polymer layer.

[0015] In one embodiment, the bit line comprises:

[0016] Metal silicide, located on the surface of the first bit line groove and the surface of the second bit line groove;

[0017] The bit line conductive layer is located on the surface of the metal silicide.

[0018] The present invention also provides a method for preparing a semiconductor structure, comprising the following steps:

[0019] Providing a substrate, the substrate comprising a substrate and an insulating dielectric layer, wherein a plurality of grooves extending along a first direction are formed in the substrate, semiconductor pillars are formed on both sides of the grooves, and the insulating dielectric layer is located on the sidewalls and top of the semiconductor pillars;

[0020] doping the substrate at the bottom of the semiconductor column through the trench to form a doped region;

[0021] Etching the doped region at the bottom of the trench to form a plurality of first bit line grooves spaced apart from each other in the doped region;

[0022] Etching the substrate below the first bit line groove to form a second bit line groove extending along a second direction, wherein the second direction and the first direction have an included angle, and the second bit line groove is connected to a plurality of the first bit line grooves;

[0023] Bit lines are formed in the first bit line trench and the second bit line trench.

[0024] In one embodiment, the doped region at the bottom of the trench is etched to form a plurality of mutually spaced first bit line grooves in the doped region, including:

[0025] In the vertical direction, the doped region at the bottom of the trench is etched to form the first bit line trench.

[0026] In one embodiment, the doping region is formed by ion implantation; the doping region includes a first doping region and a second doping region arranged vertically, the second doping region is located on both sides of the first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the second doping region; the bottom of the first bit line groove is located in the first doping region.

[0027] In one embodiment, a top of the second bit line trench is located in the first doped region.

[0028] In one embodiment, before etching the substrate below the first bit line trench to form a second bit line trench extending along the second direction, the method further includes:

[0029] A passivation protection layer is formed on the sidewall of the first bit line trench.

[0030] In one embodiment, forming a passivation protection layer on the sidewall of the first bit line trench includes:

[0031] Passivation gas is introduced to form a passivation material layer on the sidewall and bottom of the first line groove;

[0032] The passivation material layer at the bottom of the first bit line trench is removed by etching to form the passivation protection layer.

[0033] In one embodiment, in the same ion etching chamber, after the passivation material layer at the bottom of the first bit line trench is removed by etching, the substrate below the first bit line trench is etched to form a second bit line trench extending along the second direction.

[0034] In one embodiment, forming the bit lines in the first bit line trench and the second bit line trench includes:

[0035] forming metal silicide on a surface of the first bit line groove and a surface of the second bit line groove;

[0036] A bit line conductive layer is formed on the surface of the metal silicide.

[0037] The semiconductor structure and the preparation method thereof of the present invention have the following beneficial effects:

[0038] The semiconductor structure of the present invention reduces the contact resistance between the bit line and the semiconductor column by arranging a bit line composed of a plurality of mutually spaced first bit line grooves and a second bit line groove extending along a second direction in the doping region, thereby improving the performance of the VAGG.

[0039] The method for preparing the semiconductor structure of the present invention forms a first bit line groove and a second bit line groove by etching the doped area at the bottom of the groove, and forms a bit line in the first bit line groove and the second bit line groove, thereby reducing the contact resistance between the bit line and the semiconductor column and increasing the integration of the VAGG. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0042] Figure 2 A schematic diagram of the structure of a VAGG provided in an embodiment;

[0043] Figure 3 is a schematic structural diagram of an insulating dielectric layer provided in an embodiment;

[0044] Figure 4 is a schematic structural diagram of an insulating dielectric layer provided in an embodiment;

[0045] Figure 5 is a schematic diagram of the structure of a doping region provided in an embodiment;

[0046] Figure 6 A schematic diagram of the structure of a first bit line slot provided in an embodiment;

[0047] Figure 7 is a schematic structural diagram of a passivation protection layer provided in an embodiment;

[0048] Figure 8 is a schematic structural diagram of a second bit line slot provided in an embodiment;

[0049] Fig. 9 is a schematic structural diagram of a metal silicide provided in an embodiment;

[0050] Fig.10 FIG. 1 is a schematic structural diagram of a bit line conductive layer provided in an embodiment.

[0051] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0052] Description of reference numerals:

[0053] 100-substrate; 110-semiconductor column; 120-doped region; 120a-first doped region; 120b-first doped region; 130-first bit line groove; 131-passivation protection layer; 132-passivation material layer; 140-second bit line groove; 200-insulating dielectric layer; 200a-first dielectric layer; 200b-second dielectric layer; 300-bit line; 310-metal silicide; 320-bit line conductive layer. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, groove or portion discussed below may be represented as a second element, component, region, layer, groove or portion; for example, a first bit line groove may be referred to as a second bit line groove, and similarly, a second bit line groove may be referred to as a first bit line groove; the first bit line groove and the second bit line groove are different bit line grooves.

[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, and variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

[0060] In one embodiment, see Figure 1 , a method for preparing a semiconductor structure is provided, comprising the following steps:

[0061] Step S100, see Figures 2 to 4 , providing a substrate, the substrate includes a substrate 100 and an insulating dielectric layer 200, a plurality of grooves extending along a first direction are formed in the substrate 100, the substrate 100 on both sides of the grooves forms a semiconductor column 110, and the insulating dielectric layer 200 is located on the sidewall and top of the semiconductor column 110.

[0062] Step S200, see Figure 5 , through the trench, the substrate 100 at the bottom of the semiconductor column 110 is doped to form a doped region 120 .

[0063] Step S300, see Figure 6 , the doped region 120 at the bottom of the trench is etched to form a plurality of first bit line grooves 130 spaced apart from each other in the doped region 120 .

[0064] Step S500, see Figure 8 , etching the substrate 100 below the first bit line groove 130 to form a second bit line groove 140 extending along a second direction, wherein the second direction and the first direction have an included angle, and the second bit line groove 140 connects the plurality of first bit line grooves 130 .

[0065] Step S600, see Fig.10 , a bit line 300 is formed in the first bit line trench 130 and the second bit line trench 140 .

[0066] In step S100, refer to Figures 2 to 4 The substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator, or silicon germanium on insulator. Therefore, the type of the substrate 100 should not limit the scope of protection of the present disclosure.

[0067] The groove in the substrate 100 can be formed by etching the substrate 100 along the first direction, and there can be multiple grooves. After etching, the substrate 100 located on both sides of the groove forms a semiconductor column 110. Similarly, there can be multiple semiconductor columns 110. As an example, multiple semiconductor columns 110 can be arranged in parallel and at equal intervals in a row. This application does not limit the number of grooves and semiconductor columns.

[0068] The material of the insulating dielectric layer 200 may include but is not limited to any one or more of silicon dioxide, silicon nitride, silicon oxynitride, etc. Meanwhile, the insulating dielectric layer 200 may be formed by a deposition process. The deposition process may include but is not limited to one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-coating insulating dielectric layer process.

[0069] The insulating dielectric layer 200 can be formed by different deposition processes or materials. Figure 3 and Figure 4 The insulating dielectric layer 200 may include a first dielectric layer 200a and a second dielectric layer 200b. The first dielectric layer 200a may be located on the top of the semiconductor column 110, and the second dielectric layer 200b may be located on the sidewall of the semiconductor column 110. The first dielectric layer 200a and the second dielectric layer 200b may be formed using different deposition processes and materials.

[0070] The insulating dielectric layer 200 can protect the semiconductor pillar 110 when doping ions and etching the first bit line groove 130 and the second bit line groove 140. At the same time, the insulating dielectric layer 200 can cover the semiconductor pillar 110 along the second direction to enhance the stability of the semiconductor pillar 110.

[0071] In step S200, refer to Figure 5 The doping method may be solid diffusion doping, gas diffusion doping, ion implantation doping and other methods, and the present application has no restrictions on this. Similarly, the present application has no restrictions on the type of doped ions. As an example, the doped ions may be As ions, P ions, N ions, etc.

[0072] The doping region 120 is formed in the substrate 100, so that the bit line 300 can contact the bottom of the semiconductor column 110 through the doping region 120, thereby reducing the contact resistance between the bit line 300 and the bottom of the semiconductor column 110. In addition, the doping region 120 can increase the etching rate of the substrate 100, and the first bit line groove 130 and the second bit line groove 140 can be formed more quickly and effectively.

[0073] In step S300, refer to Figure 6The first bit line groove 130 may be at least partially located in the doping region 120 of the substrate 100. The present application does not impose any specific restrictions on the shape, size, and number of the first bit line groove 130.

[0074] The plurality of first bit line grooves 130 are arranged at intervals from each other so as to retain a portion of the doped region 120. The present application does not impose any specific limitation on the intervals between the plurality of first bit line grooves 130.

[0075] In some cases, the doping region 120 may be in contact with the surface of the substrate 100 . In this case, the first bit line groove 130 may be entirely located in the doping region 120 .

[0076] In some cases, the doped region 120 may also be at a distance from the surface of the substrate 100. At this time, in the vertical direction, the first bitline groove 130 may be partially located in the doped region 120 and partially located in the non-doped region of the substrate 100. That is, the bottom of the first bitline groove 130 is located in the doped region 120, and the top may be located in the non-doped region of the substrate 100.

[0077] In step S500, refer to Figure 8 , the second bit line slot 140 can be connected to the first bit line slot 130. An isotropic etching method can be used to form the second bit line slot 140. Specifically, isotropic dry etching can be used, and isotropic wet etching can also be used, which is not limited in this application. Specifically, for example, carbon tetrafluoride and sulfur hexafluoride can be used for dry etching; in some cases, sulfur tetrafluoride can also be used as an etching gas.

[0078] The etching conditions are controlled so that the second bit line groove 140 is connected to the plurality of first bit line grooves 130 along the second direction. The angle between the second direction and the first direction may be perpendicular to the first direction, or may be at other angles. Specifically, for example, 80 degrees or 60 degrees. In some cases, the first direction, the second direction, and the extension direction of the semiconductor pillar 110 may be perpendicular to each other.

[0079] See also Figure 8 The second bit line groove 140 is located in the substrate 100 and is connected to the plurality of first bit line grooves 130 along the second direction, so that the second bit line groove 140 is partially located below the semiconductor pillar 110 and partially located below the trench. The sizes and specific shapes of the first bit line groove 130 and the second bit line groove 140 are not limited here.

[0080] The second bit line trench 140 is at least partially located in the doping region 120 . The present application does not limit the relationship between the bottom of the second bit line trench 140 and the doping region 120 .

[0081] Likewise, in the vertical direction, the second bit line trench 140 may be partially located in the doped region 120 and partially located in the non-doped region of the substrate 100. That is, the top of the second bit line trench 140 is located in the doped region 120, and the bottom of the second bit line trench 140 may be located in the non-doped region of the substrate 100.

[0082] In step S600, refer to Fig. 9 and Fig.10 The bit line 300 can be formed by depositing a bit line metal. After the bit line metal is deposited in the first bit line groove 130 and the second bit line groove 140, the bit line 300 is completed by etching back.

[0083] In this embodiment, the first bit line groove 130 is first formed by etching in the doped region 120, and then the second bit line groove 140 is formed in the substrate 100 to connect the first bit line groove 130, thereby reducing the removal of the doped region 120. After the bit line 300 is formed in the first bit line groove 130 and the second bit line groove 140, there is a remaining doped region 120 between the bottom of the semiconductor column 110 and the bit line 300, and at this time, the contact resistance between the bottom of the semiconductor column 110 and the bit line 300 can be effectively reduced.

[0084] At the same time, since the bit lines are formed in both the first bit line groove 130 and the second bit line groove 140 , the contact area between the bit line 300 and the bottom of the semiconductor pillar 110 is increased, and the contact resistance can be further reduced.

[0085] In one embodiment, see Figure 6 Step S300 includes: etching the doped region 120 at the bottom of the trench in a vertical direction to form a first bit line trench 130 .

[0086] An anisotropic etching method may be used to form the first bitline groove 130. Specifically, an anisotropic dry etching method or an anisotropic wet etching method may be used. Anisotropic etching can prevent the first bitline groove 130 from lateral expansion, thereby better preventing the doped region 120 from being completely removed.

[0087] In one embodiment, the doping region 120 is formed by ion implantation in step 200; the doping region 120 includes a first doping region 120a and a second doping region 120b arranged vertically, the second doping region 120b is located on both sides of the first doping region 120a, and the doping concentration of the first doping region 120a is greater than the doping concentration of the second doping region 120b. In step 300, the bottom of the first bit line groove 130 is located in the first doping region 120a.

[0088] During ion implantation, a target implantation depth may be set. Ideally, at the target implantation depth, the ion concentration of the doping region 120 is the highest, and the doping concentrations on both sides of the target implantation depth decrease in sequence. Of course, during actual implantation, there will be a certain process error in the depth at the maximum doping concentration.

[0089] At this point, as an example, see Figure 5 and Figure 6 , the doping region 120 may include a first doping region 120a and a second doping region 120b arranged vertically. The first doping region 120a may be set within a range having a first preset distance from the target injection depth. The second doping region 120b is located on both sides of the first doping region 120a, and the doping concentration of the first doping region 120a is greater than the doping concentration of the second doping region 120b. The present application does not specifically limit the first preset distance, the size of the first doping region 120a, and the size of the second doping region 120b.

[0090] Also, see Figure 6 When forming the first bit line groove 130 in step S300, the bottom of the first bit line groove 130 may be located in the first doping region 120. For example, the bottom of the first bit line groove 130 may be etched to the target implantation depth. At this time, the subsequently formed bit line 300 has a larger contact area with the region of the doping region 120 with a larger ion concentration, further reducing the contact resistance between the semiconductor pillar 110 and the bit line 300.

[0091] In one embodiment, in step 400 , the top of the second bit line trench 140 is located in the first doping region.

[0092] The second bitline trench 140 is formed by etching the substrate 100 below the first bitline trench 130. Therefore, when the bottom of the first bitline trench 130 is located in the first doping region 120a, the top of the second bitline trench 140 connected to the bottom of the first bitline trench 130 is also located in the first doping region 120a.

[0093] Meanwhile, the top of the second bit line groove 140 below the semiconductor column 110 may also be located in the first doped region 120a. At this time, the subsequently formed bit line 300 has a larger contact area with the region with a higher ion concentration in the doped region 120, which is beneficial to further reduce the contact resistance between the semiconductor column 110 and the bit line 300.

[0094] In one embodiment, see Figure 7 , before step S500, further comprising:

[0095] Step S400 : forming a passivation protection layer 131 on the sidewall of the first bit line trench 130 .

[0096] The passivation protection layer 131 can be used to protect the sidewalls of the first bitline trench 130. When etching the second bitline trench 140, the passivation protection layer 131 can prevent the sidewalls of the first bitline trench 130 from being etched, thereby preventing more doping regions 120 from being removed.

[0097] In one embodiment, see Figure 6 and Figure 7 , which includes in step S400:

[0098] In step S410 , a passivation gas is introduced to form a passivation material layer 132 on the sidewall and the bottom of the first bit line trench 130 .

[0099] In step S420 , the passivation material layer 132 at the bottom of the first bitline trench 130 is removed by etching to form a passivation protection layer 131 .

[0100] The passivation gas may be a gas including fluorocarbon gas, hydrofluorocarbon gas, hydrochlorocarbon gas, hydrochlorofluorocarbon gas, hydrocarbon gas or a combination thereof, which is not limited in the present application. The passivation material layer 132 may be a dense carbon polymer film layer formed by the passivation gas.

[0101] Specifically, as an example, the passivation gas may be carbon tetrafluoride, which dissociates under a strong electric field to form carbon ions, which polymerize to form a dense carbon polymer film attached to the sidewall and bottom of the first bit line groove 130 .

[0102] The passivation material layer 132 at the bottom of the first bitline groove 130 can be etched and removed by using a physical bombardment method to remove the passivation material layer 132 at the bottom. Specifically, an inert gas can be used. Under the action of an external electric field, the inert gas impacts the passivation material layer 132 at a high speed, so that atoms or molecules on the surface of the passivation material layer 132 are separated, thereby achieving the purpose of removing the passivation material layer 132 at the bottom of the first bitline groove 130. Specifically, for example, under high voltage conditions, argon ions can be used to vertically bombard the passivation material layer 132 at the bottom of the first bitline groove 500. The passivation material layer 132 at the bottom of the first bitline groove 500 is removed, and the passivation material layer 132 on the side wall of the first bitline groove 130 is retained, so as to facilitate the subsequent etching of the second bitline groove 140.

[0103] Of course, in other embodiments, the passivation protection layer 131 may be formed by other methods. Specifically, for example, an oxide layer is formed on the sidewall and bottom of the first bit line groove 130 by thermal oxidation. Then, the oxide layer at the bottom of the first bit line groove 130 is removed by etching, and the oxide layer remaining on the sidewall of the first bit line groove 130 forms the passivation protection layer 131.

[0104] In one embodiment, step S500 includes: in the same ion etching chamber, after removing the passivation material layer 132 at the bottom of the first bitline groove 130 , etching the substrate 100 below the first bitline groove 130 to form a second bitline groove 140 extending along the second direction.

[0105] In this embodiment, the substrate can be placed in the same ion etching chamber, the first bit line groove 130 is first etched, and then the passivation material layer 132 at the bottom of the first bit line groove 130 is etched away to form a passivation protection layer 131, and then the second bit line groove 140 is etched, which can effectively improve the process efficiency.

[0106] Of course, etching can also be performed in different process chambers. Specifically, for example, the substrate is placed in a first ion etching chamber to form the first bit line groove 130 by etching, and the substrate is placed in a second ion etching chamber to form the second bit line groove 140 by etching.

[0107] In one embodiment, see Fig. 9 and Fig.10 , in step S600, including:

[0108] In step S610 , a metal silicide 310 is formed on the surface of the first bit line trench 130 and the surface of the second bit line trench 140 .

[0109] In step S620 , a bit line conductive layer 320 is formed on the surface of the metal silicide 310 .

[0110] The metal silicide 310 can reduce the contact resistance between the bit line 300 and the bottom of the semiconductor pillar 110. Specifically, as an example, the metal silicide 310 can be titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, palladium silicide, platinum silicide, cobalt silicide or a combination thereof.

[0111] The bit line conductive layer 320 may be a conductive layer formed by a bit line metal deposited on the surface of the metal silicide 310. Specifically, as an example, the bit line metal may be tungsten / titanium amide, or may be one or more of ruthenium, iridium, platinum, rhodium, and molybdenum. The present application does not specifically limit the specific material combination, concentration, and deposition process of the metal silicide 310 and the bit line conductive layer 320.

[0112] After the bit line conductive layer 320 is formed, etching back can be performed to obtain a relatively flat top surface of the substrate 100, which is convenient for subsequent processes. The present application does not specifically limit the etching back method.

[0113] In this embodiment, by forming a metal silicide 310 and a bit line conductive layer 320 on the surface of the first bit line groove 130 and the surface of the second bit line groove 140, the contact between the bit line 300 and the ions of the doped region 120 is improved, thereby reducing the contact resistance between the bottom of the semiconductor column 110 and the bit line 300, and ultimately improving the performance of the VAGG.

[0114] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0115] Please continue reading Figures 2 to 10 The present invention further provides a semiconductor structure, including: a substrate, a doping region 120 , and a bit line 300 .

[0116] See also Figures 2 to 4 The base includes a substrate 100 and an insulating dielectric layer 200 . The substrate 100 has a plurality of grooves extending along a first direction, and semiconductor pillars 110 are formed on the substrate 100 on both sides of the grooves. The insulating dielectric layer 200 is located on the sidewalls and top of the semiconductor pillars 110 .

[0117] The groove in the substrate 100 can be formed by etching the substrate 100 along the first direction, and there can be multiple grooves. After etching, the substrate 100 located on both sides of the groove forms a semiconductor column 110. Similarly, there can be multiple semiconductor columns 110. As an example, multiple semiconductor columns 110 can be arranged in parallel and at equal intervals in a row. This application does not limit the number of grooves and semiconductor columns.

[0118] The material of the insulating dielectric layer 200 may include, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, and the like.

[0119] See also Figures 5 to 8 The doped region 120 is located in the substrate 100 at the bottom of the semiconductor pillar 110 and the bottom of the trench, and has a plurality of first bit line grooves 130 spaced apart from each other in the doped region 120 .

[0120] In some cases, the doping region 120 may be in contact with the surface of the substrate 100 . In this case, the first bit line groove 130 may be entirely located in the doping region 120 .

[0121] In some cases, the doped region 120 may also be at a distance from the surface of the substrate 100. At this time, in the vertical direction, the first bitline groove 130 may be partially located in the doped region 120 and partially located in the non-doped region of the substrate 100. That is, the bottom of the first bitline groove 130 is located in the doped region 120, and the top may be located in the non-doped region of the substrate 100.

[0122] A second bit line groove 140 extending along a second direction is provided in the substrate 100 below the first bit line groove 130 . The second direction and the first direction form an angle. The second bit line groove is connected to the plurality of first bit line grooves.

[0123] The second bit line trench 140 is at least partially located in the doping region 120 . The present application does not limit the relationship between the bottom of the second bit line trench 140 and the doping region 120 .

[0124] Similarly, in the vertical direction, the second bit line trench 140 may be partially located in the doped region 120 and partially located in the non-doped region of the substrate 100. That is, the top of the second bit line trench 140 is located in the doped region 120, and the bottom of the second bit line trench 140 may be located in the non-doped region of the substrate 100. The present application does not specifically limit the positional relationship between the bottom of the second bit line trench 140 and the doped region 121.

[0125] See also Fig.10 , the bit line 300 is located in the first bit line groove 130 and the second bit line groove 140 .

[0126] In this embodiment, a plurality of first bit line grooves 130 are formed in the semiconductor structure substrate 100 while the second bit line grooves are formed, and the same second bit line groove 140 connects the plurality of first bit line grooves 130. There are doped regions 120 between the first bit line grooves 130, which can effectively reduce the contact resistance between the bottom of the semiconductor pillar 110 and the bit line 300.

[0127] At the same time, since the bit lines are formed in both the first bit line groove 130 and the second bit line groove 140 , the contact area between the bit line 300 and the bottom of the semiconductor pillar 110 is increased, and the contact resistance can be further reduced.

[0128] In some embodiments, the first bit line trench 130 is located at the bottom of the trench between the semiconductor pillars 110 .

[0129] The first bit line groove 130 may be formed at the bottom of the trench between the semiconductor pillars 110 by vertical etching.

[0130] In some embodiments, the doping region 120 is an ion implantation region; the doping region 120 includes a vertically arranged first doping region 120a and a second doping region 120b, the second doping region 120b is located on both sides of the first doping region 120a, the doping concentration of the first doping region 120a is greater than the doping concentration of the second doping region 120b, and the bottom of the first bit line groove 130 is located in the first doping region 120a.

[0131] When the doping region 120 is formed by ion implantation, the ion concentration may reach a peak at the center of the first doping region 120a. The ion concentration gradually decreases from the first doping region 120a to the second doping region 120b. Specifically, the ion concentration of the first doping region 120a may be 3e+20cm- 3 To 8e+17cm- 3 , the ion concentration of the second doping region 120b may be -1.8e+18cm- 3 to -5e+15cm- 3 The above ion concentrations are only examples, and in actual embodiments, there is no limitation on the specific values ​​of the ion concentrations.

[0132] In some embodiments, a top of the second bit line trench is located in the first doping region.

[0133] In some embodiments, see Figure 7 The semiconductor structure further includes a passivation protection layer 131 . The passivation protection layer 131 is located on the sidewall of the first bit line groove 130 .

[0134] The passivation protection layer 131 can be used to protect the sidewalls of the first bitline trench 130. When etching the second bitline trench 140, the passivation protection layer 131 can prevent the sidewalls of the first bitline trench 130 from being etched, thereby preventing more doping regions 120 from being removed.

[0135] In some embodiments, the passivation protection layer 131 includes a polymer layer.

[0136] The polymer layer can be a structure formed by the polymerization of a passivating gas. For example, when carbon tetrafluoride is used as the passivating gas, under the action of a strong electric field, carbon tetrafluoride dissociates and carbon ions polymerize to form carbon chains. At this time, the polymer layer is a carbon polymer layer formed by carbon chains. The above polymer layer is only used as an example. In some cases, the passivating gas can also be a mixed gas, so that the polymer layer is a mixture layer. In actual embodiments, the present application does not limit the composition and thickness of the polymer layer.

[0137] In some embodiments, see Fig. 9 and Fig.10The bit line 300 includes: a metal silicide 310 and a bit line conductive layer 320. The metal silicide 310 is located on the surface of the first bit line groove 130 and the surface of the second bit line groove 140. The bit line conductive layer 320 is located on the surface of the metal silicide 310.

[0138] In this embodiment, by setting the bottom of the first bit line groove 130 in the first doping region 120a, the contact area between the bit line and the ions in the first doping region 120 with a larger concentration is increased, and the contact resistance between the bottom of the semiconductor column 110 and the bit line 300 is reduced, thereby improving the performance of the VAGG.

[0139] In some embodiments, there may be a plurality of bit lines 300 on the substrate, and the plurality of bit lines 300 may extend along the second direction. When the bottom of the semiconductor pillar 110 is a drain, the drain may be connected to the bit line 300 .

[0140] In some embodiments, the semiconductor structure can be applied to a dynamic random access memory transistor. Since the bit line 300 formed by the first bit line groove 130 and the second bit line groove 140 can reduce the contact resistance between the bottom of the semiconductor column 110 and the bit line 300, it is beneficial to the input and output of current, thereby increasing the read and write speed of the dynamic random access memory transistor.

[0141] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A base, comprising a substrate and an insulating dielectric layer, wherein the substrate has a plurality of grooves extending along a first direction, the substrate on both sides of the grooves forms a semiconductor column, and the insulating dielectric layer is located on the sidewall and top of the semiconductor column; a doped region located in the substrate at the bottom of the semiconductor column, wherein the doped region has a plurality of first bit line grooves spaced apart from each other, wherein the substrate below the first bit line groove has a second bit line groove extending along a second direction, wherein the second direction has an angle with the first direction, and the second bit line groove is connected to the plurality of first bit line grooves; A bit line is located in the first bit line slot and the second bit line slot; The second bit line trench is at least partially located in the doped region; The doped region is retained between the bottom of the semiconductor column and the bit line.

2. The semiconductor structure according to claim 1, characterized in that: The first bit line trench is located at the bottom of the trench between the semiconductor pillars.

3. The semiconductor structure according to claim 1, characterized in that: The doping region is an ion implantation region; the doping region comprises a first doping region and a second doping region arranged vertically, the second doping region is located on both sides of the first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the second doping region; The bottom of the first bit line groove is located in the first doping region.

4. The semiconductor structure according to claim 3, characterized in that: A top of the second bit line trench is located in the first doping region.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The passivation protection layer is located on the sidewall of the first bit line groove.

6. The semiconductor structure according to claim 5, characterized in that: The passivation protection layer includes a polymer layer.

7. The semiconductor structure according to claim 1, characterized in that: The bit line comprises: Metal silicide, located on the surface of the first bit line groove and the surface of the second bit line groove; The bit line conductive layer is located on the surface of the metal silicide.

8. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, the substrate comprising a substrate and an insulating dielectric layer, a plurality of grooves extending along a first direction are formed in the substrate, the substrate on both sides of the grooves forms a semiconductor column, and the insulating dielectric layer is located on the sidewall and top of the semiconductor column; doping the substrate at the bottom of the semiconductor column through the trench to form a doped region; Etching the doped region at the bottom of the trench to form a plurality of first bit line grooves spaced apart from each other in the doped region; Etching the substrate below the first bit line groove to form a second bit line groove extending along a second direction, wherein the second direction and the first direction have an included angle, and the second bit line groove is connected to a plurality of the first bit line grooves; forming bit lines in the first bit line groove and the second bit line groove; The second bit line trench is at least partially located in the doped region; The doped region is retained between the bottom of the semiconductor column and the bit line.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The doped region at the bottom of the trench is etched to form a plurality of mutually spaced first bit line grooves in the doped region, including: In the vertical direction, the doped region at the bottom of the trench is etched to form the first bit line trench.

10. The method for preparing a semiconductor structure according to claim 8 or 9, characterized in that: The doping region is formed by ion implantation; the doping region includes a first doping region and a second doping region arranged vertically, the second doping region is located on both sides of the first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the second doping region; the bottom of the first bit line groove is located in the first doping region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: A top of the second bit line trench is located in the first doping region.

12. The method for preparing a semiconductor structure according to claim 8, characterized in that: Before etching the substrate below the first bit line groove to form a second bit line groove extending along the second direction, the method further includes: A passivation protection layer is formed on the sidewall of the first bit line trench.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The forming of a passivation protection layer on the sidewall of the first bit line trench comprises: Passivation gas is introduced to form a passivation material layer on the sidewall and bottom of the first line groove; The passivation material layer at the bottom of the first bit line trench is removed by etching to form the passivation protection layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: In the same ion etching chamber, after the passivation material layer at the bottom of the first bit line groove is removed by etching, the substrate below the first bit line groove is etched to form a second bit line groove extending along the second direction.

15. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step of forming bit lines in the first bit line groove and the second bit line groove comprises: forming metal silicide on a surface of the first bit line groove and a surface of the second bit line groove; A bit line conductive layer is formed on the surface of the metal silicide.

Images