Information sending and receiving method and device

Abstract

The present invention provides a method and device for sending and receiving information, wherein the sending method comprises: carrying the configuration information of a control resource set on a physical broadcast channel; wherein the configuration information is used to indicate to a terminal at least one of the following of the control resource set: time domain location information, frequency domain location information; and sending the control resource set to the terminal according to the configuration information. The present invention solves the technical problem in the related art that the time and frequency domain resource location of the control resource set cannot be effectively indicated without affecting the PBCH combined reception, thereby improving the flexibility of data transmission.

Description

[0001] This application is a divisional application of the Chinese patent application with application number "201711148126.3", application date "November 17, 2017", and title "Information sending, receiving method and device". Technical Field

[0002] The present invention relates to the field of communications, and in particular to a method and device for sending and receiving information. Background Art

[0003] In the new generation wireless communication system NR, system information is divided into minimum system information (minimum SI) and other system information (other SI). Among them, the minimum system information is further divided into the "main system information (MIB)" carried on the physical broadcast channel (PBCH) and the "remaining minimum system information (RMSI, remaining minimum SI)" carried on the physical downlink shared channel; the main system information is used to provide basic system parameters of the cell, and the remaining minimum system information is used to provide configuration information related to initial access, such as the sending configuration of the initial access request, the receiving configuration of the initial access response message, etc. Other system information that needs to be broadcast is called other system information.

[0004] RMSI is scheduled by the physical downlink control channel PDCCH and carried on the physical downlink shared channel PDSCH. The time-frequency domain location of the common control resource set CORESET where the RMSI scheduling information is located can be indicated in the PBCH.

[0005] In the NR system, PBCH is carried in the synchronization signal / physical broadcast channel block (SS / PBCH block) and sent. A synchronization cycle contains multiple SS / PBCH blocks. Different SS / PBCH blocks can send synchronized broadcast signals of the same or different beam directions or ports to jointly achieve full coverage of the expected area. PBCHs of different beam directions or ports need to be combined for reception. Therefore, when considering introducing indication information into PBCH, ensure that the information content is the same.

[0006] In order to ensure the flexibility of data transmission, the relationship between the time domain positions of different SS / PBCH blocks and the time domain positions of their corresponding RMSI public control resource sets may be different. There is no effective solution in the relevant technology for effectively indicating the time domain position of the RMSI public control resource set without affecting the PBCH combined reception. Summary of the invention

[0007] The embodiments of the present invention provide a method and device for sending and receiving information, so as to at least solve the technical problem in the related art that the time-frequency domain resource position of the control resource set cannot be effectively indicated without affecting the PBCH combined reception.

[0008] According to one embodiment of the present invention, there is provided an information sending method, comprising: carrying configuration information of a control resource set on a physical broadcast channel; wherein the configuration information is used to indicate to a terminal at least one of the following of the control resource set: time domain position information, frequency domain position information; and sending the control resource set to the terminal according to the configuration information.

[0009] According to one embodiment of the present invention, another information sending method is provided, including: receiving configuration information of a control resource set, wherein the configuration information of the control resource set is carried on a physical broadcast channel, and the configuration information is used to indicate at least one of the following of the control resource set: time domain position information, frequency domain position information; receiving the control resource set according to the configuration information.

[0010] According to another embodiment of the present invention, an information sending device is provided, comprising: a configuration module, used to carry the configuration information of the control resource set on a physical broadcast channel; wherein the configuration information is used to indicate to the terminal at least one of the following of the control resource set: time domain position information, frequency domain position information; and a sending module, used to send the control resource set according to the configuration information.

[0011] According to another embodiment of the present invention, another information receiving device is provided, including: a first receiving module, used to receive configuration information of a control resource set, wherein the configuration information of the control resource set is carried on a physical broadcast channel, and the configuration information is used to indicate at least one of the following of the control resource set: time domain position information, frequency domain position information; a second receiving module, used to receive the control resource set according to the configuration information.

[0012] According to yet another embodiment of the present invention, a storage medium is provided, wherein the storage medium includes a stored program, wherein the program executes any of the above methods when it is run.

[0013] According to yet another embodiment of the present invention, a processor is provided, wherein the processor is used to run a program, wherein the program executes any of the above methods when running.

[0014] Through the present invention, by carrying the configuration information of the control resource set on the physical broadcast channel and sending the control resource set to the terminal according to the configuration information, the technical problem in the related technology that the time-frequency domain resource position of the control resource set cannot be effectively indicated without affecting the PBCH combined reception is solved, and the flexibility of data transmission is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0016] Figure 1 is a flow chart of a method for sending information according to an embodiment of the present invention;

[0017] Figure 2 is a flow chart of an information receiving method according to an embodiment of the present invention;

[0018] Figure 3 is a structural block diagram of an information sending device according to an embodiment of the present invention;

[0019] Figure 4 is a structural block diagram of an information receiving device according to an embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of a synchronization signal block of this embodiment;

[0021] Figure 6 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 1 ;

[0022] Figure 7 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 2 ;

[0023] Figure 8 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 3 ;

[0024] Fig. 9 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 4 ;

[0025] Fig.10 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 5 ;

[0026] Fig.11 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 6 ;

[0027] Fig.12 This is a schematic diagram of a structure in which a CORESET is transmitted only in the time slot where the SSB is located in this embodiment;

[0028] Fig.13 is a schematic diagram of a transmission period using multiple synchronization signal blocks in this embodiment;

[0029] Fig.14 Schematic diagram of mapping of current synchronization signal block (SSB) to time slot in this embodiment;

[0030] Fig.15 This is a schematic diagram of the position information of the symbols occupied by CORESET in the time slot of this embodiment. Figure 1 ;

[0031] Fig.16 This is a schematic diagram of the position information of the symbols occupied by CORESET in the time slot of this embodiment. Figure 2 ;

[0032] Fig.17 This is an example of how CORESET is mapped only to slots other than SSB in this embodiment. Figure 1 ;

[0033] Fig.18 This is an example of how CORESET is mapped only to slots other than SSB in this embodiment. Figure 2 ;

[0034] Fig.19 is a schematic diagram of the embodiment in which CORESET is transmitted only in the time slot containing the synchronization signal block;

[0035] Fig. 20 is a schematic diagram of the embodiment in which the CORESET is transmitted only in a time slot that does not include a synchronization signal block;

[0036] Fig.21 Schematic diagram of the embodiment in which the CORESET transmits both in the time slot containing the synchronization signal block and in the time slot not containing the synchronization signal block;

[0037] Fig. 22 This is a schematic diagram of the CORESET in this embodiment transmitting only in the time slot where the synchronization signal block is located;

[0038] Fig.23 In this embodiment, CORESET transmits only in the time slot not including the synchronization signal block. Figure 1 ;

[0039] Fig.24 In this embodiment, CORESET transmits only in the time slot not including the synchronization signal block. Figure 2 ;

[0040] Fig.25 It is a schematic diagram of the same CORESET monitoring window corresponding to all synchronization signal blocks in this embodiment;

[0041] Fig.26 This is a schematic diagram of a CORESET monitoring window in which multiple synchronization signal blocks correspond to one CORESET monitoring window in this embodiment. DETAILED DESCRIPTION

[0042] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0044] Example 1

[0045] The network architecture in which the embodiments of the present application can operate includes: a base station and a terminal, wherein information is exchanged between the base station and the terminal.

[0046] In this embodiment, a method for sending information running on the above network architecture is provided. Figure 1 is a flow chart of a method for sending information according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0047] Step S102, carrying configuration information of the control resource set on a physical broadcast channel; wherein the configuration information is used to indicate to the terminal at least one of the following of the control resource set: time domain position information, frequency domain position information;

[0048] Step S104: Send a control resource set to the terminal according to the configuration information.

[0049] Through the above steps, by carrying the configuration information of the control resource set on the physical broadcast channel and sending the control resource set to the terminal according to the configuration information, the technical problem in the related technology that the time-frequency domain resource position of the control resource set cannot be effectively indicated without affecting the PBCH combined reception is solved, and the flexibility of data transmission is improved.

[0050] Optionally, the execution entity of the above steps may be a network side, such as a base station, etc., but is not limited thereto.

[0051] Optionally, the configuration information of the control resource set includes: bandwidth information of the control resource set.

[0052] Optionally, the bandwidth information includes at least one of the following: minimum channel bandwidth, minimum terminal bandwidth.

[0053] Optionally, the configuration information of the control resource set includes: frequency domain position information of the control resource set, wherein the frequency domain position information is indicated by a frequency offset between the control resource set and a synchronization signal block.

[0054] Optionally, the frequency domain location information of the control resource set is indicated by one of the following:

[0055] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is M×SC SSB ;

[0056] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET -BW SSB ) / 2-M×SC SSB ;

[0057] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET -BW SSB ) / 2-(12×SC CORESET -M×SC SSB );

[0058] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET +BW SSB ) / 2+M×SC SSB ;

[0059] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET +BW SSB ) / 2+(12×SC CORESET +M×SC SSB );

[0060] Where M is the frequency domain offset between the synchronization signal block and the carrier physical resource block grid PRB grid. The number of synchronization signal block subcarriers, M is an integer, SC CORESET To control the frequency domain width of the resource set subcarrier, SC SSB BW is the frequency domain width of the synchronization signal block subcarrier. CORESET To control the resource aggregation bandwidth, BW SSB is the synchronization signal block bandwidth.

[0061] Optionally, the configuration information of the control resource set includes time domain location information of the control resource set; wherein the time domain location information includes at least one of the following information: time slot information where the control resource set is located, and location information of symbols occupied by the control resource set in the time slot.

[0062] Optionally, the position information of the symbols occupied by the control resource set in the time slot includes: the starting symbol index of the symbols occupied by the control resource set in the time slot, and the number of symbols occupied by the control resource set in the time slot.

[0063] Optionally, the time slot information where the control resource set is located includes one of the following:

[0064] The control resource set is transmitted in a time slot including a synchronization signal block;

[0065] Control resource sets to be transmitted in time slots not including synchronization signal blocks;

[0066] The control resource set is transmitted both in the time slot containing the synchronization signal block and in the time slot not containing the synchronization signal block.

[0067] Optionally, the configuration information of the control resource set is also used to indicate: whether the control resource set is transmitted in a time slot containing a synchronization signal block; or whether the control resource set is transmitted in a time slot not containing a synchronization signal block.

[0068] Optionally, when the control resource set is transmitted both in a time slot including a synchronization signal block and in a time slot not including a synchronization signal block, the control resource set adopts the same resource mapping rule in the time slot including the synchronization signal block and in the time slot not including the synchronization signal block.

[0069] Optionally, the configuration information of the control resource set includes monitoring window configuration information of the control resource set, wherein the monitoring window configuration information of the control resource set includes at least one of the following information: the monitoring period of the control resource set, the time domain length of the monitoring window, the time domain offset between adjacent monitoring windows, and the starting monitoring window position, wherein the monitoring window of the control resource set includes one or more control resource set monitoring opportunities.

[0070] Optionally, the monitoring window of the control resource set corresponds to the synchronization signal block.

[0071] Optionally, the time domain length of the monitoring window of the control resource set is greater than or equal to 1 time slot.

[0072] Optionally, the time domain offset between adjacent monitoring windows includes one or more of the following: 0, the time domain length of the monitoring window, 1 / X of the time domain length of the monitoring window, where X is an integer greater than 1, and the value of X is predefined by a predetermined protocol or indicated by signaling.

[0073] Optionally, when the time domain length of the monitoring window of the control resource set is 1 time slot, the time domain offset between adjacent monitoring windows is the time domain length of the monitoring window, or 1 / X of the time domain length of the monitoring window; when the time domain length of the monitoring window of the control resource set is greater than 1 time slot, the time domain offset between adjacent monitoring windows is 0, or 1 / X of the time domain length of the monitoring window.

[0074] Optionally, the starting monitoring window position is indicated by a time domain offset from a starting time slot of a synchronization time block, or the starting monitoring window position is fixedly configured.

[0075] Optionally, the control resource set is one of the following: a remaining minimum system information (RMSI) common control resource set and a paging information common control resource set.

[0076] In this embodiment, a method for receiving information running on the above network architecture is provided. Figure 2 is a flow chart of an information receiving method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0077] Step S202, receiving configuration information of a control resource set, wherein the configuration information of the control resource set is carried on a physical broadcast channel, and the configuration information is used to indicate at least one of the following of the control resource set: time domain position information, frequency domain position information;

[0078] Step S204: receiving a control resource set according to the configuration information.

[0079] Optionally, the configuration information of the control resource set includes: bandwidth information of the control resource set.

[0080] Optionally, the configuration information of the control resource set includes: frequency domain position information of the control resource set, wherein the frequency domain position information is indicated by a frequency offset between the control resource set and a synchronization signal block.

[0081] Optionally, the frequency domain location information of the control resource set is indicated by one of the following:

[0082] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is M×SC SSB ;

[0083] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET -BW SSB ) / 2-M×SC SSB ;

[0084] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET -BWSSB ) / 2-(12×SC CORESET -M×SC SSB );

[0085] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET +BW SSB ) / 2+M×SC SSB ;

[0086] The offset between the center frequency of the control resource set and the center frequency of the synchronization signal block is (BW CORESET +BW SSB ) / 2+(12×SC CORESET +M×SC SSB );

[0087] Where M is the frequency domain offset between the synchronization signal block and the carrier physical resource block grid PRB grid. The number of synchronization signal block subcarriers, M is an integer, SC CORESET To control the frequency domain width of the resource set subcarrier, SC SSB BW is the frequency domain width of the synchronization signal block subcarrier. CORESET To control the resource aggregation bandwidth, BW SSB is the synchronization signal block bandwidth.

[0088] Optionally, the configuration information of the control resource set includes time domain location information of the control resource set; wherein the time domain location information includes at least one of the following information: time slot information where the control resource set is located, and location information of symbols occupied by the control resource set in the time slot.

[0089] Optionally, the configuration information of the control resource set includes monitoring window configuration information of the control resource set, wherein the monitoring window configuration information of the control resource set includes at least one of the following information: the monitoring period of the control resource set, the time domain length of the monitoring window, the time domain offset between adjacent monitoring windows, and the starting monitoring window position, wherein the monitoring window of the control resource set includes one or more control resource set monitoring opportunities.

[0090] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0091] Example 2

[0092] In the present embodiment, a device for sending and receiving information is also provided, and the device is used to implement the above-mentioned embodiment and preferred implementation mode, and the descriptions have been made no further. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0093] Figure 3 is a structural block diagram of an information sending device according to an embodiment of the present invention, which can be applied to network side network elements, such as base stations, etc. Figure 3 As shown, the device comprises:

[0094] The configuration module 30 is used to carry the configuration information of the control resource set on the physical broadcast channel; wherein the configuration information is used to indicate to the terminal at least one of the following of the control resource set: time domain position information, frequency domain position information;

[0095] The sending module 32 is used to send the control resource set according to the configuration information.

[0096] Figure 4 is a structural block diagram of an information receiving device according to an embodiment of the present invention, which can be applied to a terminal such as Figure 4 As shown, including:

[0097] The first receiving module 40 is configured to receive configuration information of a control resource set, wherein the configuration information of the control resource set is carried on a physical broadcast channel, and the configuration information is used to indicate at least one of the following of the control resource set: time domain position information, frequency domain position information;

[0098] The second receiving module 42 is configured to receive the control resource set according to the configuration information.

[0099] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0100] Example 3

[0101] In order to ensure the flexibility of data transmission, the relationship between the time domain positions of different SS / PBCH blocks and the time domain positions of their corresponding RMSI public control resource sets may be different. How to effectively indicate the time domain position of the RMSI public control resource set without affecting the PBCH combined reception is a problem that must be considered and solved.

[0102] In the new generation wireless communication system NR, system information is divided into minimum system information (minimum SI) and other system information (other SI). Among them, the minimum system information is further divided into the "main system information (MIB)" carried on the physical broadcast channel (PBCH) and the "remaining minimum system information (RMSI, remaining minimum SI)" carried on the physical downlink shared channel; the main system information is used to provide basic system parameters of the cell, and the remaining minimum system information is used to provide configuration information related to initial access, such as the sending configuration of the initial access request, the receiving configuration of the initial access response message, etc. Other system information that needs to be broadcast is called other system information.

[0103] RMSI is scheduled by the physical downlink control channel PDCCH and carried on the physical downlink shared channel PDSCH. The time-frequency domain location of the common control resource set CORESET where the RMSI scheduling information is located can be indicated in the PBCH.

[0104] In the NR system, PBCH is carried in the synchronization signal / physical broadcast channel block (SS / PBCH block) and sent. A synchronization cycle contains multiple SS / PBCH blocks. Different SS / PBCH blocks can send synchronized broadcast signals of the same or different beam directions or ports to jointly achieve full coverage of the expected area. PBCHs of different beam directions or ports need to be combined for reception. Therefore, when considering introducing indication information into PBCH, ensure that the information content is the same.

[0105] In order to ensure the flexibility of data transmission, the relationship between the time domain positions of different SS / PBCH blocks and the time domain positions of their corresponding RMSI public control resource sets may be different. How to effectively indicate the time domain position of the RMSI public control resource set without affecting the PBCH combined reception is a problem that must be considered and solved.

[0106] This application provides an information transmission method and system, including the following specific methods:

[0107] The network side carries the control resource set (CORESET, Control Resource Set) configuration information on the physical broadcast channel; wherein the control resource set configuration information is used to indicate the time-frequency domain location information of the control resource set to the terminal;

[0108] The network side sends the control resource set CORESET according to the configuration information.

[0109] The control resource set configuration information includes one or more of the following:

[0110] Bandwidth information of the control resource set;

[0111] Frequency domain location information of the control resource set;

[0112] The time domain location information of the control resource set includes at least one of the following information: the time slot information where the control resource set is located, and the location information of the symbols occupied by the control resource set in the time slot. The location information of the symbols occupied by the control resource set in the time slot includes: the starting symbol index of the symbols occupied by the control resource set in the time slot, and the number of symbols occupied by the control resource set in the time slot.

[0113] Monitoring window configuration information of the control resource set;

[0114] The monitoring window configuration information of the control resource set includes at least one of the following information: the monitoring period of the control resource set, the time domain length of the monitoring window, the time domain offset between adjacent monitoring windows, and the starting monitoring window position.

[0115] In the public control resource set CORESET of this embodiment, one or more of the following downlink control information may be included: paging downlink control information, scheduling information of remaining minimum system information (RMSI, Remaining Minimum System Information), paging indication, etc. Since these information need to achieve full coverage of the expected range, a certain CORESET sends public control information of a specific downlink port / downlink beam direction, and in a polling transmission cycle / CORESET monitoring cycle, one or more CORESETs are included, and public control information is sent in one or more downlink ports / downlink beam directions to achieve coverage of the expected range.

[0116] Paging downlink control information (paging DCI) is used to indicate the scheduling information of the paging message, also known as paging scheduling downlink control information (paging scheduling DCI);

[0117] In the new generation wireless communication system NR, system information is divided into minimum system information (minimum SI) and other system information (other SI). Among them, the minimum system information is further divided into "main system information (MIB)" carried on the physical broadcast channel (PBCH), and "remaining minimum system information (RMSI, remaining minimum SI)" carried on the physical downlink shared channel; the main system information is used to provide basic system parameters of the cell, and the remaining minimum system information is used to provide configuration information related to initial access, such as the sending configuration of the initial access request, the receiving configuration of the initial access response message, etc. Other system information that needs to be broadcast is called other system information (other SI).

[0118] RMSI is scheduled by the physical downlink control channel PDCCH and carried on the physical downlink shared channel PDSCH. The time-frequency domain location of the common control resource set CORESET where the RMSI scheduling information is located can be indicated in the PBCH.

[0119] Paging indicator: used to trigger the terminal to report the downlink preferred beam, also known as paging group indicator.

[0120] Synchronization signal block (SS / PBCH block): used to carry the synchronization signal, physical broadcast channel (and corresponding demodulation reference signal DMRS) and other access-related signal channels, time frequency and resources. Figure 5 Schematic diagram of the synchronization signal block of this embodiment, such as Figure 5 As shown in FIG. 1 , the synchronization signal block usually includes 4 symbols. The first and third symbols carry the primary synchronization signal PSS and the secondary synchronization signal SSS, respectively. The synchronization signal sequences are mapped to 127 resource elements (REs) in 12 physical resource blocks (PRBs), respectively. Figure 5 As shown in (a), in some configurations, the physical broadcast channel PBCH is only carried on the second and fourth symbols in the synchronization signal block, occupying 24 PRBs, or, in other resource configurations, the physical broadcast channel PBCH is mapped on the second, third and fourth symbols in the synchronization signal block, and the number of PRBs occupied on each symbol is as follows: 20 PRBs are occupied on the second and fourth symbols, and on the third symbol, PBCH occupies 4 PRBs on both sides of the secondary synchronization signal, for a total of 8 PRBs. In the above configuration, the synchronization signal is aligned with the center frequency of the PBCH.

[0121] This embodiment also includes the following implementation modes:

[0122] Implementation 1:

[0123] This implementation describes the indication of bandwidth information of CORESET, which is specifically described as follows:

[0124] The bandwidth information of the control resource set included in the control resource set configuration information may be a minimum channel bandwidth or a minimum terminal bandwidth;

[0125] Among them, the minimum channel bandwidth is defined as the minimum bandwidth supported by the system within a certain frequency band. For example, in the frequency range below 6 GHz, the minimum channel bandwidth is defined as 5 MHz; in the frequency range above 6 GHz, the minimum channel bandwidth is defined as 50 MHz.

[0126] The minimum terminal bandwidth refers to the maximum value of the bandwidth supported by all terminals.

[0127] For the indication of the CORESET bandwidth information, 1 bit may be included on the physical broadcast channel to indicate whether the CORESET bandwidth of the current carrier is the minimum channel bandwidth or the minimum terminal bandwidth. For example, 0 represents that the CORESET bandwidth of the current carrier is the minimum channel bandwidth, and 1 represents that the CORESET bandwidth of the current carrier is the minimum terminal bandwidth.

[0128] Alternatively, the CORESET bandwidth is predefined based on the frequency band, for example, the CORESET bandwidth of a certain frequency band is equal to the minimum channel bandwidth or the minimum terminal bandwidth as specified in the protocol. Alternatively, the specific CORESET bandwidth value of a specific frequency band is given in the protocol, for example, 24PRB (physical transport block), 48PRB, etc. In this case, there is no need to introduce a bandwidth indication bit separately.

[0129] Alternatively, the CORESET bandwidth is implicitly indicated by the number of symbols occupied by the control resource set in the time slot. For example, the number of symbols occupied by the CORESET in the time slot is 1, corresponding to the CORESET bandwidth of 48PRB; when the number of symbols occupied by the CORESET in the time slot is 2, the CORESET bandwidth is 24PRB. In this case, there is no need to introduce a bandwidth indication bit separately.

[0130] Implementation 2:

[0131] This embodiment describes the indication of CORESET frequency domain location information, which is described as follows:

[0132] The control resource set configuration information includes frequency domain position information of the control resource set; the frequency domain position is indicated by a frequency offset between the control resource set and a synchronization signal block;

[0133] Figure 6In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 1 , Figure 7 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 2 , Figure 8 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 3 , Fig. 9 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 4 , Fig.10 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 5 , Fig.11 In this embodiment, the frequency domain position is indicated by the frequency offset between the control resource set and the synchronization signal block. Figure 6 ,like Figure 6 , 7 As shown in , 8, 9, 10, and 11, the physical resource block PRB boundary of the synchronization signal block may be offset from the actual PRB boundary of the carrier (physical resource block grid (PRB grid)) (as shown by offset). Information bits (such as 4 bits or 5 bits) are introduced into the physical broadcast channel to explicitly indicate the above offset, and the offset can be predefined as the offset between the physical resource block PRB boundary of the synchronization signal block and the PRB boundary of the carrier with a lower frequency (i.e., as shown by Figure 6 , 8 , 10), or the offset between the physical resource block PRB boundary of the synchronization signal block and the higher frequency carrier PRB boundary (i.e., as shown in Figure 7 , 9 , 11); and there is no offset between the transmission of CORESET and the actual PRB boundary of the carrier. Therefore, when the frequency offset between the synchronization signal block and the CORESET is used to indicate the frequency domain position of the CORESET, this offset needs to be taken into account. The following describes the indication method of the frequency domain position of the CORESET when the subcarrier spacing of the CORESET is equal to, less than or greater than the subcarrier spacing of the synchronization signal block:

[0134] When the subcarrier spacing of the CORESET is equal to the subcarrier spacing of the synchronization signal block (for example, the subcarrier spacing of the CORESET and the synchronization signal block are both 15kHz), Figure 6 , 7As shown, at this time, within the carrier physical resource block grid (PRBgrid), a carrier PRB contains 12 synchronization signal block subcarriers in the frequency domain. Therefore, there are 12 possible offset values, that is, the offset value range is 0 to 11 subcarriers, and the specific offset amount (that is, the offset value) is indicated by 4 bits in the PBCH.

[0135] like Figure 8 , 9 As shown, when the subcarrier spacing of the CORESET is smaller than the subcarrier spacing of the synchronization signal block (for example, the subcarrier spacing of the CORESET is 15kHz, and the subcarrier spacing of the synchronization signal block is 30kHz), the carrier physical resource block grid (PRB grid) is defined by the larger subcarrier spacing (30kHz), and the smaller subcarrier is nested in the larger subcarrier, that is, one 30kHz subcarrier corresponds to two 15kHz subcarriers in the frequency domain. At this time, within the carrier physical resource block grid (PRB grid), one carrier PRB contains 12 synchronization signal block subcarriers in the frequency domain, and the offset offset ranges from 0 to 11 synchronization signal block (30kHz) subcarriers, and the specific offset amount (i.e., the value of the offset) is indicated by 4 bits in the PBCH.

[0136] like Fig.10 , 11 As shown, when the subcarrier spacing of the CORESET is larger than the subcarrier spacing of the synchronization signal block (for example, the subcarrier spacing of the CORESET is 30kHz, and the subcarrier spacing of the synchronization signal block is 15kHz), the carrier physical resource block grid (PRB grid) is defined by the larger subcarrier spacing (30kHz), and the smaller subcarrier is nested in the larger subcarrier, that is, one 30kHz subcarrier corresponds to two 15kHz subcarriers in the frequency domain. At this time, in the carrier physical resource block grid (PRB grid), one carrier PRB contains 24 synchronization signal block subcarriers in the frequency domain, and the offset offset ranges from 0 to 23 synchronization signal block (30kHz) subcarriers, and the specific offset amount (that is, the value of the offset) is indicated by 5 bits in the PBCH.

[0137] Sub-implementation 2.1:

[0138] When the offset is defined as the offset between the physical resource block (PRB) boundary of the synchronization signal block and the PRB boundary of the carrier with a lower frequency (i.e. Figure 6 , 8 , 10), the frequency domain position of the CORESET is one of the following frequency domain position situations:

[0139] Case 1: The low frequency boundary of the CORESET is M 15kHz subcarriers lower than the low frequency boundary of the synchronization signal block; at this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET -BW SSB ) / 2-M×SC SSB ;

[0140] Case 2: The high frequency boundary of the CORESET is 12×SC higher than the high frequency boundary of the synchronization signal block CORESET -M×SC SSB ; At this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET -BW SSB ) / 2-(12×SC CORESET -M×SC SSB );

[0141] Case 3: The center frequency of the CORESET is offset from the center frequency of the synchronization signal block by M 15kHz subcarriers; that is, the absolute offset between the center frequencies is M×SC SSB .

[0142] Case 4: The high frequency boundary of the CORESET is M 15kHz subcarriers lower than the low frequency boundary of the synchronization signal block; at this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET +BW SSB ) / 2+M×SC SSB .

[0143] Case 5: The low frequency boundary of the CORESET is 12×SC higher than the high frequency boundary of the synchronization signal block CORESET -M×SC SSB ; At this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET +BW SSB ) / 2+(12×SC CORESET -M×SC SSB );

[0144] Wherein, M is the number of subcarriers of the frequency domain offset synchronization signal block between the synchronization signal block and the PRB boundary, M is an integer, and when the subcarrier spacing of the CORESET is less than or equal to the subcarrier spacing of the synchronization signal block, the value range of M is: 0≤M≤11. When the subcarrier spacing of the CORESET is greater than the subcarrier spacing of the synchronization signal block, the value range of M is: 0≤M≤23. SC CORESET To control the frequency domain width of the resource set subcarrier, SC SSB BW is the frequency domain width of the synchronization signal block subcarrier. CORESET To control the resource aggregation bandwidth, BW SSB is the synchronization signal block bandwidth.

[0145] In the above five cases, in cases 1, 2, and 3, the frequency domain range of CORESET includes the frequency domain range of the synchronization signal block; in cases 4 and 5, the frequency domain range of CORESET and the frequency domain range of the synchronization signal block do not overlap with each other.

[0146] Sub-implementation 2.2:

[0147] Figure 7 , 9 , 11 describes the case where the offset offset is the offset between the physical resource block PRB boundary of the synchronization signal block and the carrier PRB boundary of the higher frequency, and Figure 6 Similar to the situation described, there are the following situations:

[0148] Case 1: The low frequency boundary of the CORESET is 12×SC lower than the low frequency boundary of the synchronization signal block CORESET -M×SC SSB ; At this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET -BW SSB ) / 2-(12×SC CORESET -M×SC SSB ).

[0149] Case 2: The high frequency boundary of the CORESET is M×SC higher than the high frequency boundary of the synchronization signal block SSB , i.e., M synchronization signal block subcarriers; at this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET -BW SSB ) / 2-M×SC SSB ;

[0150] Case 3: The center frequency of the CORESET is offset from the center frequency of the synchronization signal block by M 15kHz subcarriers; that is, the absolute offset between the center frequencies is M×SC SSB .

[0151] Case 4: The high frequency boundary of the CORESET is 12×SC lower than the low frequency boundary of the synchronization signal block CORESET -M×SC SSB ; At this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET +BW SSB ) / 2+(12×SC CORESET -M×SC SSB ).

[0152] Case 5: The low frequency boundary of the CORESET is M×SC higher than the high frequency boundary of the synchronization signal block SSB , i.e., M synchronization signal block subcarriers; at this time, the offset between the center frequency of the CORESET and the center frequency of the synchronization signal block is: (BW CORESET +BW SSB ) / 2+M×SC SSB ;

[0153] Wherein, M is the number of subcarriers of the frequency domain offset synchronization signal block between the synchronization signal block and the PRB boundary, M is an integer, and when the subcarrier spacing of the CORESET is less than or equal to the subcarrier spacing of the synchronization signal block, the value range of M is: 0≤M≤11. When the subcarrier spacing of the CORESET is greater than the subcarrier spacing of the synchronization signal block, the value range of M is: 0≤M≤23. SC CORESET To control the frequency domain width of the resource set subcarrier, SC SSB BW is the frequency domain width of the synchronization signal block subcarrier. CORESET To control the resource aggregation bandwidth, BW SSB is the synchronization signal block bandwidth.

[0154] In the above five cases, in cases 1, 2, and 3, the frequency domain range of CORESET includes the frequency domain range of the synchronization signal block; in cases 4 and 5, the frequency domain range of CORESET and the frequency domain range of the synchronization signal block do not overlap with each other.

[0155] In the CORESET frequency domain position above, any one or more optional positions can be specified in the protocol, and an indication bit can be introduced in the CORESET configuration information indication field of the PBCH to indicate the frequency domain position of the CORESET of the current carrier to the terminal. For example, the protocol specifies that the frequency domain position of the CORESET includes the following four types: case1, case2, case4, and case5. 2 bits are used in the PBCH to indicate which configuration of the above four frequency domain positions is currently used.

[0156] Or, as defined below, since in case 1 and case 2, the bandwidth of CORESET overlaps with the synchronization signal block, it is more suitable for the case where the subcarrier spacing of the two is the same. On the contrary, in case 4 and case 5, the bandwidth of CORESET and the synchronization signal block do not overlap with each other, which is more suitable for the case where the subcarrier spacing of the two is different. Therefore, the protocol stipulates that when the subcarrier spacing of CORESET and the synchronization signal block is the same, 1 bit is introduced in PBCH to indicate which configuration of the frequency domain position of case 1 and case 2 is currently used; when the subcarrier spacing of CORESET and the synchronization signal block is different, 1 bit is introduced in PBCH to indicate which configuration of the frequency domain position of case 4 and case 5 is currently used.

[0157] Implementation 3:

[0158] This embodiment describes a method for indicating the time slot information where the control resource set is located;

[0159] The time slot information of the CORESET has the following three situations:

[0160] 1. The CORESET is transmitted only in the time slot containing the synchronization signal block (such as Fig.12 As shown in (a), Fig.12 This is a structural diagram of a CORESET in this embodiment that is transmitted only in the time slot where the SSB is located: that is, in one time slot, two synchronization signal blocks SSB1 and SSB2 are included, and the CORESET corresponding to each is in the symbol before the symbol occupied by the SSB);

[0161] 2. The CORESET is transmitted both in the time slot containing the synchronization signal block and in the time slot not containing the synchronization signal block (e.g. Fig.12 (b) is a schematic diagram of a structure in which a CORESET is transmitted both in the time slot where the SSB is located and in the time slot that does not contain the synchronization signal block: that is, in a time slot, two synchronization signal blocks SSB1 and SSB2 are included, the CORESET corresponding to SSB2 is in the symbol before the symbol occupied by SSB, and the CORESET corresponding to SSB1 is transmitted in the time slot that does not contain SSB);

[0162] 3. The CORESET is transmitted only in the time slot that does not contain the synchronization signal block (such as Fig.12 (c) shows a structure in which CORESET is transmitted only in a time slot that does not contain SSB: that is, in a time slot that does not contain SSB, CORESET is mapped to the first and seventh symbols in the time slot respectively).

[0163] like Fig.13 As shown, the control resource set is transmitted only in the time slot containing the synchronization signal block. There is another form, that is, using multiple synchronization signal block transmission cycles, Fig.13 is a schematic diagram of the present embodiment using multiple synchronization signal block transmission cycles ( Fig.13 In the example, SS burst set periodicity refers to the transmission period of the synchronization signal block. Two synchronization signal blocks are mapped in one time slot. The CORESET1 corresponding to the first SSB is transmitted in the time slot where SSB1 is located in the first period, and the CORESET2 corresponding to the second SSB is transmitted in the time slot where SSB2 is located in the second period. At this time, the transmission period of CORESET is twice the transmission period of SSB.

[0164] Which SSBs are transmitted in which SS burst set cycle? The CORESETs corresponding to these SSBs may be predefined by the system. For example, in a radio frame with a system frame number SFN mod 4 = 0, the CORESETs corresponding to odd SSBs are included; in a radio frame with a system frame number SFN mod 4 = 2, the CORESETs corresponding to even SSBs are included. Alternatively, in a radio frame with a system frame number SFN mod 4 = 0 or 1, the CORESETs corresponding to odd SSBs are included; in a radio frame with a system frame number SFN mod 4 = 2 or 3, the CORESETs corresponding to even SSBs are included.

[0165] In the CORESET configuration information indication field of PBCH, an indication bit can be introduced to indicate to the terminal the information of the time slot where the CORESET of the current carrier is located. For example, using 2 bits to indicate, '00' represents 'the control resource set is only transmitted in the time slot containing the synchronization signal block', '01' represents 'the control resource set is transmitted in both the time slot containing the synchronization signal block and the time slot not containing the synchronization signal block', '10' represents 'the control resource set is only transmitted in the time slot not containing the synchronization signal block', '11' represents 'the mode of cross-period CORESET transmission (same as Fig.13 correspond)'.

[0166] Alternatively, 1 bit is used to indicate that '0' represents 'the control resource set is transmitted in the time slot containing the synchronization signal block', and '1' represents 'the control resource set is only transmitted in the time slot not containing the synchronization signal block'. In this case, '0' actually contains Fig.12 (a) Fig.12 (b) Fig.13 Three situations are shown.

[0167] Alternatively, 1 bit is used to indicate that '0' represents 'the control resource set is transmitted only in the time slot containing the synchronization signal block'; '1' represents 'the control resource set is transmitted in the time slot not containing the synchronization signal block'. In this case, '0' actually includes Fig.12 (a) and Fig.13 Two cases; '1' actually contains Fig.12 (b) and Fig.12 (c) Two cases

[0168] Alternatively, the protocol specifies that only any two of the above four situations are included, and 1 bit is further used in the PBCH to indicate which specific configuration is adopted by the current carrier.

[0169] Implementation 4:

[0170] This embodiment describes a method for indicating the position information of the symbols occupied by the CORESET in the time slot;

[0171] The position information of the symbols occupied by the CORESET in the time slot includes: the starting symbol index of the symbols occupied by the CORESET in the time slot, and the number of symbols occupied by the CORESET in the time slot.

[0172] like Fig.14 As shown, Fig.14 Schematic diagram of mapping the current synchronization signal block (SSB) to the time slot in this embodiment, wherein: Fig.14 (a) is applicable to the mapping of synchronization signal blocks with a subcarrier spacing of 15 kHz or 30 kHz (pattern 2) to time slots; Fig.14 (b) is applicable to the mapping of synchronization signal blocks with a subcarrier spacing of 30 kHz (pattern 1) or 120 kHz to time slots; Fig.14 (c) is applicable to the mapping of synchronization signal blocks with a subcarrier spacing of 240kHz to time slots. Fig.14 (a) and Fig.14 In (b), the slots are all time slots corresponding to the subcarrier spacing of the current synchronization signal block; Fig.14 The slot in (c) corresponds to a time slot of 120kHz.

[0173] Sub-implementation 4.1:

[0174] for Fig.14 The 15kHz or 30kHz (pattern 2) synchronization signal block mapping shown in (a) is as follows: Fig.15 This is a schematic diagram of the position information of the symbols occupied by CORESET in the time slot of this embodiment. Figure 1 ,like Fig.15 As shown, the position information of the symbol occupied by the CORESET in the time slot includes one or more of the following, wherein the arrow starting from the SSB points to the CORESET corresponding to it:

[0175] exist Fig.15 (1) In the configuration, each CORESET occupies 1 symbol and is mapped in the same slot. The SSB specifically occupies the symbol before the SSB, that is, the CORESET corresponding to the first SSB in the slot occupies the second symbol in the slot, and the CORESET corresponding to the second SSB in the slot occupies the eighth symbol in the slot;

[0176] exist Fig.15 (2) In the configuration, each CORESET occupies 1 symbol, and the CORESET corresponding to the first SSB in the slot is mapped to the 8th symbol of the slot outside the 5ms SSB time window; the CORESET corresponding to the second SSB in the slot is mapped in the slot where the SSB is located, specifically occupying 1 symbol before the SSB, that is, the 8th symbol in the slot;

[0177] exist Fig.15 (3) In the configuration, each CORESET occupies 1 symbol, and the CORESET corresponding to the first SSB in the slot is mapped in the slot where the SSB is located, specifically occupying the symbol before the SSB, that is, the second symbol in the slot; the CORESET corresponding to the second SSB in the slot is mapped on the second symbol of the slot outside the 5ms SSB time window;

[0178] exist Fig.15 (4) In the configuration, each CORESET occupies one symbol and is mapped in the slot where the SSB is located. The SSB specifically occupies the first two symbols in the slot, that is, the CORESET corresponding to the first SSB in the slot occupies the first symbol in the slot, and the CORESET corresponding to the second SSB in the slot occupies the second symbol in the slot;

[0179] exist Fig.15(5) In the configuration, each CORESET occupies 2 symbols, and the CORESET corresponding to the first SSB in the slot is mapped in the slot where the SSB is located, specifically occupying the first 2 symbols of the slot where the SSB is located; the CORESET corresponding to the second SSB in the slot is mapped on the 1st and 2nd symbols of the slot outside the 5ms SSB time window;

[0180] exist Fig.15 (6) In the configuration, each CORESET occupies 2 symbols, and the CORESET corresponding to the first SSB in the slot is mapped to the 7th and 8th symbols of the slot outside the 5ms SSB time window; the CORESET corresponding to the second SSB in the slot is mapped in the slot where the SSB is located, specifically occupying the 7th and 8th symbols of the slot where the SSB is located;

[0181] exist Fig.15 (7) In the configuration, each CORESET occupies 2 symbols, and the CORESET corresponding to the first SSB in the slot is mapped to the 1st and 2nd symbols of the slot outside the 5ms SSB time window; the CORESET corresponding to the second SSB in the slot is mapped in the slot where the SSB is located, specifically occupying the 7th and 8th symbols of the slot where the SSB is located;

[0182] exist Fig.15 (8) In the configuration, each CORESET occupies 2 symbols and is mapped in the same slot. The SSB specifically occupies the two symbols before the SSB, that is, the CORESET corresponding to the first SSB in the slot occupies the 1st and 2nd symbols in the slot, and the CORESET corresponding to the second SSB in the slot occupies the 7th and 8th symbols in the slot.

[0183] exist Fig.15(9) In the configuration, each CORESET occupies 1, 2, 3, or 4 symbols, and the CORESET and the corresponding SSB adopt FDM multiplexing, that is, the CORESET corresponding to the first SSB in the slot is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 3rd symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 3rd and 4th symbols. For a three-symbol CORESET, it occupies the 3rd, 4th, and 5th symbols. For a four-symbol CORESET, it occupies the 3rd, 4th, 5th symbols. For a four-symbol CORESET, it occupies the 3rd, 4th, 5th, and 6th symbols. The CORESET corresponding to the second SSB in the slot is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 9th symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 9th and 10th symbols. For a three-symbol CORESET, it occupies the 9th, 10th, and 11th symbols. For a four-symbol CORESET, it occupies the 9th, 10th, 11th, and 12th symbols. In the frequency domain, it occupies resources other than the SSB.

[0184] exist Fig.15 (10) In the configuration, each CORESET occupies 1, 2, 3 or 4 symbols, and the CORESET and the corresponding SSB adopt FDM multiplexing mode, that is, the CORESET corresponding to the first SSB in the slot is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 3rd symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 3rd and 4th symbols. For a three-symbol CORESET, it occupies the 3rd, 4th and 5th symbols. For a four-symbol CORESET, it occupies the 3rd, 4th, 5th and 6th symbols; the CORESET corresponding to the second SSB in the slot is mapped to the slot outside the 5ms SSB time window. Specifically, when the CORESET occupies 1 symbol, it occupies the 3rd symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 3rd and 4th symbols. For a three-symbol CORESET, it occupies the 3rd, 4th and 5th symbols. For a four-symbol CORESET, it occupies the 3rd, 4th, 5th symbols. In the frequency domain, it occupies resources other than the frequency domain resources corresponding to the SSB.

[0185] Sub-implementation 4.2:

[0186] for Fig.14 The 30kHz (pattern 1) or 120kHz synchronization signal block mapping shown in (b) is configured with two slots and four SSBs as a period for mapping resources. Fig.16 This is a schematic diagram of the position information of the symbols occupied by CORESET in the time slot of this embodiment. Figure 2,like Fig.16 As shown, the position information of the symbol occupied by the CORESET in the time slot includes one or more of the following, wherein the arrow starting from the SSB points to the CORESET corresponding to it:

[0187] exist Fig.16 (1) In the configuration, each CORESET occupies 1 symbol, where the CORESET of the first SSB occupies the third symbol in the previous slot; the CORESET of the second SSB occupies the fourth symbol in the previous slot; the CORESET of the third SSB occupies the first symbol in the next slot; and the CORESET of the fourth SSB occupies the second symbol in the next slot.

[0188] exist Fig.16 (2) In the configuration, each CORESET occupies 1 symbol, wherein the CORESET of the first SSB occupies the third symbol in the previous slot; the CORESET of the second SSB occupies the fourth symbol in the previous slot; the CORESET of the third SSB occupies the third symbol in the slot outside the 5ms SSB time window; the CORESET of the fourth SSB occupies the fourth symbol in the slot outside the 5ms SSB time window; the 'interval between the CORESET of the first SSB and the CORESET of the third SSB' is equal to the 'interval between the CORESET of the second SSB and the CORESET of the fourth SSB', for example, the intervals are all equal to 5ms.

[0189] exist Fig.16 (3) In the configuration, each CORESET occupies 1 symbol, wherein the CORESET of the first SSB occupies the 4th symbol in the previous slot; the CORESET of the second SSB occupies the 4th symbol in the slot outside the 5ms SSB time window; the CORESET of the third SSB occupies the 4th symbol in the next slot; the CORESET of the fourth SSB occupies the 2nd symbol in the slot outside the 5ms SSB time window; the 'interval between the CORESET of the first SSB and the CORESET of the third SSB' is equal to the 'interval between the CORESET of the second SSB and the CORESET of the fourth SSB', for example, the intervals are all equal to 5ms.

[0190] exist Fig.16(4) In the configuration, each CORESET occupies 1 symbol and is mapped to the first four symbols in the first slot. Specifically, the CORESET of the first SSB occupies the first symbol in the previous slot; the CORESET of the second SSB occupies the second symbol in the previous slot; the CORESET of the third SSB occupies the third symbol in the previous slot; and the CORESET of the fourth SSB occupies the fourth symbol in the previous slot.

[0191] exist Fig.16 (5) In the configuration, each CORESET occupies 2 symbols, among which the CORESET of the first SSB occupies the 1st and 2nd symbols in the previous slot; the CORESET of the second SSB occupies the 3rd and 4th symbols in the previous slot; the CORESET of the third SSB occupies the 1st and 2nd symbols in the slot outside the 5ms SSB time window; the CORESET of the fourth SSB occupies the 3rd and 4th symbols in the slot outside the 5ms SSB time window; the 'time domain interval between the CORESET of the first SSB and the CORESET of the third SSB' is equal to the 'time domain interval between the CORESET of the second SSB and the CORESET of the fourth SSB', for example, the intervals are both equal to 5ms.

[0192] exist Fig.16 (6) In the configuration, each CORESET occupies 2 symbols, among which the CORESET of the first SSB occupies the 3rd and 4th symbols in the previous slot; the CORESET of the second SSB occupies the 1st and 2nd symbols in the next slot; the CORESET of the third SSB occupies the 3rd and 4th symbols in the slot outside the 5ms SSB time window; the CORESET of the fourth SSB occupies the 1st and 2nd symbols in the slot outside the 5ms SSB time window; the 'time domain interval between the CORESET of the first SSB and the CORESET of the third SSB' is equal to the 'time domain interval between the CORESET of the second SSB and the CORESET of the fourth SSB', for example, the intervals are both equal to 5ms.

[0193] exist Fig.16(7) In the configuration, each CORESET occupies 2 symbols, among which the CORESET of the first SSB occupies the 1st and 2nd symbols in the previous slot; the CORESET of the second SSB occupies the 3rd and 4th symbols in the previous slot; the CORESET of the third SSB occupies the 1st and 2nd symbols in the next slot; the CORESET of the fourth SSB occupies the 1st and 2nd symbols in the slot outside the 5ms SSB time window; the 'time domain interval between the CORESET of the first SSB and the CORESET of the fourth SSB' is equal to 5ms.

[0194] exist Fig.16 (8) In the configuration, each CORESET occupies 2 symbols, among which the CORESET of the first SSB occupies the 1st and 2nd symbols in the previous slot; the CORESET of the second SSB occupies the 3rd and 4th symbols in the previous slot; the CORESET of the third SSB occupies the 1st and 2nd symbols in the next slot; the CORESET of the fourth SSB occupies the 1st and 2nd symbols in the slot outside the 5ms SSB time window; the 'time domain interval between the CORESET of the second SSB and the CORESET of the fourth SSB' is equal to 5ms, or, the 'time domain interval between the CORESET of the third SSB and the CORESET of the fourth SSB' is equal to 5ms.

[0195] exist Fig.16 (9) In the configuration, each CORESET occupies 1, 2, 3, or 4 symbols, and the CORESET and the corresponding SSB adopt FDM multiplexing, that is,

[0196] – The CORESET corresponding to the first SSB is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 5th symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 5th and 6th symbols. For a three-symbol CORESET, it occupies the 5th, 6th, and 7th symbols. For a four-symbol CORESET, it occupies the 5th, 6th, 7th, and 8th symbols. In the frequency domain, it occupies resources other than the SSB.

[0197] –The CORESET corresponding to the second SSB is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 9th symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 9th and 10th symbols. For a three-symbol CORESET, it occupies the 9th, 10th, and 11th symbols. For a four-symbol CORESET, it occupies the 9th, 10th, 11th, and 12th symbols. In the frequency domain, it occupies resources other than the SSB.

[0198] – The CORESET corresponding to the third SSB is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 3rd symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 3rd and 4th symbols. For a three-symbol CORESET, it occupies the 3rd, 4th, and 5th symbols. For a four-symbol CORESET, it occupies the 3rd, 4th, 5th, and 6th symbols. In the frequency domain, it occupies resources other than the SSB.

[0199] –The CORESET corresponding to the fourth SSB is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 7th symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 7th and 8th symbols. For a three-symbol CORESET, it occupies the 7th, 8th, and 9th symbols. For a four-symbol CORESET, it occupies the 7th, 8th, 9th, and 10th symbols. In the frequency domain, it occupies resources other than the SSB.

[0200] exist Fig.16 (10) In the configuration, each CORESET occupies 1, 2, 3, or 4 symbols, and the CORESET and the corresponding SSB adopt FDM multiplexing, that is,

[0201] – The CORESET corresponding to the first SSB is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 5th symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 5th and 6th symbols. For a three-symbol CORESET, it occupies the 5th, 6th, and 7th symbols. For a four-symbol CORESET, it occupies the 5th, 6th, 7th, and 8th symbols. In the frequency domain, it occupies resources other than the SSB.

[0202] – The CORESET corresponding to the second SSB is mapped in the slot outside the 5ms SSB time window. Specifically, when the CORESET occupies 1 symbol, it occupies the 5th symbol. For the two-symbol CORESET, it occupies the 5th and 6th symbols. For the three-symbol CORESET, it occupies the 5th, 6th, and 7th symbols. For the four-symbol CORESET, it occupies the 5th, 6th, 7th, and 8th symbols. In the frequency domain, it occupies resources other than the frequency domain resources corresponding to the SSB. And the interval between the CORESET of the first SSB and the CORESET of the third SSB is equal to 5ms.

[0203] – The CORESET corresponding to the third SSB is mapped in the slot where the SSB is located. Specifically, when the CORESET occupies 1 symbol, it occupies the 3rd symbol of the slot where the SSB is located. For a two-symbol CORESET, it occupies the 3rd and 4th symbols. For a three-symbol CORESET, it occupies the 3rd, 4th, and 5th symbols. For a four-symbol CORESET, it occupies the 3rd, 4th, 5th, and 6th symbols. In the frequency domain, it occupies resources other than the SSB.

[0204] – The CORESET corresponding to the fourth SSB is mapped in the slot outside the 5ms SSB time window. Specifically, when the CORESET occupies 1 symbol, it occupies the 7th symbol. For the two-symbol CORESET, it occupies the 7th and 8th symbols. For the three-symbol CORESET, it occupies the 7th, 8th, and 9th symbols. For the four-symbol CORESET, it occupies the 7th, 8th, 9th, and 10th symbols. In the frequency domain, it occupies resources other than the frequency domain resources corresponding to the SSB. And the interval between the CORESET of the second SSB and the CORESET of the fourth SSB is equal to 5ms.

[0205] Sub-implementation 4.3:

[0206] When CORESET is mapped only in slots other than SSB, Fig.17 This is an example of how CORESET is mapped only to slots other than SSB in this embodiment. Figure 1 , Fig.18 This is an example of how CORESET is mapped only to slots other than SSB in this embodiment. Figure 2 ,like Fig.17 , 18 As shown, the position information of the symbols occupied by CORESET in the time slot includes one or more of the following:

[0207] exist Fig.17 (1) In the configuration, a slot contains two CORESETs, each occupying one symbol, located on the first and second symbols in the slot respectively;

[0208] exist Fig.17 (2) In the configuration, a slot contains two CORESETs, each occupying two symbols. Specifically, one CORESET is mapped to the 1st and 2nd symbols in the slot, and the other CORESET is mapped to the 3rd and 4th symbols in the slot;

[0209] exist Fig.17 (3) In the configuration, a slot contains two CORESETs, each occupying one symbol, located on the first and eighth symbols in the slot respectively;

[0210] exist Fig.17 (4) In the configuration, a slot contains two CORESETs, each occupying two symbols. Specifically, one CORESET is mapped to the 1st and 2nd symbols in the slot, and the other CORESET is mapped to the 8th and 9th symbols in the slot;

[0211] exist Fig.17 (5) In the configuration, a slot contains two CORESETs, each occupying one symbol, located at the 3rd and 9th symbols in the slot respectively;

[0212] exist Fig.17 (6) In the configuration, a slot contains two CORESETs, each occupying two symbols. Specifically, one CORESET is mapped to the 3rd and 4th symbols in the slot, and the other CORESET is mapped to the 9th and 10th symbols in the slot;

[0213] exist Fig.17 (7) In the configuration, a slot contains one CORESET, which occupies one symbol. Specifically, this CORESET is mapped to the first symbol in the slot;

[0214] exist Fig.17 (8) In the configuration, a slot contains one CORESET, which occupies two symbols. Specifically, this CORESET is mapped to the first and second symbols in the slot;

[0215] exist Fig.18 (1) In the configuration, two slots are used as the configuration cycle, which includes 4 CORESETs, and each CORESET contains 1 symbol: the first CORESET is mapped on the 5th symbol of the previous slot, the second CORESET is mapped on the 9th symbol of the previous slot, the third CORESET is mapped on the 3rd symbol of the next slot, and the fourth CORESET is mapped on the 7th symbol of the next slot;

[0216] exist Fig.18 (2) In the configuration, two slots are used as the configuration cycle, which includes 4 CORESETs, and each CORESET includes 2 symbols: the first CORESET is mapped on the 5th and 6th symbols of the previous slot, the second CORESET is mapped on the 9th and 10th symbols of the previous slot, the third CORESET is mapped on the 3rd and 4th symbols of the next slot, and the fourth CORESET is mapped on the 7th and 8th symbols of the next slot;

[0217] In the above configuration, the terminal may be provided with the symbol position occupied by the currently used CORESET in the time slot in the following manner.

[0218] According to the CORESET bandwidth configuration described in implementation mode 1, the terminal can determine the bandwidth of the current CORESET. When the CORESET bandwidth takes the minimum channel bandwidth, since the bandwidth value is relatively small, the CORESET and SSB time division multiplexing method is preferred.

[0219] On the contrary, when the CORESET bandwidth takes a larger value, that is, the minimum UE bandwidth, the CORESET and SSB frequency division multiplexing method is tended to be adopted;

[0220] In addition, the terminal can determine the time slot information where the CORESET is located according to the method described in Implementation 3.

[0221] Define the following three tables: Table 1, Table 2, and Table 3.

[0222] Among them, Table 1 is applicable to the case where the CORESET bandwidth configuration is 'minimum channel bandwidth', and the time slot information where the CORESET is located is 'the control resource set is transmitted in the time slot containing the synchronization signal block'; in the PBCH, 3 bits specifically indicate which of the 8 configurations in Table 1 is adopted by the terminal.

[0223] Table 2 is applicable to the case where the CORESET bandwidth takes a larger value, namely, the 'minimum UE bandwidth', and the time slot information where the CORESET is located is 'the control resource set is transmitted in the time slot containing the synchronization signal block'; in the PBCH, 3 bits specifically indicate which of the 8 configurations in Table 2 is adopted by the terminal.

[0224] Table 3 is applicable to the time slot information where CORESET is located, which is 'the control resource set is transmitted only in the time slot that does not contain the synchronization signal block'; or, the subcarrier spacing of CORESET and the synchronization signal block is different. In this case, CORESET and the synchronization signal block belong to different bandwidth parts (BWP, Bandwidth Part). In PBCH, 3 bits specifically indicate which of the 8 configurations in Table 3 of the terminal is adopted.

[0225] Table 1

[0226]

[0227]

[0228] Table 2

[0229]

[0230] Table 3

[0231]

[0232] Implementation 5:

[0233] This embodiment describes the indication method of the CORESET monitoring window (PDCCH monitoring window) configuration information;

[0234] The CORESET monitoring window configuration information includes at least one of the following information: the monitoring period of the CORESET, the starting monitoring window position, the time domain length of the monitoring window, and the time domain offset between adjacent monitoring windows.

[0235] The CORESET monitoring window is also called the physical downlink control channel PDCCH monitoring window. Each monitoring window corresponds to a synchronization signal block. The CORESET monitoring window contains one or more CORESET monitoring opportunities, that is, one or more resources for transmitting PDCCH. The base station selects a PDCCH transmission resource in a CORESET monitoring window for PDCCH transmission. The terminal can try to receive the PDCCH corresponding to the synchronization signal block on one or more PDCCH transmission resources in the CORESET monitoring window. The synchronization signal block has a quasi-co-location (QCL) relationship with the CORESET or PDCCH in the corresponding monitoring window.

[0236] The monitoring period of the CORESET can also be understood as the transmission period of the CORESET. The value of this period can be predefined, for example, 40ms. It is also possible to predefine multiple monitoring period values ​​in the protocol, such as 20ms, 40ms, and indicate the specific value of the monitoring period of the current carrier through 1 bit in the PBCH.

[0237] The starting monitoring window position of the CORESET refers to the time domain starting position of the first CORESET monitoring window. Taking the CORESET transmission period of 20ms as an example, when the CORESET is transmitted only in the time slot containing the synchronization signal block, the starting monitoring window position of the CORESET is predefined. Fig.19 FIG. 1 is a schematic diagram showing that the CORESET of this embodiment is transmitted only in the time slot containing the synchronization signal block. Fig.19 As shown, the starting monitoring window position of CORESET is the starting point of the radio frame with SFN mod 2=0.

[0238] When the CORESET is transmitted only in a time slot that does not contain a synchronization signal block, the CORESET start monitoring window position is predefined. Fig. 20 FIG. 1 is a schematic diagram of the embodiment in which CORESET is transmitted only in a time slot that does not contain a synchronization signal block. Fig. 20As shown, the starting monitoring window position of CORESET is the 6th subframe (ie, the second half frame) of the radio frame with SFN mod 2=0.

[0239] When the CORESET is transmitted in both a time slot containing a synchronization signal block and a time slot not containing a synchronization signal block, Fig.21 This is a schematic diagram of the embodiment in which the CORESET is transmitted in both the time slot containing the synchronization signal block and the time slot not containing the synchronization signal block (such as Fig.21 As shown, for the CORESET sent in the time slot where the synchronization signal block is located, the starting monitoring window position is the starting point of the wireless frame with SFN mod 2 = 0; for the CORESET sent in the time slot that does not contain the synchronization signal block, the starting monitoring window position is the 6th subframe (i.e., the second half frame) of the wireless frame with SFN mod 2 = 0.

[0240] The time domain length of the monitoring window of the CORESET is 1 or more time slots; preferably, the time domain length of the monitoring window is one or more of the following: 1 time slot, 2 time slots, 4 time slots, or M time slots, where M is the number of time slots occupied by the synchronization signal block in one synchronization signal block transmission cycle.

[0241] When the CORESET is transmitted in the time slot where the synchronization signal block is located, the time domain length of the monitoring window is 1 time slot; when the CORESET is transmitted in the time slot that does not contain the synchronization signal block, the time domain length of the monitoring window can be 1 or more time slots.

[0242] In the CORESET configuration information indication field of PBCH, an indication bit can be introduced to indicate to the terminal the time domain length of the CORESET monitoring window of the current carrier. For example, using 2 bits to indicate, '00' represents 'the time domain length of the monitoring window is 1 time slot', '01' represents 'the time domain length of the monitoring window is 2 time slots', '10' represents 'the time domain length of the monitoring window is M time slots', and '11' status reserved'.

[0243] Alternatively, the protocol specifies that only any two of the four time domain lengths of the CORESET monitoring window are included, and 1 bit is further used in the PBCH to indicate which specific configuration is adopted by the current carrier. For example, '0' represents 'the time domain length of the monitoring window is 1 time slot', and '1' represents 'the time domain length of the monitoring window is 2 time slots'.

[0244] Alternatively, the protocol specifies that the time domain length of the CORESET monitoring window can be configured in the following three ways: 1 time slot, 2 time slots, and 4 time slots; and the time domain transmission resource of the CORESET monitoring window is jointly indicated with the time domain length of the monitoring window, occupying a total of 2 bits, for example,

[0245] '00': CORESET transmits in the time slot containing the SS / PBCH block, and the CORESET monitoring window length = 1 slot;

[0246] '01': CORESET transmits in a slot that does not contain an SS / PBCH block, and the CORESET monitoring window length = 1 slot;

[0247] '10': CORESET transmits in the time slot that does not contain the SS / PBCH block, and the CORESET monitoring window length = 2 slots;

[0248] '11': CORESET transmits in the time slot that does not contain the SS / PBCH block, and the CORESET monitoring window length = 4 slots;

[0249] The time domain offset between adjacent monitoring windows includes one or more of the following: 0, the time domain length of the monitoring window, 1 / X of the time domain length of the monitoring window, where X is an integer greater than 1, and its specific value may be predefined in the protocol or indicated by signaling.

[0250] Fig. 22 This is a schematic diagram of the CORESET in this embodiment transmitting only in the time slot where the synchronization signal block is located, such as Fig. 22 As shown, when the CORESET is transmitted only in the time slot where the synchronization signal block is located, and the CORESET is transmitted in frequency division multiplexing with the corresponding SSB, the time domain length of the monitoring window is 1 time slot, and the time domain offset between adjacent monitoring windows is equal to the time domain length of the monitoring window, that is, 1 time slot. At this time, there is no overlap between adjacent monitoring windows. Fig. 22 In the , 8 synchronization signal blocks can be used as resources for sending synchronization signals and physical broadcast channels, and the base station can select some or all of them as the synchronization signal blocks (actual SSB) actually sent.

[0251] Fig.23 In this embodiment, CORESET transmits only in the time slot not including the synchronization signal block. Figure 1 , Fig.23 In the embodiment, the CORESET is transmitted only in the time slot that does not contain the synchronization signal block, that is, the second half of the wireless frame where the synchronization signal block is located, the time domain length of the monitoring window is 1 time slot, and the time domain offset between adjacent monitoring windows is equal to the time domain length of the monitoring window, that is, 1 time slot. At this time, there is no overlap between adjacent monitoring windows. Fig.23 The dashed box in the middle shows a pseudo synchronization signal block (pseudo SSB). The transmission of CORESET will also avoid these pseudo synchronization signal blocks. The resources occupied by CORESET in the time slot are the same as Fig. 22The advantage of this configuration is that when the transmission period of the synchronization signal block is 5ms, the time slot where the CORESET is located will also transmit the synchronization signal block of the next period. Since the transmission of the CORESET avoids the resources for transmitting the synchronization signal block, even if the transmission period of the synchronization signal block is 5ms, there will be no conflict between the two. The terminal does not need to know the actual transmission period of the synchronization signal block of the current carrier.

[0252] Fig.24 In this embodiment, CORESET transmits only in the time slot not including the synchronization signal block. Figure 2 ,like Fig.24 As shown, the CORESET is only transmitted in the time slot that does not contain the synchronization signal block, that is, the second half of the wireless frame where the synchronization signal block is located. The time domain length of the monitoring window is 2 time slots, and the time domain offset between adjacent monitoring windows is equal to 1 / 2 of the time domain length of the monitoring window, that is, 1 time slot. Then the adjacent monitoring windows are partially overlapped. Specifically, the second synchronization signal block in the time slot slot1 where the synchronization signal block is located is actually transmitted. This synchronization signal block corresponds to monitoring window 1, that is, the second and third time slots in the second half of the frame. These two time slots contain 4 CORESET transmission resources, and the base station selects one of them to send the CORESET corresponding to this synchronization signal block. Similarly, the first synchronization signal block in slot2 is actually sent, which corresponds to monitoring window 2, that is, the third and fourth time slots. The base station selects one of the CORESET transmission resources in these two time slots to send the CORESET corresponding to this synchronization signal block.

[0253] It should be noted that the CORESETs corresponding to different synchronization signal blocks cannot occupy the same CORESET transmission resources. Therefore, when selecting CORESET transmission resources for the subsequent synchronization signal blocks in the corresponding monitoring window, it is necessary to avoid the CORESET transmission resources that have been occupied.

[0254] Fig.25 Schematic diagram of the CORESET monitoring window corresponding to all synchronization signal blocks in this embodiment, such as Fig.25 As shown, all synchronization signal blocks correspond to the same CORESET monitoring window. Specifically, 4 time slots containing synchronization signal blocks contain 8 synchronization signal block resources. At this time, only two of the synchronization signal blocks are sent. The 8 synchronization signal blocks all correspond to the same CORESET monitoring window. The monitoring window contains 8 CORESET transmission resources. For the terminal, no matter which synchronization signal block is received, it is necessary to try to receive the corresponding CORESET at the 8 CORESET monitoring opportunities in this monitoring window.

[0255] Fig.26is a schematic diagram of a plurality of synchronization signal blocks corresponding to a CORESET monitoring window in this embodiment, such as Fig.26 As shown, multiple synchronization signal blocks correspond to a CORESET monitoring window. Specifically, 8 synchronization signal block resources are included in 4 time slots containing synchronization signal blocks. At this time, the first 4 synchronization signal blocks are actually sent, and the 4 synchronization signal blocks in the first two time slots all correspond to the first CORESET monitoring window (corresponding to the first two false synchronization signal block time slots in the time domain), and the 4 synchronization signal blocks in the last two time slots all correspond to the second CORESET monitoring window (corresponding to the third and fourth false synchronization signal block time slots in the time domain). For the terminal, when one of the first four SSBs is received, it is necessary to try to receive the corresponding CORESET at the 8 CORESET monitoring opportunities in monitoring window 1. When one of the last four SSBs is received, it is necessary to try to receive the corresponding CORESET at the 8 CORESET monitoring opportunities in monitoring window 2.

[0256] In the CORESET configuration information indication field of PBCH, an indication bit can be introduced to indicate to the terminal the time domain offset of the CORESET adjacent monitoring window of the current carrier. For example, using 2 bits to indicate, '00' represents 'the time domain offset of the adjacent monitoring window is 0', '01' represents 'the time domain offset of the adjacent monitoring window is the monitoring window length', '10' represents 'the time domain offset of the adjacent monitoring window is 1 / X of the monitoring window length', and '11' is reserved. Among them, X is an integer greater than 1, and its specific value can be specified in the protocol, or indicated by signaling.

[0257] In the above indication method, a 2-bit indication overhead needs to be introduced in order to reduce this overhead. The types of time domain offsets of adjacent monitoring windows can also be limited according to different time domain lengths of monitoring windows. For example, when the monitoring window length is 1 time slot, it is stipulated that there are only two possibilities for the time domain offset between adjacent monitoring windows: the time domain offset of adjacent monitoring windows is the monitoring window length (that is, adjacent monitoring windows do not overlap and are configured continuously), or the time domain offset of adjacent monitoring windows is 1 / X of the time domain length of the monitoring window (that is, adjacent monitoring windows partially overlap). At this time, only 1 bit is needed to indicate this offset value, for example, '0' represents 'the time domain offset of adjacent monitoring windows is the monitoring window length', and '1' represents 'the time domain offset of adjacent monitoring windows is 1 / X of the monitoring window length'. Similarly, X is an integer greater than 1, and its specific value can be specified in the protocol, or indicated by signaling.

[0258] For the case where the monitoring window length is greater than 1 time slot, it is stipulated that there are only two possibilities for the time domain offset between adjacent monitoring windows: the time domain offset of adjacent monitoring windows is 0 (i.e., adjacent monitoring windows completely overlap), and the time domain offset of adjacent monitoring windows is 1 / X of the monitoring window length (i.e., adjacent monitoring windows partially overlap). In this case, only 1 bit is needed to indicate the offset value, for example, '0' represents 'the time domain offset of adjacent monitoring windows is 0', and '1' represents 'the time domain offset of adjacent monitoring windows is 1 / X of the monitoring window length'. Similarly, X is an integer greater than 1, and its specific value can be specified in the protocol, or indicated by signaling.

[0259] In this application, the technical features in various embodiments can be combined and used in one embodiment without conflict. Each embodiment is only the best embodiment of this application.

[0260] This embodiment provides a method for transmitting the configuration information of the common control information block. Through this solution, the time-frequency domain resource position of the control resource set can be effectively indicated without affecting the PBCH combined reception (i.e., ensuring that the PBCH content in each SS block is the same). In addition, by configuring the time domain length of the control resource set monitoring window and the time domain offset of the monitoring window corresponding to the adjacent SS block, the transmission resources of the common control block are made more flexible, which effectively avoids the impact of burst service transmission on the common control block transmission.

[0261] Example 4

[0262] An embodiment of the present invention further provides a storage medium, which includes a stored program, wherein when the program is run, any of the above methods is executed.

[0263] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0264] S1, carrying configuration information of a control resource set on a physical broadcast channel; wherein the configuration information is used to indicate to a terminal at least one of the following of the control resource set: time domain location information, frequency domain location information;

[0265] S2: Send the control resource set to the terminal according to the configuration information.

[0266] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0267] An embodiment of the present invention further provides a processor, which is used to run a program, wherein the program executes the steps in any of the above methods when running.

[0268] Optionally, in this embodiment, the above program is used to perform the following steps:

[0269] S1, carrying configuration information of a control resource set on a physical broadcast channel; wherein the configuration information is used to indicate to a terminal at least one of the following of the control resource set: time domain location information, frequency domain location information;

[0270] S2: Send the control resource set to the terminal according to the configuration information.

[0271] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0272] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0273] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A wireless communication method, comprising: Transmitting configuration information of a common control resource set to a terminal on a physical broadcast channel, The common control resource set corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and According to the configuration information, the common control resource set is transmitted to the terminal in the first time slot and the second time slot, the first time slot contains a synchronization signal block SSB, the second time slot does not contain the SSB, and the common control resource set adopts the same resource mapping rule in the first time slot and the second time slot.

2. The method according to claim 1, wherein: The starting symbol index of at least one symbol occupied by the common control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

3. A wireless communication method, comprising: Transmitting configuration information of a common control resource set to a terminal on a physical broadcast channel, The common control resource set corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and transmitting the common control resource set to the terminal according to the configuration information, The first time slot where the common control resource set is located includes a synchronization signal block SSB, Among them, the starting symbol index of at least one symbol occupied by the public control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

4. A wireless communication method, comprising: The terminal receives the configuration information of the common control resource set on the physical broadcast channel. The common control resource set corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and The terminal receives the common control resource set in the first time slot and the second time slot according to the configuration information, the first time slot contains a synchronization signal block SSB, the second time slot does not contain the SSB, and the common control resource set adopts the same resource mapping rule in the first time slot and the second time slot.

5. The method according to claim 4, wherein: The starting symbol index of at least one symbol occupied by the common control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

6. A wireless communication method, comprising: The terminal receives the configuration information of the common control resource set on the physical broadcast channel. The common control resource set corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and The terminal receives the common control resource set according to the configuration information, The first time slot where the common control resource set is located includes a synchronization signal block SSB, Among them, the starting symbol index of at least one symbol occupied by the public control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

7. A base station, comprising a processor, wherein the processor is configured to: Transmitting configuration information of a common control resource set to a terminal on a physical broadcast channel, in, The set of common control resources corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and According to the configuration information, the common control resource set is transmitted to the terminal in the first time slot and the second time slot, the first time slot contains a synchronization signal block SSB, the second time slot does not contain the SSB, and the common control resource set adopts the same resource mapping rule in the first time slot and the second time slot.

8. The base station according to claim 7, wherein: The starting symbol index of at least one symbol occupied by the common control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

9. A base station, comprising a processor, wherein the processor is configured to: Transmitting configuration information of a common control resource set to a terminal on a physical broadcast channel, in, The set of common control resources corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and transmitting the common control resource set to the terminal according to the configuration information, The first time slot where the common control resource set is located includes a synchronization signal block SSB, Among them, the starting symbol index of at least one symbol occupied by the public control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

10. A terminal, comprising a processor, wherein the processor is configured to: receiving configuration information of a set of common control resources on a physical broadcast channel, in, The set of common control resources corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and The common control resource set is received in the first time slot and the second time slot according to the configuration information, the first time slot contains a synchronization signal block SSB, the second time slot does not contain the SSB, and the common control resource set adopts the same resource mapping rule in the first time slot and the second time slot. The terminal according to claim 10 , wherein: The starting symbol index of at least one symbol occupied by the common control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

12. A terminal, comprising a processor, wherein the processor is configured to: receiving configuration information of a set of common control resources on a physical broadcast channel, in, The set of common control resources corresponds to the remaining minimized system information RMSI, The configuration information indicates the time domain location information of the common control resource set, The time domain location information of the common control resource set includes: (1) information of a first time slot where the common control resource set is located, (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first time slot, and (3) the number of at least one symbol occupied by the common control resource set in the first time slot. The at least one symbol occupied by the common control resource set in the first time slot includes at least one of the third symbol, the fifth symbol, the seventh symbol or the ninth symbol of the first time slot; and receiving the common control resource set according to the configuration information, The first time slot where the common control resource set is located includes a synchronization signal block SSB, Among them, the starting symbol index of at least one symbol occupied by the public control resource set in the first time slot is the same as the starting symbol index of the symbol occupied by the SSB in the first time slot.

13. A storage medium, characterized in that: The storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 6 when executed.

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