Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, wherein the array substrate comprises a base substrate, a first metal layer, a first insulating layer, a second metal layer, and a flat layer; the first metal layer, the first insulating layer, the second metal layer, and the flat layer are sequentially stacked on the base substrate, a first via hole and a second via hole are formed on the flat layer, and the depth of the first via hole is greater than the depth of the second via hole; the array substrate further comprises a first electrode, a second electrode, and a second insulating layer, the first electrode is laid on the flat layer and covers the first via hole and the second via hole; the second insulating layer is laid on the first electrode; the second electrode corresponds to the setting of the first electrode and is set on the second insulating layer, and the second electrode is at least laid in the first via hole and covers the first via hole. The present application improves the problem of panel defects caused by the etching solution remaining in the via hole by the above method.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] In the current manufacturing process of display panels, since some of the vias formed on the flat layer are deeper and some are shallower, the photoresist of the pixel electrode will accumulate in the deep hole during the preparation of the pixel electrode, resulting in the photoresist not being easily exposed during exposure. Some shallow holes of the pixel electrode material may be exposed, while some deep holes are not exposed, resulting in poor uniformity of the panel, which may lead to some ongoing risks and cause troubles to detection. At the same time, the residual pixel electrode is generally accompanied by residual etching solution, which can easily cause ongoing adverse risks to the display panel and cause problems such as image abnormality and screen burn-in.

[0003] Therefore, how to improve the panel defects caused by the etching solution remaining in the via hole has become an urgent problem to be solved in the art. Summary of the invention

[0004] The present application discloses an array substrate and a display panel, the purpose of which is to improve the problem of etching liquid remaining in via holes causing panel defects.

[0005] The present application discloses an array substrate, comprising a base substrate, a first metal layer, a first insulating layer, a second metal layer, and a flat layer; the first metal layer, the first insulating layer, the second metal layer, and the flat layer are stacked in sequence on the base substrate, a first via hole and a second via hole are formed on the flat layer, and the depth of the first via hole is greater than the depth of the second via hole; the array substrate also comprises a first electrode, a second electrode, and a second insulating layer, the first electrode is laid on the flat layer and covers the first via hole and the second via hole; the second insulating layer is laid on the first electrode; the second electrode corresponds to the setting of the first electrode and is set on the second insulating layer, the second electrode is at least laid in the first via hole and covers the first via hole.

[0006] Optionally, the second electrode is laid only at a position corresponding to the first via hole.

[0007] Optionally, an opening is formed in the second insulating layer at a position corresponding to the second via hole, and an area of ​​the opening is equal to an opening area of ​​the second via hole.

[0008] Optionally, the second electrode is laid in both the first via hole and the second via hole, and the second electrode covers both the first via hole and the second via hole.

[0009] Optionally, an orthographic projection area of ​​the second electrode on the base substrate is smaller than or equal to an orthographic projection area of ​​the first electrode on the base substrate.

[0010] Optionally, a thickness of the second electrode in the first via hole is greater than a thickness of the first electrode in the first via hole.

[0011] Optionally, a thickness of the second electrode at the bottom of the first via hole is greater than a thickness of the second electrode at the wall of the first via hole.

[0012] Optionally, a thickness of the second insulating layer in the first via hole is greater than a thickness of the second insulating layer outside the first via hole.

[0013] Optionally, the array substrate further includes a third electrode, the third electrode and the second electrode are both pixel electrodes, and the third electrode is located in the display area of ​​the array substrate; the third electrode is arranged in the same layer as the second electrode and is disconnected from the second electrode.

[0014] The present application also discloses a display panel, including a color film substrate. The display panel also includes the above-mentioned array substrate. The color film substrate and the array substrate are stacked.

[0015] The present application improves the film layer structure of the array substrate. Since a plurality of via holes of different depths are formed on the flat layer of the array substrate, when the second electrode on the flat layer is exposed, the second electrode material is most likely to accumulate in the deeper via hole, affecting the uniformity of the panel. Therefore, the present application at least covers the first via hole in the deeper first via hole and lays the second electrode, and the position of the second electrode corresponds to the position of the first electrode, so as to ensure that the second electrode is not connected with the electrodes at other positions above the flat layer, and does not affect the normal display of the display panel; that is, when making the second electrode, at least the second electrode in the first via hole is retained, and the second electrode in the first via hole is not exposed, so that the second electrode forms a second electrode layer in the first via hole, so that no etching solution attached to the second electrode material will remain in the first via hole; thereby ensuring the uniformity of the panel, preventing the second electrode material from accumulating in the via hole and causing uneven exposure, thereby causing inspection problems; and at the same time improving the problem of panel defects caused by etching solution remaining in the via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0017] Figure 1 This is a schematic diagram of a first embodiment of an array substrate of the present application:

[0018] Figure 2 A schematic diagram of a second embodiment of an array substrate of the present application;

[0019] Figure 3 is a schematic diagram of a third embodiment of an array substrate of the present application;

[0020] Figure 4 is a schematic diagram of a fourth embodiment of an array substrate of the present application;

[0021] Figure 5 is a schematic diagram of a fifth embodiment of an array substrate of the present application;

[0022] Figure 6 is a schematic diagram of a sixth embodiment of an array substrate of the present application;

[0023] Figure 7 is a schematic diagram of a seventh embodiment of the array substrate of the present application;

[0024] Figure 8 FIG. 1 is a schematic diagram of an embodiment of a display panel of the present application.

[0025] Among them, 10, display panel; 100, array substrate; 200, color film substrate; 110, base substrate; 111, first metal layer; 112, first insulating layer; 113, second metal layer; 120, flat layer; 121, first via hole; 122, second via hole; 130, first electrode; 140, second electrode; 150, second insulating layer; 151, opening; 160, third electrode; 170, display area. DETAILED DESCRIPTION

[0026] The present application is described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0027] Figure 1 is a schematic diagram of a first embodiment of an array substrate of the present application, as shown Figure 1As shown, the present application discloses an array substrate 100, including a base substrate 110, a first metal layer 111, a first insulating layer 112, a second metal layer 113, and a flat layer 120; the first metal layer 111, the first insulating layer 112, the second metal layer 113, and the flat layer 120 are stacked on the base substrate 110 in sequence, and a first via hole 121 and a second via hole 122 are formed on the flat layer 120, and the depth of the first via hole 121 is greater than the depth of the second via hole 122; the array substrate 100 also includes a first electrode 130, a second electrode 140, and a second insulating layer 150, the first electrode 130 is laid on the flat layer 120 and covers the first via hole 121 and the second via hole 122; the second insulating layer 150 is laid on the first electrode 130; the second electrode 140 corresponds to the setting of the first electrode 130, and is set on the second insulating layer 150, and the second electrode 140 is at least laid in the first via hole 121 and covers the first via hole 121.

[0028] The present application improves the film structure of the array substrate 100. Since a plurality of via holes of different depths are formed on the flat layer 120 of the array substrate 100, when the second electrode 140 on the flat layer 120 is exposed, the second electrode 140 material is most likely to be deposited in the deeper via hole, affecting the uniformity of the panel. Therefore, the present application at least lays the second electrode 140 in the deeper first via hole 121, covering the first via hole 121, and the position of the second electrode 140 corresponds to the position of the first electrode 130. In this way, it can be ensured that the second electrode 140 does not overlap with the electrode shape at other positions above the flat layer 120. The second electrode 140 is at least retained in the first via hole 121, and the second electrode 140 in the first via hole 121 is not exposed, so that the second electrode 140 forms a second electrode 140 layer in the first via hole 121. Therefore, no etching liquid attached to the second electrode 140 material will remain in the first via hole 121. This ensures the uniformity of the panel and prevents uneven exposure caused by the accumulation of the second electrode 140 material in the via hole, thereby causing inspection problems. At the same time, it improves the problem of panel defects caused by the etching liquid remaining in the via hole.

[0029] It should be noted that the first metal layer 111 in the present application can be a gate for transmitting gate signals and common electrode VCOM signals, and the first insulating layer 112 can be a gate insulating layer: the second metal layer 113 can be a source and drain for transmitting data line signals or pixel voltages; the first electrode 130 is used to transmit VCOM signals, and the second insulating layer 150 is used to isolate the first electrode 130 and the second electrode 140, and allow the first electrode 130 and the second electrode 140 to form a storage capacitor, and the second electrode 140 can be made of pixel electrode material to transmit pixel voltage; of course, the above is limited to pixels of TOP Pixel structure, TOP COM pixel architecture, and the functions of the first electrode 130 and the second electrode 140 can be interchanged.

[0030] like Figure 1 As shown, the second electrode 140 is only laid at the position corresponding to the first via hole 121. The second electrode 140 is not set at the position of the second via hole 122, that is, the second electrode 140 is only set in the deep hole, and the second electrode 140 is not set in the shallow hole; when the second electrode 140 on the flat layer 120 is exposed, the second electrode 140 material is most likely to accumulate in the deeper via hole, affecting the uniformity of the panel. Therefore, in this embodiment, the second electrode 140 is only laid in the deeper first via hole 121, covering the first via hole 121, which can not only improve the problem of etching solution residue in the deep hole, but also reduce the cost.

[0031] Figure 2 is a schematic diagram of a second embodiment of the array substrate of the present application, as shown Figure 2 As shown, Figure 2 The illustrated embodiment is based on Figure 1 In the improvement, the second insulating layer 150 is formed with an opening 151 at a position corresponding to the second via hole 122 , and the area of ​​the opening 151 is equal to the opening area of ​​the second via hole 122 .

[0032] This embodiment and Figure 1 The difference from the illustrated embodiment is that in this embodiment, an opening 151 is provided at a position of the second insulating layer 150 corresponding to the second via hole 122 , so that the second insulating layer 150 forms a relief at the position of the second via hole 122 .

[0033] Since the second electrode 140 is only provided at the deeper first via hole 121, and the second electrode 140 is not provided at the shallower second via hole 122, it is only necessary to ensure that there is a second insulating layer 150 at the position of the first via hole 121, and the first electrode 130 and the second electrode 140 are separated by the second insulating layer 150 to avoid the first electrode 130 and the second electrode 140 being conductive to form a short circuit, which affects the normal display of the display panel 10. The second insulating layer 150 does not need to be provided at the second via hole 122, which can not only improve the problem of etching solution residue in the deep hole, but also reduce the use area of ​​the second insulating layer 150, reduce the cost, and reduce the weight of the substrate.

[0034] Figure 3 is a schematic diagram of a third embodiment of the array substrate of the present application, as shown Figure 3 As shown, Figure 3 The illustrated embodiment is based on Figure 1 In the improvement, the second electrode 140 is laid in both the first via hole 121 and the second via hole 122 , and the second electrode 140 covers the first via hole 121 and the second via hole 122 at the same time.

[0035] This embodiment and Figure 1 The difference from the illustrated embodiment is that in this embodiment, the second electrode 140 is laid in both the first via hole 121 and the second via hole 122, that is, the second electrode 140 is used to cover the deeper and shallower via holes at the same time. When the second electrode 140 is manufactured, the second electrode 140 in the first via hole 121 and the second via hole 122 is retained, and the second electrode 140 in the first via hole 121 and the second via hole 122 is not exposed, so that the second electrode 140 forms a second electrode 140 layer in the first via hole 121 and the second via hole 122. Therefore, no etching liquid attached to the second electrode 140 material will remain in the first via hole 121 and the second via hole 122; thereby further ensuring the uniformity of the display panel 10, preventing the second electrode 140 material from accumulating in the via hole and causing uneven exposure, thereby causing inspection problems; at the same time, improving the problem of panel defects caused by etching liquid remaining in the via hole.

[0036] In addition, in this embodiment, the orthographic projection area of ​​the second electrode 140 on the base substrate 110 is less than or equal to the orthographic projection area of ​​the first electrode 130 on the base substrate 110. Figure 3 As shown, the width of the second electrode 140 is equal to or smaller than the width of the first electrode 130 .

[0037] When the orthographic projection area of ​​the second electrode 140 on the base substrate 110 is equal to the orthographic projection area of ​​the first electrode 130 on the base substrate 110, that is, the width of the second electrode 140 is equal to the width of the first electrode 130, the storage capacitance formed between the first electrode 130 and the second electrode 140 can be maximized, thereby ensuring the display stability of the display panel 10; when the orthographic projection area of ​​the second electrode 140 on the base substrate 110 is smaller than the orthographic projection area of ​​the first electrode 130 on the base substrate 110, that is, the width of the second electrode 140 is smaller than the width of the first electrode 130, the laying area of ​​the second electrode 140 can be effectively controlled, and the laying cost of the second electrode 140 can be controlled; and it can also ensure that the second electrode 140 completely covers the first via hole 121 and the second via hole 122, while preventing the second electrode 140 from contacting other structures on the flat layer 120 and the same layer as the second electrode 140, resulting in a short circuit, thereby further ensuring the stability and quality of the array substrate 100.

[0038] Figure 4 is a schematic diagram of a fourth embodiment of the array substrate of the present application, as shown Figure 4 As shown, Figure 4 The illustrated embodiment is based on Figure 1 In the improvement, the thickness of the second electrode 140 in the first via hole 121 is greater than the thickness of the first electrode 130 in the first via hole 121 .

[0039] Since the first via hole 121 is deeper and the inclination angle of the hole wall of the first via hole 121 is larger than that of the hole wall of the second via hole 122, the second electrode 140 is easily broken when laid in the first via hole 121; therefore, in this embodiment, the structure of the second electrode 140 is improved, and the thickness of the second electrode 140 in the first via hole 121 is greater than the thickness of the first electrode 130 in the first via hole 121, that is, by increasing the thickness of the second electrode 140 in the first via hole 121, the structural strength of the second electrode 140 is increased, so that the second electrode 140 is not easy to break in the first via hole 121, and a stable storage capacitor can be formed between the second electrode 130, thereby enhancing the display quality of the display panel 10.

[0040] Figure 5 is a schematic diagram of a fifth embodiment of the array substrate of the present application, as shown Figure 5 As shown, the thickness of the second electrode 140 at the bottom of the first via hole 121 is greater than the thickness of the second electrode 140 at the wall of the first via hole 121 .

[0041] The present embodiment is different from the previous embodiment in that, in order to prevent the second electrode 140 from breaking in the first via hole 121, the thickness of the second electrode 140 at the bottom of the first via hole 121 is greater than the thickness of the second electrode 140 at the wall of the first via hole 121, that is, by increasing the thickness of the second electrode 140 at the bottom of the first via hole 121, the structural strength of the second electrode 140 is increased, so that the connection between the hole wall and the bottom of the first via hole 121 is more stably made, and the second electrode 140 is not easy to break in the first via hole 121, thereby ensuring that a stable storage capacitor is formed between the second electrode 140 and the first electrode 130, thereby enhancing the display quality of the display panel 10.

[0042] In addition, in order to realize the thinness and lightness of the array substrate 100, the present application also designs the structure of the second insulating layer 150, as follows:

[0043] Figure 6 is a schematic diagram of a sixth embodiment of the array substrate of the present application, as shown Figure 6 As shown, the thickness of the second insulating layer 150 inside the first via hole 121 is greater than the thickness of the second insulating layer 150 outside the first via hole 121 .

[0044] and Figure 1 What is different from the illustrated embodiment is that, in this embodiment, the thickness of the second insulating layer 150 laid outside the first via hole 121 is made smaller than the thickness of the second insulating layer 150 inside the first via hole 121, so that the thickness of the second insulating layer 150 outside the first via hole 121 and laid on the flat layer 120 is thinned. By thinning the thickness of the second insulating layer 150, the thickness of the entire array substrate 100 can be effectively reduced, thereby achieving a lightweight and thin array substrate 100.

[0045] Figure 7 is a schematic diagram of a seventh embodiment of the array substrate of the present application, as shown Figure 7 As shown, the array substrate 100 also includes a third electrode 160 . The third electrode 160 and the second electrode 140 are both pixel electrodes. The third electrode 160 is located in the display area 170 of the array substrate 100 . The third electrode 160 is arranged in the same layer as the second electrode 140 and is disconnected from the second electrode 140 .

[0046] In the present embodiment, the material of the second electrode 140 is the same as the material of the third electrode 160 in the display area 170 of the array substrate 100, and both are pixel electrode materials. Thus, when forming the pixel electrode of the display area 170 and the second electrode 140 of the non-display area 170, both can be made of the pixel electrode material, thereby simplifying the manufacturing process. During the manufacturing process, the pixel electrode material is laid on the flat layer 120 of the array substrate 100 in an entire layer. After the pixel electrode is formed in the display area 170 of the array substrate 100, the pixel electrode of the display area 170 of the array substrate 100 is disconnected from the pixel electrode above the first via hole 121 and the second via hole 122, so as to avoid the pixel electrode of the display area 170 being connected to the pixel electrode of the non-display area 170 to form a short circuit after power is turned on, thereby ensuring the display quality of the display panel 10.

[0047] Furthermore, by laying the pixel electrode in the first via hole 121 and the second via hole 122, that is, by using the pixel electrode to cover the deeper and shallower via holes at the same time, when manufacturing the pixel electrode in the non-display area 170, the pixel electrode material in the first via hole 121 and the second via hole 122 is retained, and the pixel electrode material in the first via hole 121 and the second via hole 122 is not exposed, so that the second electrode 140 forms a pixel electrode layer in the first via hole 121 and the second via hole 122 together, so that no etching liquid attached to the pixel electrode material will remain in the first via hole 121 and the second via hole 122; thereby further ensuring the uniformity of the display panel 10, preventing the pixel electrode material from accumulating in the first via hole 121 and the second via hole 122 and causing uneven exposure, thereby causing inspection problems; at the same time, improving the problem of panel defects caused by etching liquid remaining in the via holes.

[0048] Figure 8 1 is a schematic diagram of an embodiment of a display panel of the present application. The present application also discloses a display panel 10, including a color filter substrate 200. The display panel 10 also includes the above-mentioned array substrate 100. The color filter substrate 200 and the array substrate 100 are stacked. When manufacturing the display panel 10, the color filter substrate 200 is installed above the array substrate 100, and liquid crystal is encapsulated between the color filter substrate 200 and the array substrate 100 to form a complete display panel 10.

[0049] Since a plurality of via holes of varying depths are formed on the flat layer 120 in the array substrate 100 of the display panel 10, when the second electrode 140 on the flat layer 120 is exposed, the material of the second electrode 140 is most likely to accumulate in the deeper via holes, thus affecting the uniformity of the display panel 10 and further affecting the display quality of the display panel 10.

[0050] In view of the above problems, the present application improves the film structure of the array substrate 100, at least in the deeper first via hole 121, the second electrode 140 is laid to cover the first via hole 121, and the position of the second electrode 140 corresponds to the position of the first electrode 130, so that it can be ensured that the second electrode 140 is not connected with the electrodes at other positions above the flat layer 120, and does not affect the normal display of the display panel 10; that is, when the second electrode 140 is manufactured, at least the second electrode 140 in the first via hole 121 is retained, and the second electrode 140 in the first via hole 121 is not exposed, so that the second electrode 140 forms a second electrode 140 layer in the first via hole 121, so that no etching liquid attached to the second electrode 140 material will remain in the first via hole 121; thereby, the uniformity of the panel is ensured, and the uneven exposure caused by the accumulation of the second electrode 140 material in the via hole is prevented, thereby preventing the inspection trouble caused by the uneven exposure; at the same time, the problem of the etching liquid remaining in the via hole causing the panel to be defective is improved, thereby effectively improving the display quality of the display panel 10.

[0051] It should be noted that the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0052] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. An array substrate, comprising a base substrate, a first metal layer, a first insulating layer, a second metal layer, and a flat layer; the first metal layer, the first insulating layer, the second metal layer, and the flat layer are sequentially stacked on the base substrate, a first via hole and a second via hole are formed on the flat layer, and a depth of the first via hole is greater than a depth of the second via hole; It is characterized in that The array substrate further includes a first electrode, a second electrode and a second insulating layer, wherein the first electrode is laid on the flat layer and covers the first via hole and the second via hole; and the second insulating layer is laid on the first electrode; The second electrode corresponds to the arrangement of the first electrode and is arranged on the second insulating layer. The second electrode is at least laid in the first via hole and covers the first via hole; The second electrode is laid in both the first via hole and the second via hole, and the second electrode covers both the first via hole and the second via hole; The array substrate further includes a third electrode, the third electrode and the second electrode are both pixel electrodes, and the third electrode is located in the display area of ​​the array substrate; the third electrode is arranged in the same layer as the second electrode and is disconnected from the second electrode; The material of the second electrode is the same as that of the third electrode, both of which are pixel electrode materials, forming a pixel electrode in a display area and a second electrode in a non-display area; The pixel electrode is laid in the first via hole and the second via hole. When manufacturing the pixel electrode in the non-display area, the pixel electrode material in the first via hole and the second via hole is not exposed, so that the second electrode forms a pixel electrode layer in the first via hole and the second via hole.

2. The array substrate according to claim 1, characterized in that: An opening is formed in the second insulating layer at a position corresponding to the second via hole, and an area of ​​the opening is equal to an opening area of ​​the second via hole.

3. The array substrate according to claim 1, characterized in that: The orthographic projection area of ​​the second electrode on the base substrate is smaller than or equal to the orthographic projection area of ​​the first electrode on the base substrate.

4. The array substrate according to claim 1, wherein: The thickness of the second electrode in the first via hole is greater than the thickness of the first electrode in the first via hole.

5. The array substrate according to claim 4, characterized in that: The thickness of the second electrode at the bottom of the first via hole is greater than the thickness of the second electrode at the wall of the first via hole.

6. The array substrate according to claim 1, characterized in that: The thickness of the second insulating layer in the first via hole is greater than the thickness of the second insulating layer outside the first via hole.

7. A display panel, comprising a color film substrate, characterized in that: The display panel further comprises an array substrate as claimed in any one of claims 1 to 6, and the color filter substrate and the array substrate are stacked.

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