Semiconductor devices

Abstract

The semiconductor device (1) is a vertical field effect transistor (10) having a first gate trench (17) extending in a first direction, a second gate trench (27) formed deeper than the first gate trench (17), a first gate insulating film (16) and a first gate conductor (15) formed inside the first gate trench (17), and a second gate insulating film (26) and a second gate conductor (25) formed inside the second gate trench (27), wherein the first gate conductor (15) and the second gate conductor (25) are at the same potential, and when the number of the first gate trenches (17) is n, the number of the second gate trenches (27) is greater than 2 and less than n+1, and the second gate trench (27) is provided at the end of the region where the first gate trench (17) and the second gate trench (27) are provided in a second direction parallel to the upper surface of the low-concentration impurity layer (33) and orthogonal to the first direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip size package type semiconductor device. Background Art

[0002] In a vertical field effect transistor having a gate trench, it is known that there is a trade-off relationship between breakdown voltage and on-resistance.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-219774

[0006] Patent Document 2: Japanese Patent No. 6509674 Summary of the invention

[0007] Problems to be solved by the invention

[0008] In a vertical field effect transistor having a gate trench, it is required to reduce on-resistance while maintaining a withstand voltage, and to reduce the electric field intensity generated near the bottom of the gate trench when a voltage is applied between the drain and the source, thereby improving resistance to reliability degradation.

[0009] Patent Documents 1 and 2 disclose structures of vertical field effect transistors, and disclose structures for optimizing characteristics that are in a trade-off relationship.

[0010] Means for solving problems

[0011] In order to solve the above-mentioned problems, the semiconductor device disclosed in the present invention is a semiconductor device of chip size package type that can be mounted face-down, and is a vertical field effect transistor, comprising: a semiconductor substrate of the first conductivity type, containing impurities of the first conductivity type; a low-concentration impurity layer of the first conductivity type, formed in contact with the semiconductor substrate, containing impurities of the first conductivity type at a concentration lower than the concentration of impurities of the first conductivity type of the semiconductor substrate; a body region of the second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer; a source region of the first conductivity type, formed in the body region; a source electrode, electrically connected to the body region and the source region; a first gate trench, which penetrates the body region from the upper surface of the low-concentration impurity layer and is formed to a depth that reaches a portion of the low-concentration impurity layer, has a portion in contact with the source region, and is parallel to the upper surface of the low-concentration impurity layer. extending in the first direction; a second gate trench, which penetrates the body region from the upper surface of the low-concentration impurity layer and is formed deeper than the first gate trench, has a portion in contact with the source region, and extends in the first direction; a first gate insulating film, formed inside the first gate trench; a first gate conductor, formed on the first gate insulating film; a second gate insulating film, formed inside the second gate trench; and a second gate conductor, formed on the second gate insulating film; the first gate conductor and the second gate conductor are of the same potential; when the number of the first gate trenches is n, the number of the second gate trenches is greater than 2 and less than n+1, and n is an integer greater than 1; in a second direction parallel to the upper surface of the low-concentration impurity layer and orthogonal to the first direction, the second gate trench is set at the end of the region where the first gate trench and the second gate trench are set.

[0012] According to this structure, the on-resistance can be reduced, and the resistance to the electric field intensity which is a factor causing the reliability to be reduced when a voltage is applied between the drain and the source can be improved.

[0013] Effects of the Invention

[0014] An object of the present disclosure is to provide a semiconductor device capable of reducing on-resistance while maintaining a breakdown voltage and improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0016] Figure 2A It is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0017] Figure 2BThis is a schematic cross-sectional view showing a main current flowing in the semiconductor device according to the first embodiment.

[0018] Figure 3A This is a schematic plan view of a rough unit structure of the first transistor in Embodiment 1.

[0019] Figure 3B This is a schematic three-dimensional diagram of a rough unit structure of the first transistor in embodiment 1.

[0020] Figure 4 It is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0021] Figure 5A FIG. 1 is a schematic cross-sectional view showing an example of the structure of the first transistor of Comparative Example 1 of Embodiment 1. FIG.

[0022] Figure 5B So Figure 5A The structure of the semiconductor device shown is a schematic cross-sectional view which simulates the potential distribution generated when a rated voltage is applied between the drain and the source.

[0023] Figure 5C So Figure 5A The structure of the semiconductor device shown is a schematic cross-sectional view that simulates the electric field strength generated when a rated voltage is applied between the drain and the source.

[0024] Fig. 6A FIG. 1 is a schematic cross-sectional view showing an example of the structure of the first transistor of Comparative Example 2 of Embodiment 1. FIG.

[0025] Figure 6B So Fig. 6A The structure of the semiconductor device shown is a schematic cross-sectional view which simulates the potential distribution generated when a rated voltage is applied between the drain and the source.

[0026] Figure 6C So Fig. 6A The structure of the semiconductor device shown is a schematic cross-sectional view that simulates the electric field strength generated when a rated voltage is applied between the drain and the source.

[0027] Fig. 7A This is a schematic cross-sectional view showing an example of the structure of the first transistor according to Embodiment 1.

[0028] Figure 7B So Fig. 7A The structure of the semiconductor device shown is a schematic cross-sectional view simulating a potential distribution generated when a rated voltage is applied between the drain and the source.

[0029] Figure 7C So Fig. 7AThe structure of the semiconductor device shown is a schematic cross-sectional view that simulates the electric field strength generated when a rated voltage is applied between the drain and the source.

[0030] Figure 8 This is a schematic cross-sectional view showing an example of the structure of the first transistor according to Embodiment 1.

[0031] Fig. 9 This is a graph plotting the relationship between the gate trench depth difference Δ and the drain breakdown voltage VDS of the first transistor according to the first embodiment.

[0032] Fig. 10A This is a schematic cross-sectional view showing an example of the structure of the first transistor according to Embodiment 1.

[0033] Fig. 10B So Fig. 10A The structure of the semiconductor device shown is a schematic cross-sectional view which simulates the potential distribution generated when a rated voltage is applied between the drain and the source.

[0034] Fig. 10C So Fig. 10A The structure of the semiconductor device shown is a schematic cross-sectional view that simulates the electric field strength generated when a rated voltage is applied between the drain and the source.

[0035] Fig.11A This is a schematic cross-sectional view showing an example of the structure of the first transistor according to Embodiment 1.

[0036] Fig. 11B So Fig.11A The structure of the semiconductor device shown is a schematic cross-sectional view which simulates the potential distribution generated when a rated voltage is applied between the drain and the source.

[0037] Fig. 11C So Fig.11A The structure of the semiconductor device shown is a schematic cross-sectional view that simulates the electric field strength generated when a rated voltage is applied between the drain and the source.

[0038] Fig. 12A It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0039] Fig. 12B It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0040] Fig. 12C It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0041] Fig.12D It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0042] Fig.12E It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0043] Fig.12F It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0044] Figure 12G It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0045] Fig.13 This is a schematic cross-sectional view showing an example of the structure of the first transistor according to the second embodiment.

[0046] Fig.14 This is a schematic cross-sectional view showing an example of the structure of the first transistor according to the third embodiment. DETAILED DESCRIPTION

[0047] Hereinafter, a specific example of a semiconductor device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown here all represent a specific example of the present disclosure. Therefore, the numerical values, shapes, components, configurations and connection forms of the components, and steps (processes) and the order of the steps shown in the following embodiments are taken as examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily a strict illustration. In each figure, the same reference numerals are given to substantially the same structures, and repeated descriptions are omitted or simplified.

[0048] (Implementation Method 1)

[0049] [1. Structure of semiconductor device]

[0050] Hereinafter, the structure of the vertical field effect transistor of the present disclosure will be described by taking a double structure as an example, but it is not necessarily a double structure, and may be a single structure vertical field effect transistor, or may be a triple or more structure vertical field effect transistor.

[0051] Figure 1 This is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 2A This is a plan view, and the size, shape, and arrangement of electrode pads of the semiconductor device are only examples. Figure 2B This is a cross-sectional view schematically showing the main current flowing in the semiconductor device. Figure 1 and Figure 2B yes Figure 2A The section plane at I-I.

[0052] like Figure 1 and Figure 2AAs shown, the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, a first vertical field effect transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 in the semiconductor layer 40, and a second vertical field effect transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 in the semiconductor layer 40. Figure 2A As shown, the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40 . Figure 2A In FIG. 1 , a virtual boundary line 90 between the first area A1 and the second area A2 is indicated by a dotted line.

[0053] The semiconductor layer 40 is formed by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33. The semiconductor substrate 32 is arranged on the back side of the semiconductor layer 40 and is composed of first-conductivity-type silicon containing first-conductivity-type impurities. The low-concentration impurity layer 33 is arranged on the surface side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. It contains first-conductivity-type impurities at a concentration lower than the first-conductivity-type impurity concentration of the semiconductor substrate 32 and is of the first-conductivity-type.

[0054] The low-concentration impurity layer 33 can be formed, for example, by epitaxial growth on the semiconductor substrate 32. The low-concentration impurity layer 33 is also a drift layer common to the transistor 10 and the transistor 20, and is sometimes referred to as a drift layer in this specification.

[0055] The metal layer 30 is formed in contact with the back side of the semiconductor layer 40 and is composed of silver (Ag) or copper (Cu). In addition, the metal layer 30 may contain a trace amount of elements other than metals mixed as impurities in the manufacturing process of the metal material. In addition, the metal layer 30 may be formed on the entire back side of the semiconductor layer 40 or not.

[0056] like Figure 1 and Figure 2A As shown, a first body region 18 of a second conductivity type containing impurities of a second conductivity type different from the first conductivity type is formed in a first region A1 of the low-concentration impurity layer 33. A first source region 14 of a first conductivity type containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed in the first body region 18. The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 that penetrate the first source region 14 and the first body region 18 from the upper surface of the semiconductor layer 40 to a depth that reaches a portion of the low-concentration impurity layer 33, and the first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trenches 17.

[0057] The first source electrode 11 includes a portion 12 and a portion 13 . The portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 . The first gate conductor 15 is a buried gate electrode buried in the semiconductor layer 40 , and is electrically connected to the first gate electrode pad 119 .

[0058] The portion 12 of the first source electrode 11 is a layer that is bonded to the solder during reflow in face-down mounting, and can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium as a non-limiting example. The surface of the portion 12 can be plated with gold or the like.

[0059] The portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0060] A second body region 28 of the second conductivity type containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 of the first conductivity type containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28. The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 that penetrate the second source region 24 and the second body region 28 from the upper surface of the semiconductor layer 40 to a depth that reaches a portion of the low-concentration impurity layer 33, and the second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trenches 27.

[0061] The second source electrode 21 includes a portion 22 and a portion 23 . The portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 . The second gate conductor 25 is a buried gate electrode buried in the semiconductor layer 40 , and is electrically connected to the second gate electrode pad 129 .

[0062] The portion 22 of the second source electrode 21 is a layer that is bonded to the solder during reflow in face-down mounting, and can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium as a non-limiting example. The surface of the portion 22 can be plated with gold or the like.

[0063] The portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0064] With the above-described structures of the transistors 10 and 20, the semiconductor substrate 32 functions as a common drain region that makes common the first drain region of the transistor 10 and the second drain region of the transistor 20. In some cases, a portion of the low-concentration impurity layer 33 that is in contact with the semiconductor substrate 32 also functions as a common drain region. In addition, the metal layer 30 functions as a common drain electrode that makes common the drain electrode of the transistor 10 and the drain electrode of the transistor 20.

[0065] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 is provided through the opening of the interlayer insulating layer 34 and connected to the first source region 14. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 having an opening, and a portion 12 is provided through the opening of the passivation layer 35 and connected to the portion 13 of the first source electrode 11.

[0066] The second body region 28 is covered by an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 is provided which passes through the opening of the interlayer insulating layer 34 and is connected to the second source region 24. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 having an opening, and a portion 22 is provided which passes through the opening of the passivation layer 35 and is connected to the portion 23 of the second source electrode 21.

[0067] Therefore, the plurality of first source electrode pads 116 and the plurality of second source electrode pads 126 refer to the regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, that is, the so-called terminal portions. Similarly, the one or more first gate electrode pads 119 and the one or more second gate electrode pads 129 refer to the first gate electrode 19 (at Figure 1 , Figure 2A , Figure 2B ) and the second gate electrode 29 (in Figure 1 , Figure 2A , Figure 2B ) An area partially exposed on the surface of the semiconductor device 1, namely, a so-called terminal portion.

[0068] In the semiconductor device 1, for example, the first conductivity type can be set to N type, the second conductivity type can be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are N-type semiconductors, and the first body region 18 and the second body region 28 are P-type semiconductors.

[0069] In addition, in the semiconductor device 1, for example, the first conductivity type can be set to P type, the second conductivity type can be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are P type semiconductors, and the first body region 18 and the second body region 28 are N type semiconductors.

[0070] In the following description, the on-state operation of the semiconductor device 1 is described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors having an N-type as a first conductivity type and a P-type as a second conductivity type.

[0071] Here, the description is given on the premise that the transistor 10 and the transistor 20 have symmetry and have no difference in function, characteristics, structure, etc. Figure 1 , Figure 2A , Figure 2B Although the description is also made on the premise of symmetry, symmetry is not an essential condition for the dual-structure vertical field effect transistor of the chip size package type disclosed in the present invention.

[0072] [2. Operation of vertical field effect transistor]

[0073] Figure 3A and Figure 3B They are respectively a plan view and a perspective view of a rough unit structure of the transistor 10 (or the transistor 20 ) repeatedly formed in the X direction and the Y direction of the semiconductor device 1 . Figure 3A and Figure 3B In the figure, for easy understanding, the semiconductor substrate 32 and the first source electrode 11 (or the second source electrode 21) are not shown.

[0074] In addition, the so-called Y direction is a direction parallel to the upper surface of the semiconductor layer 40 and in which the first gate trench 17 and the second gate trench 27 extend. In addition, the so-called X direction refers to a direction parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction. The so-called Z direction refers to a direction orthogonal to both the X direction and the Y direction and represents the height direction of the semiconductor device. In the present disclosure, the Y direction is sometimes expressed as the first direction, the X direction is expressed as the second direction, and the Z direction is expressed as the third direction.

[0075] like Figure 3A and Figure 3B As shown, the transistor 10 is provided with a first connection portion 18A that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18A is a region of the first body region 18 where the first source region 14 is not formed, and contains the same second conductivity type impurities as the first body region 18. The first source region 14 and the first connection portion 18A are alternately and periodically arranged along the Y direction. The transistor 20 is also the same.

[0076] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage greater than a threshold value is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21, a conduction channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a main current flows in a path of the first source electrode 11-first connection portion 18A-first body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conduction channel formed in the second body region 28-second source region 24-second source electrode 21, and the semiconductor device 1 is turned on. In addition, a PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in the conduction path, and functions as a body diode. In addition, since the main current flows through the metal layer 30, the cross-sectional area of ​​the main current path is increased by making the metal layer 30 thicker, and the on-resistance of the semiconductor device 1 can be reduced.

[0077] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage above the threshold is applied to the first gate electrode 19 (first gate conductor 15) with reference to the first source electrode 11, a conduction channel is formed near the first gate insulating film 16 in the first body region 18. As a result, the main current flows in the path of the second source electrode 21-second connecting portion 28A-second body region 28-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conduction channel formed in the first body region 18-first source region 14-first source electrode 11, and the semiconductor device 1 is turned on. In addition, a PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in this conduction path, and functions as a body diode.

[0078] Figure 4 The diagram is a plan view showing an example of the shapes of the first and second body regions 18 and 28 and the first and second active regions 112 and 122 among the components of the semiconductor device 1 in a plan view of the semiconductor layer 40 (low-concentration impurity layer 33 ). Figure 4 Although not shown in the figure, the first gate trench 17 and the second gate trench 27 both extend in the Y direction.

[0079] The first active region 112 is a minimum range that includes all of the portions that form a conduction channel when a voltage above a threshold value is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portion that forms a conduction channel is a portion of each of the plurality of first gate trenches 17 that is adjacent to the first source region 14. In a plan view of the semiconductor layer 40, the first active region 112 is included in the first body region 18.

[0080] The second active region 122 is a minimum range that includes all of the portions that form a conduction channel when a voltage above a threshold value is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portion that forms a conduction channel is a portion of each of the plurality of second gate trenches 27 that is adjacent to the second source region 24. In a plan view of the semiconductor layer 40, the second active region 122 is included in the second body region 28.

[0081] A region surrounding the first active region 112 in the first region A1 is referred to as a first peripheral region, and a region surrounding the second active region 122 in the second region A2 is referred to as a second peripheral region.

[0082] The single-structure vertical field effect transistor can be roughly understood as being formed by only one side (transistor 10) of the double-structure vertical field effect transistor. However, in the chip-scale package type, a drain electrode pad is sometimes provided on the surface side of the semiconductor layer 40 having the source electrode pad 116 and the gate electrode pad 119. In this case, it is necessary to form a drain lead structure electrically connected to the semiconductor substrate 32 provided on the back side of the semiconductor layer 40 from the surface side of the semiconductor layer 40 in advance.

[0083] [3. Gate trench depth and transistor characteristics]

[0084] (3-1. Drain withstand voltage)

[0085] In the following description, only components of the transistor 10 will be described with respect to the semiconductor device 1 unless otherwise specified. Reference numerals assigned to components of the transistor 10 will be used as representatives unless necessary.

[0086] In the semiconductor device 1, the potential difference between the first source electrode 11 and the second source electrode 21 is set as the source-source voltage (VSS [V]). In the product specification of the semiconductor device 1, the maximum source-source voltage (BVSSS [V]) is set according to the application. In the present disclosure, the maximum source-source voltage (BVSSS [V]) is sometimes referred to as the withstand voltage or the drain withstand voltage. Or it is also called the rated voltage.

[0087] A PN junction is provided at the boundary between the first body region 18 and the low concentration impurity layer 33, and a depletion layer is formed across the PN junction. To improve the drain withstand voltage, a structure is required in which the depletion layer can be sufficiently extended when the transistor 10 is turned off, and the carrier concentration (resistivity) and thickness of the low concentration impurity layer 33 must be appropriately designed.

[0088] In order to fully expand the depletion layer, the low-concentration impurity layer 33 needs to have a low carrier concentration (high resistivity) and a thicker thickness. Since the thickness of the low-concentration impurity layer 33 can be relatively thick when viewed from the bottom of the first gate trench 17, in order to improve the drain withstand voltage, it is preferred that the first gate trench 17 is shallow.

[0089] In addition, the description in this embodiment is based on the description of all VSS and BVSSS for the dual-structure vertical field effect transistor, but in the case of a single-structure vertical field effect transistor, the drain-source voltage (VDS[V]) and the maximum drain-source specification voltage (BVDSS[V]) can be used respectively.

[0090] In the following, even in a dual-structure vertical field effect transistor, the source-source region is conveniently referred to as the drain-source region, and VDS and BVDSS are used for explanation.

[0091] (3-2. On-resistance)

[0092] The first gate trench 17 is formed from the upper surface of the semiconductor layer 40 to penetrate the first body region 18 in contact with the first source region 14 and to a depth reaching a portion of the low-concentration impurity layer 33. After passing through the first body region 18, the current flowing from the first source electrode 11 toward the semiconductor substrate 32 as the common drain flows in the low-concentration impurity layer 33 along the first gate trench 17 until reaching the bottom end of the first gate trench 17.

[0093] The current flowing along the bottom of the first gate trench 17 also flows in the low-concentration impurity layer 33 with relatively low on-resistance under the influence of the voltage applied to the first gate conductor 15. However, when the current exceeds the bottom of the first gate trench 17, the current flows due to resistance corresponding to the resistivity of the low-concentration impurity layer 33.

[0094] Therefore, when the first gate trench 17 is relatively shallow, the current flows over a relatively long distance inside the low-concentration impurity layer 33 before reaching the semiconductor substrate 32. On the contrary, when the first gate trench 17 is relatively deep, the current flows over a relatively short distance inside the low-concentration impurity layer 33 before reaching the semiconductor substrate 32. Therefore, in order to reduce the resistance of the current flowing through the low-concentration impurity layer 33, it is preferable that the first gate trench 17 is deep.

[0095] (3-3. Electric field strength and reliability)

[0096] In the semiconductor device 1, when VDS is increased, the potential distribution in the low-concentration impurity layer 33 changes. Since the first gate trench 17 is a groove whose bottom is formed to a depth reaching a part of the low-concentration impurity layer 33, the potential distribution in the low-concentration impurity layer 33 changes according to its width, interval, and depth.

[0097] Figure 5A This is Comparative Example 1 of the present embodiment 1, and is a structure in which all first gate trenches 17 are formed in the same manner with a certain depth Da [nm]. Figure 5B In Figure 5A The results are obtained by simulating the distribution of the potential [V] when a voltage is applied until VDS=BVDSS (here, 22 V) in a state where the applied voltage to the first gate conductor 15 is zero.

[0098] also, Fig. 6A This is a comparative example 2 of the present embodiment 1, and is a structure in which all first gate trenches 17 are formed in the same manner with a certain depth Db [nm] (Da < Db). Figure 6B In Fig. 6A The results are obtained by simulating the distribution of the potential [V] when a voltage is applied until VDS=BVDSS (here, 22 V) in a state where the applied voltage to the first gate conductor 15 is zero.

[0099] In Comparative Example 1 ( Figure 5A , Figure 5B ) and Comparative Example 2 ( Fig. 6A , Figure 6B ), only the depth of the first gate trench 17 is changed, and the position of the PN junction remains unchanged.

[0100] Comparative Example 1 ( Figure 5A , Figure 5B ) is shown in Comparative Example 2 ( Fig. 6A , Figure 6B ) compared to the case where the first gate trench 17 is also relatively shallow. Fig. 6A , Figure 6B ) shows the difference with Comparative Example 1 ( Figure 5A , Figure 5B ) compared to the case where the first gate trench 17 is also relatively deep. Figure 5A , Figure 5B ) and the first gate trench 17 shown in Comparative Example 2 ( Fig. 6A , Figure 6B ) shown in FIG. 1 , the difference in depth of the first gate trench 17 is 100 nm.

[0101] Figure 5B In the figure, from the bottom of the first gate trench 17, Figure 6B In contrast, the low-concentration impurity layer 33 is relatively thick, so the potential distribution of VDS=BVDSS is in a thick range, and the interval between equipotential lines near the bottom of the first gate trench 17 becomes wider. This means that the electric field strength in the low-concentration impurity layer 33 is relatively weak.

[0102] In contrast, Figure 6B In the figure, from the bottom of the first gate trench 17, Figure 5B In contrast, the low-concentration impurity layer 33 is relatively thin, so the potential distribution of VDS=BVDSS is in a thin range, and the interval between equipotential lines near the bottom of the first gate trench 17 is narrowed. This means that the electric field strength in the low-concentration impurity layer 33 is relatively strong.

[0103] Figure 5C , Figure 6C The distribution of the potential is expressed by light and dark. Figure 5B , Figure 6B The results are obtained by simulating the distribution of electric field intensity [V / cm] at Figure 5C , Figure 6C The maximum electric field strength is at the center of the bottom of the first gate trench 17. The difference in electric field strength at this position is calculated by comparing the difference in electric field strength of the first gate trench 17 with that of the first gate trench 17. Figure 5C ) and Comparative Example 2 ( Figure 6C ) for comparison, it is 0.02MV / cm.

[0104] When the electric field intensity near the first gate trench 17 becomes greater than a certain level, carriers are accumulated near the first gate insulating film 16 and become so-called hot electrons. If hot electrons are generated, an inversion layer is generated even if a gate voltage is not applied to the first gate conductor 15, thereby forming a conductive channel, which becomes a factor in reducing the reliability of the transistor 10.

[0105] according to Figure 5C , Figure 6C Since the electric field intensity increases as the first gate trench 17 becomes deeper, it is preferable that the first gate trench 17 be shallower from the viewpoint of preventing reliability degradation.

[0106] [4. Mixed existence of shallow gate trenches and deep gate trenches]

[0107] As described above, the characteristics of the transistor 10 are closely related to the depth of the first gate trench 17. There is a trade-off relationship depending on the characteristics, and it is difficult to optimize all the characteristics. The depth of the first gate trench 17 needs to be appropriately designed according to the intended use.

[0108] Therefore, the inventors have repeatedly conducted careful studies and found that by mixing trenches with different depths in a plurality of first gate trenches 17, the characteristics of the transistor 10 can be improved compared to the case where the depths of all the first gate trenches 17 are uniform as in Comparative Examples 1 and 2. The following describes the effect of the mixing of trenches with different depths from the upper surface of the semiconductor layer 40 in the first gate trench 17 on the characteristics of the transistor 10.

[0109] The difference in the depth of the first gate trench 17 that is the subject of the present disclosure does not refer to a variation that is unavoidable in manufacturing, but refers to a difference in design that is intentionally expressed by setting a target value.

[0110] First, as an example, use Fig. 7A , explaining the situation where two trenches of depth Da [nm] and Db [nm] (Da<Db) are mixed in the plurality of first gate trenches 17. For convenience, hereinafter, regardless of the first gate trench 17 or the second gate trench 27, the trench of depth Da is referred to as the third gate trench 171, and the trench of depth Db is referred to as the fourth gate trench 172. The third gate trench 171 becomes a relatively shallow gate trench, and the fourth gate trench 172 becomes a relatively deep gate trench.

[0111] The gate conductor and the gate insulating film provided in the third gate trench 171 are respectively referred to as the third gate conductor 151 and the third gate insulating film 161. The gate conductor and the gate insulating film provided in the fourth gate trench 172 are respectively referred to as the fourth gate conductor 152 and the fourth gate insulating film 162.

[0112] Fig. 7A This is a schematic diagram of a portion of the transistor 10 cut along the XZ plane, and the components above the interlayer insulating layer 34, such as the first source electrode 11, and the lower components including the semiconductor substrate 32 are omitted from the illustration. Fig. 7A In the structure, the third gate trenches 171 and the fourth gate trenches 172 are alternately arranged one by one with the same width at equal intervals.

[0113] Figure 7B Expressing Fig. 7A The distribution of the potential [V] when a voltage is applied to the third gate conductor 151 and the fourth gate conductor 152 under the structure is simulated until VDS=BVDSS (here, 22V) is reached. Figure 7C The distribution of the potential is expressed in shades. Figure 7B The results are obtained by simulating the distribution of electric field intensity [V / cm] when .

[0114] from Figure 7B It can be seen that the potential in the drift layer 33 is pushed downward as a whole due to the fourth gate trench 172, and the interval between equipotential lines near the third gate trench 171 is relatively widened. As a result, the electric field intensity at the bottom center of the third gate trench 171 is reduced.

[0115] Fig. 7A The depth Da of the third gate trench 171 in Figure 5A The depth Da of the first gate trench 17 of (Comparative Example 1) is the same, but the depth Da of all the first gate trenches 17 is the same as that of the case where the first gate trenches 17 are unified to the same depth. Figure 5A By comparison, it can be seen that the electric field intensity at the center of the bottom of the third gate trench 171 is reduced. The reason why the electric field intensity at the center of the bottom of the third gate trench 171 is reduced despite the same depth Da is that the fourth gate trench 172 pushes the potential down toward the low-concentration impurity layer 33, and the fourth gate trench 172 deeper than the third gate trench 171 exists near the third gate trench 171. That is, this effect cannot be obtained according to the conventional structure in which the depth of all the first gate trenches 17 is unified.

[0116] On the other hand, the electric field intensity at the bottom center of the fourth gate trench 172 increases. Fig. 6A The depth of the first gate trench 17 in (Comparative Example 2) is Fig. 7A The depth of the fourth gate trench 172 in is Db, but Fig. 6A The depth of all first gate trenches 17 is uniform. Figure 6C and Figure 7C Comparing the electric field strength, we can see that Figure 6C Compared with the electric field strength at the bottom center of the first gate trench 17, Figure 7C The electric field intensity is stronger at the bottom center of the fourth gate trench 172.

[0117] This is because, when all the first gate trenches 17 are unified to the same depth, all the first gate trenches 17 change the potential in the same manner, whereas, in the case of Figure 7B When only a part of the fourth gate trench 172 lowers the potential in this way, the potential is suddenly changed locally only in the vicinity.

[0118] If the electric field strength increases at the bottom end of the first gate trench 17, hot electrons are generated near the first gate insulating film 16, which increases the possibility of reducing reliability, which is not preferable. Figure 7C The number of the fourth gate trenches 172 with increased electric field strength at the bottom center is greater than Figure 6CThat is, the resistance to reliability degradation is improved in the structure, and even if an electric field strength greater than that in the past is generated, it does not directly affect the degradation of reliability.

[0119] The essence of bringing about the effect of the present disclosure is that, unlike the conventional structure, instead of unifying all the first gate trenches 17 to the same depth, relatively deep fourth gate trenches 172 are provided at an appropriate number, distance, and period relative to relatively shallow third gate trenches 171. According to such a structure, the electric field intensity at the bottom center of the third gate trench 171 can be reduced, and the upper limit of the electric field intensity related to reliability degradation can be increased to improve tolerance.

[0120] The above describes an embodiment in which the third gate trench 171 and the fourth gate trench 172 are alternately arranged one by one. Preferably, the fourth gate trench 172 is arranged on both sides of the third gate trench 171 in the X direction to reduce the electric field intensity at the bottom center of the third gate trench 171. The most effective configuration is a structure in which the third gate trench 171 and the fourth gate trench 172 are alternately arranged one by one in the X direction.

[0121] The configuration that can achieve the effects of the present disclosure is not limited thereto, and the number of third gate trenches 171 sandwiched between the most adjacent pairs of fourth gate trenches 172 in the X direction may be plural. Figure 8 An example thereof is shown in . If the number of third gate trenches 171 provided in the transistor 10 is n (n is an integer greater than or equal to 1), the number of fourth gate trenches 172 provided in the transistor 10 is preferably greater than or equal to 2 and less than or equal to (n+1).

[0122] Preferably, among the first gate trenches 17 provided in the first active region 112 of the transistor 10, the trenches located at the two ends in the X direction are set as the fourth gate trenches 172, and the remaining structures are set as the third gate trenches 171. With such an arrangement, the electric field intensity at the bottom center of the third gate trench 171 provided in the first active region 112 can be suppressed.

[0123] In addition, it is preferred that the first gate trench 17 provided in the first active region 112 of the transistor 10 is obtained by taking a structure in which a pair of fourth gate trenches 172 that are most adjacent in the X direction have one or more third gate trenches 171 sandwiched therebetween as a unit structure, and periodically arranging the unit structure in the X direction, and the fourth gate trench 172 arranged at the extreme end of the unit structure is shared by adjacent unit structures.

[0124] That is, with respect to the first gate trench 17 provided in the first active region 112 of the transistor 10, it is preferable that the fourth gate trench 172 is periodically provided at a certain interval in the X direction within the arrangement of the third gate trenches 171. By arranging the third gate trench 171 and the fourth gate trench 172 in this way, the electric field intensity at the bottom center of the third gate trench 171 provided in the first active region 112 can be suppressed.

[0125] In particular, when the first gate trench 17 is composed of n third gate trenches 171 and n+1 fourth gate trenches 172, among the first gate trenches 17 provided in the transistor 10 (first active region 112), the trenches located at the two ends in the X direction can be set as the fourth gate trenches 172, and the third gate trenches 171 and the fourth gate trenches 172 can be alternately provided one by one. In this case, the electric field intensity at the bottom center of all the third gate trenches 171 can be suppressed, which is preferable.

[0126] It is preferable that the interval Laa [μm] between the third gate trenches 171 is constant. In addition, it is preferable that the interval Lbb [μm] between the fourth gate trenches 172 is constant.

[0127] Furthermore, if the third gate trench 171 and the fourth gate trench 172 are alternately arranged one by one, Laa=Lbb is preferred, and Lab=Laa / 2=Lbb / 2 is also preferred for the interval Lab [μm] between the third gate trench 171 and the fourth gate trench 172. In this case, the conduction channels can be arranged at the same density for the third gate trench 171 and the fourth gate trench 172, so it is effective for reducing the on-resistance.

[0128] In addition, although it will be described separately, the gate trenches (the first gate trench 17 or the second gate trench 27, or the third gate trench 171 or the fourth gate trench 172) that are the subject of the present disclosure all contribute to the formation of the conductive channel, including the gate conductor (the first gate conductor 15 or the second gate conductor 25, or the third gate conductor 151 or the fourth gate conductor 152).

[0129] The third gate conductor 151 and the fourth gate conductor 152 have the same potential when the transistor 10 is driven, and the voltage applied to the first gate electrode 19 is applied equally to both the third gate conductor 151 and the fourth gate conductor 152 .

[0130] As for the shape, even if it is a trench, it is excluded if it surrounds the first active region 112 and is provided in the first peripheral region of the semiconductor device 1. In addition, even if it is provided in the first active region 112, it is excluded if it does not contribute to the formation of the conduction channel. Therefore, the first gate trench 17 (the third gate trench 171 and the fourth gate trench 172) described in the present disclosure all have a portion connected to the first source region 14 at the top and a portion connected to the first body region 18 at the bottom.

[0131] Next, the relationship between the difference Δ(=Db−Da) [nm] between the depth Da of the third gate trench 171 and the depth Db of the fourth gate trench 172 in the transistor 10 , and the drain breakdown voltage VDS and on-resistance of the transistor 10 will be described.

[0132] The results of the simulation of the relationship between Δ(=Db-Da) [nm] and the drain withstand voltage VDS in the transistor 10 are shown in Table 1. In the simulation, it is assumed that the third gate trench 171 and the fourth gate trench 172 with equal internal width are arranged alternately one by one, and Lab=Laa / 2=Lbb / 2=0.40μm. In addition, the depth Da=1040nm of the third gate trench 171 is the same in all standards 1 to 8.

[0133]

Table 1

[0134]

[0135] The withstand voltages shown in Table 1 were calculated under two conditions: condition A, where the resistivity and thickness of the low-concentration impurity layer 33 were unified without changing for each standard, and condition B, where the thickness of the low-concentration impurity layer 33 was increased in accordance with the increase in the depth Db of the fourth gate trench 172 based on the shape of standard 2. In addition, standard 1 corresponds to Figure 5A , Figure 5B , Figure 5C , criterion 2 corresponds to Fig. 7A , Figure 7B , Figure 7C In addition, condition B was simulated only for criteria 3 to 7.

[0136] The results of Table 1 are plotted under both condition A (○) and condition B (◇) Fig. 9 .according to Fig. 9 Under condition A (○), in the process of VDS decreasing corresponding to the increase of Δ, it can be seen that the reduction ratio of VDS temporarily becomes gentle near Δ = 160nm. In addition, under condition B (◇), starting from Δ = 160nm, VDS increases as Δ increases.

[0137] It should be noted that the trend of the withstand voltage changes with Δ=160 nm as the boundary. In particular, it should be noted that under condition B (◇), in the range of Δ≥160 nm, VDS does not decrease or increases in a convergent manner.

[0138] exist Fig. 10B , Fig. 10C , the results of simulation of the distribution of the potential [V] and the electric field intensity [V / cm] at Db = 1200nm (Δ = 160nm) shown in Standard 5 of Table 1 are shown. Fig. 11B , Fig. 11C , the results of simulating the distribution of the potential [V] and the form of the electric field intensity [V / cm] at Db=1400nm (Δ=360nm) shown in Standard 7 of Table 1 are shown. Fig. 10B , Fig. 10C is Fig. 10A In the structure shown, the simulation results are shown when a voltage is applied to the third gate conductor 151 and the fourth gate conductor 152 until VDS=BVDSS (22 V in this case) while the voltage applied to the third gate conductor 151 and the fourth gate conductor 152 is zero. Fig. 11B , Fig. 11C is Fig.11A The simulation results are shown in the structure shown in the figure, when the voltage applied to the third gate conductor 151 and the fourth gate conductor 152 is zero until VDS=BVDSS (here 22V). In addition, the simulation results when Db=1140nm (Δ=100nm) are Figure 7B , Figure 7C .

[0139] Will Figure 7B , Fig. 10B , Fig. 11B as well as Figure 7C , Fig. 10C , Fig. 11C By comparison, it can be seen that as the depth of the fourth gate trench 172 increases, the electric field intensity at the bottom center of the third gate trench 171 decreases, just around Δ=160nm ( Fig. 10C This is because the fourth gate trench 172 provided on both sides of the third gate trench 171 presses down the potential from the bottom end of the third gate trench 171 to 160 nm, thereby eliminating the potential distribution that increases the electric field strength at the bottom center of the third gate trench 171.

[0140] Therefore, it can be said that in the case of being relatively shallow, the electric field intensity at the bottom center of the third gate trench 171 does not further decrease significantly. Fig. 9This phenomenon is an effect that cannot be obtained by forming all the first gate trenches 17 to the same depth as in the conventional structure.

[0141] Therefore, when the third gate trench 171 and the fourth gate trench 172 are alternately arranged at equal intervals, it is preferable to adjust to Δ≥160nm. That is, it is preferable that the difference between the depth of the third gate trench 171 and the depth of the fourth gate trench 172 is 160nm or more. If Δ≥160nm is set, by adjusting the thickness of the low-concentration impurity layer 33, it is possible to Fig. 9 In addition, if the need to increase the margin of the withstand voltage is low, the amount of the increase in the withstand voltage can be converted into adjusting the resistivity and thickness of the low-concentration impurity layer 33 to reduce the on-resistance. Even if Δ<160nm, a certain effect can be obtained, but in order to ensure sufficient margin for the withstand voltage and reduce the on-resistance of the low-concentration impurity layer 33, it is preferably adjusted to Δ≥160nm.

[0142] [5. Method for individually controlling the depth of the gate trench]

[0143] An example of a method for manufacturing the transistor 10 in Embodiment 1 will be described. The description will be given by taking as an example a case where the third gate trenches 171 and the fourth gate trenches 172 are alternately formed.

[0144] like Fig. 12A As shown, a mask layer 36 made of oxide or the like is formed on the upper surface of the semiconductor layer 40 (semiconductor substrate 32 and low-concentration impurity layer 33).

[0145] Then as Fig. 12B As shown in FIG. 1 , the resist coated on the mask layer 36 is patterned so that openings are provided at a certain interval in the X direction. At this time, the width of the opening of the resist in the X direction finally becomes the internal width of the fourth gate trench 172. Furthermore, when the transistor 10 is formed so that the internal width and interval of the third gate trench 171 and the fourth gate trench 172 are equal, the patterning is performed so that Fig. 12B The width of the non-opening portion in the X direction covered by the resist is approximately three times the width of the opening portion in the X direction from which the resist has been removed.

[0146] Then as Fig. 12C As shown in FIG. 1 , the opening of the resist is etched to remove the mask layer 36. The mask layer 36 may not be completely removed but may remain on the semiconductor layer 40 with a certain thickness, but it is preferred that the mask layer 36 be Fig. 12C All are removed as shown.

[0147] Then as Fig.12DAs shown, the remaining resist is patterned again, and the newly exposed portions of the mask layer 36 are periodically arranged in the X direction. The width of the opening newly provided in the resist in the X direction finally becomes the inner width of the third gate trench 171 .

[0148] Then as Fig.12E As shown, Fig.12D In the process, the newly exposed portion of the mask layer 36 is etched, and the mask layer 36 is removed in such a manner that a certain thickness remains on the semiconductor layer 40.

[0149] Then as Fig.12F As shown, the resist is removed.

[0150] Then as Figure 12G As shown, the mask layer 36 and the semiconductor layer 40 are etched using the partially remaining mask layer 36 as a mask. Figure 12G At the time of the mask layer 36, only the portion which will become the third gate trench 171 later is selectively provided with a thinner thickness. Figure 12G In the etching process shown, etching of the semiconductor layer 40 begins at the portion where the mask layer 36 was originally removed. With respect to the portion where the mask layer 36 remains relatively thin, the mask layer 36 is first completely removed, and then the semiconductor layer 40 immediately below begins to be etched. However, at this point in time, etching of the semiconductor layer 40 progresses at the portion where the mask layer 36 was originally removed, so that grooves of different depths are alternately formed in the semiconductor layer 40.

[0151] By adjusting the thickness of the mask layer 36, the etching conditions, Fig.12E In the illustrated process, the difference in depth between the third gate trench 171 and the fourth gate trench 172 can be controlled by controlling the remaining thickness of the mask layer 36 remaining on the upper surface of the semiconductor layer 40 .

[0152] In addition, the internal width of the third gate trench 171 and the internal width of the fourth gate trench 172, or the interval between the third gate trenches 171, the interval between the fourth gate trenches 172, the interval between the third gate trench 171 and the fourth gate trench 172, etc. can be freely designed by controlling the size of the anti-etching agent layout.

[0153] (Implementation Method 2)

[0154] Hereinafter, a transistor 10A of the semiconductor device 1 of the second embodiment having a configuration in which a part of the structure of the transistor 10 of the semiconductor device 1 of the first embodiment is modified will be described.

[0155] The transistor 10 is an example of a structure in which the first gate trench 17 is composed of a third gate trench 171 and a fourth gate trench 172 , and has a third gate conductor 151 and a third gate insulating film 161 provided in the third gate trench 171 , and a fourth gate conductor 152 and a fourth gate insulating film 162 provided in the fourth gate trench 172 .

[0156] In contrast, the transistor 10A of embodiment 2 is an example of a structure in which the first gate trench 17 of the transistor 10A of embodiment 2 is composed of a third gate trench 171 and a fourth gate trench 172, and has a third gate conductor 151A and a third gate insulating film 161A arranged in the third gate trench 171, and a fourth gate conductor 152A and a fourth gate insulating film 162A arranged in the fourth gate trench 172.

[0157] Here, regarding the transistor 10A of the second embodiment, the same components as those of the transistor 10 are assigned the same reference numerals as those already described, and detailed description thereof is omitted, and the description will focus on the differences from the transistor 10 .

[0158] Fig.13 Schematic diagram showing the shape of transistor 10A according to the second embodiment. Fig.13 This is a schematic diagram of a portion of the transistor 10A cut along the XZ plane, and components above the interlayer insulating layer 34 such as the first source electrode 11 and lower components including the semiconductor substrate 32 are not shown.

[0159] The difference between the second embodiment and the first embodiment is that the shapes of the third gate insulating film 161A and the fourth gate insulating film 162A are different. In particular, the fourth gate insulating film 162A is thicker at the bottom of the fourth gate trench 172 than at the top of the fourth gate trench 172 .

[0160] As described in Embodiment 1, the fourth gate trench 172 is a relatively deep trench, so the electric field strength at the center of the bottom is increased. If the fourth gate insulating film 162A is extremely thin, the structure cannot withstand the increased electric field strength, and a portion where current leakage may occur between the drain and the gate. Therefore, it is preferable to provide the fourth gate insulating film 162A thickly only on the bottom side of the fourth gate trench 172 so as to largely cover the portion where the electric field strength is increased, that is, the bottom end of the fourth gate trench 172.

[0161] Fig.13 In the embodiment, the fourth gate insulating film 162A is exemplified as having the same thickness at the bottom side of the fourth gate trench 172, but the effect of the second embodiment is not limited to Fig.13The fourth gate insulating film 162A may be provided along the shape of the fourth gate trench 172 so that only a portion of the side surface and the bottom side are thickened, and the thickened portion may have a multilayer structure of insulating films of different materials.

[0162] In addition, the third gate insulating film 161A may be Fig.13 As shown in the figure, similarly to the third gate insulating film 161 in Embodiment 1, the thickness does not change at the side and bottom of the third gate trench 171 but is constant. This is because since the electric field strength generated at the bottom of the third gate trench 171 does not increase excessively, it is not necessary to have a thick third gate insulating film 161A. Therefore, it is preferable that the fourth gate insulating film 162A, which is necessary to improve the resistance to the relatively increased electric field strength, has a portion thicker than the third gate insulating film 161A. In particular, it is preferable to provide the fourth gate insulating film 162A thicker on the bottom side of the fourth gate trench 172.

[0163] However, depending on the relative relationship between the depth difference, interval, and number of the third gate trench 171 and the fourth gate trench 172, the electric field intensity at the bottom of the third gate trench 171 may be increased to some extent. In such a case, the bottom side of the third gate insulating film 161A may be thickened similarly to the fourth gate insulating film 162A. In this case, the third gate insulating film 161A and the fourth gate insulating film 162A may be provided with the same thickness, or the fourth gate insulating film 162A may be provided in a relatively thicker manner.

[0164] (Implementation method 3)

[0165] Hereinafter, a transistor 10B of the semiconductor device 1 of the third embodiment having a configuration in which a part of the structure of the transistor 10 of the semiconductor device 1 of the first embodiment is modified will be described.

[0166] The transistor 10 is an example in which the low-concentration impurity layer 33 is composed of one layer. In contrast, the transistor 10B of the third embodiment is an example in which the transistor 10B of the third embodiment has a low-concentration impurity layer 33B having a two-layer structure.

[0167] Here, regarding the transistor 10B of the third embodiment, the same components as those of the transistor 10 are assigned the same reference numerals as those already described, and detailed description thereof is omitted, and the description will focus on the differences from the transistor 10 .

[0168] Fig.14 Schematic diagram showing the shape of transistor 10B according to the third embodiment. Fig.14This is a schematic diagram of a portion of the transistor 10B cut along the XZ plane, and the components above the interlayer insulating layer 34 such as the first source electrode 11 and the lower components including the semiconductor substrate 32 are omitted from illustration.

[0169] like Fig.14 As shown, the low-concentration impurity layer 33B of the transistor 10B has a two-layer structure. The low-concentration impurity layer 33B is formed by first stacking a second low-concentration impurity layer 332 on a semiconductor substrate 32 (not shown) and then stacking a first low-concentration impurity layer 331 thereon.

[0170] The first low-concentration impurity layer 331 is a layer having a lower resistivity than the second low-concentration impurity layer 332, and the second low-concentration impurity layer 332 is a layer having a higher resistivity than the first low-concentration impurity layer 331. For example, when comparing the impurity concentrations within the low-concentration impurity layer 33B, the first conductivity type impurity concentration in the first low-concentration impurity layer 331 is higher than the first conductivity type impurity concentration in the second low-concentration impurity layer 332.

[0171] In addition, in the third embodiment, the bottom end of the third gate trench 171 is formed so as to reach the inside of the first low-concentration impurity layer 331. Furthermore, the bottom end of the third gate trench 171 is not formed so as to penetrate the first low-concentration impurity layer 331 and reach the second low-concentration impurity layer 332. In addition, the bottom end of the fourth gate trench 172 is formed so as to reach the inside of the second low-concentration impurity layer 332. Furthermore, the bottom end of the fourth gate trench 172 is not formed so as to penetrate the second low-concentration impurity layer 332 and reach the semiconductor substrate 32.

[0172] When the third gate trench 171 is arranged so that the bottom end is confined inside the first low-concentration impurity layer 331 as described above, the main current passing through the conduction channel formed by the third gate trench 171 passes through the first low-concentration impurity layer 331 and the second low-concentration impurity layer 332 directly below the third gate trench 171 to reach the semiconductor substrate 32. Since the first low-concentration impurity layer 331 has a relatively low resistivity, the resistance of the main current flowing through the low-concentration impurity layer 33 can be reduced.

[0173] On the other hand, when the first low-concentration impurity layer 331 has a relatively low resistivity, the electric field strength generated near the bottom end of the third gate trench 171 increases. However, according to the structure of the present disclosure, by providing the fourth gate trench 172, the electric field strength near the bottom end of the third gate trench 171 is originally reduced. Therefore, the increase in the electric field strength can be offset to a certain extent. The resistivity or thickness of the first low-concentration impurity layer 331 can be appropriately selected by considering the influence of the increase or decrease in the electric field strength near the bottom end of the third gate trench 171 and the influence of the current flowing through the first low-concentration impurity layer 331 on the resistance.

[0174] If the bottom end of the fourth gate trench 172 is set in a manner limited inside the second low-concentration impurity layer 332, since the second low-concentration impurity layer 332 has a relatively high resistivity, it is possible to reduce the electric field intensity generated near the bottom end of the fourth gate trench 172. This effect is suitable for alleviating the side effect that the electric field intensity near the bottom end of the fourth gate trench 172 is originally increased corresponding to the fact that the electric field intensity near the bottom end of the third gate trench 171 is reduced in the structure of the present disclosure.

[0175] On the other hand, the main current passing through the conduction channel formed by the fourth gate trench 172 passes through the second low-concentration impurity layer 332 directly below the fourth gate trench 172 in order to reach the semiconductor substrate 32. Since the second low-concentration impurity layer 332 has a relatively high resistivity, the resistance of the main current flowing through the low-concentration impurity layer 33 increases, but in the structure of the present disclosure, since the fourth gate trench 172 is formed relatively deep, the distance that the main current flows in the second low-concentration impurity layer 332 can be not excessively increased.

[0176] As described above, in the third embodiment, by appropriately forming the low-concentration impurity layer 33B into a two-stage structure, it is possible to reduce the side effects associated with the third gate trench 171 and the fourth gate trench 172 that occur in the present disclosure.

[0177] (Replenish)

[0178] The semiconductor device of one embodiment of the present disclosure is described above based on the embodiments, but the present disclosure is not limited to these embodiments. As long as it does not deviate from the main purpose of the present disclosure, the various forms obtained by implementing various modifications that a person skilled in the art can think of to these embodiments, or the forms constructed by combining the constituent elements in different modified examples can also be included in the scope of one or more forms of the present disclosure.

[0179] In addition, in the present disclosure, regarding the structure of the vertical field effect transistor, a dual structure is first used as an example to explain, and the gate trench of the first transistor is set to the first gate trench, and the gate trench of the second transistor is set to the second gate trench. In order to avoid confusion, in the present disclosure, the relatively shallow gate trench is consistently set to the third gate trench and the relatively deep gate trench is set to the fourth gate trench for explanation, but the structure of the vertical field effect transistor that can obtain the effect of the present disclosure is not limited to the dual structure. Therefore, it is not necessary to distinguish the first transistor from the second transistor, and the third gate trench can also be renamed as the first gate trench, and the fourth gate trench can be renamed as the second gate trench.

[0180] Industrial Applicability

[0181] A semiconductor device including the vertical field effect transistor of the present invention can be widely used as a device for controlling the conduction state of a current path.

[0182] Description of symbols

[0183] 1Semiconductor device

[0184] 10, 10A, 10B transistor (first vertical field effect transistor)

[0185] 11 first source electrode

[0186] Parts 12, 13, 22, 23

[0187] 14 First source region

[0188] 15 First gate conductor

[0189] 16. First gate insulating film

[0190] 17 First gate trench

[0191] 18 First Body Region

[0192] 18A First connection

[0193] 19 first gate electrode

[0194] 20 transistor (second vertical field effect transistor)

[0195] 21 second source electrode

[0196] 24 Second source region

[0197] 25 Second gate conductor

[0198] 26. Second gate insulating film

[0199] 27 Second gate trench

[0200] 28 Second body region

[0201] 28A Second connection

[0202] 29 second gate electrode

[0203] 30 Metal Layer

[0204] 32 Semiconductor substrate

[0205] 33, 33B low concentration impurity layer (drift layer)

[0206] 34 Interlayer insulation layer

[0207] 35 Passivation layer

[0208] 36 Mask layer

[0209] 40 Semiconductor layer

[0210] 90 Boundary Line

[0211] 112 First active region

[0212] 116 first source electrode pad

[0213] 119 first gate electrode pad

[0214] 122 Second active region

[0215] 126 second source electrode pad

[0216] 129 second gate electrode pad

[0217] 151, 151A third gate conductor

[0218] 152, 152A fourth gate conductor

[0219] 161, 161A third gate insulating film

[0220] 162, 162A fourth gate insulating film

[0221] 171 Third gate trench

[0222] 172 Fourth gate trench

[0223] 331 First low concentration impurity layer

[0224] 332 Second low concentration impurity layer

Claims

1. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized in that: It is a vertical field effect transistor with: A semiconductor substrate of the first conductivity type containing the above-mentioned impurities of the first conductivity type; The first conductivity type low concentration impurity layer is formed in contact with the semiconductor substrate and contains the first conductivity type impurities at a concentration lower than the first conductivity type impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer; The source region of the first conductivity type is formed in the body region; A source electrode electrically connected to the body region and the source region; A first gate trench is formed from the upper surface of the low-concentration impurity layer to penetrate the body region to a depth reaching a portion of the low-concentration impurity layer, has a portion in contact with the source region, and extends in a first direction parallel to the upper surface of the low-concentration impurity layer; A second gate trench, which penetrates the body region from the upper surface of the low-concentration impurity layer and is formed deeper than the first gate trench, has a portion in contact with the source region, and extends in the first direction; A first gate insulating film is formed inside the first gate trench; A first gate conductor formed on the first gate insulating film; A second gate insulating film is formed inside the second gate trench; and a second gate conductor formed on the second gate insulating film; The first gate conductor and the second gate conductor have the same potential, When the number of the first gate trenches is n, the number of the second gate trenches is greater than or equal to 2 and less than or equal to n+1, where n is an integer greater than or equal to 1. The second gate trench is provided at the end of the region where the first gate trench and the second gate trench are provided in a second direction parallel to the upper surface of the low-concentration impurity layer and orthogonal to the first direction. In the second direction, the region where the first gate trench and the second gate trench are provided is formed by periodically providing the unit structure with the structure in which the most adjacent pair of the second gate trenches sandwiches one of the first gate trenches therebetween as a unit structure, The second gate trench provided at the end of the unit structure is shared by adjacent unit structures. The first gate trenches and the second gate trenches are alternately arranged one by one in the second direction. The interval between the first gate trench and the second gate trench in the second direction is constant. A difference between a depth of the first gate trench and a depth of the second gate trench is greater than or equal to 160 nm.

2. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized in that: It is a vertical field effect transistor with: a semiconductor substrate of the first conductivity type containing the impurities of the first conductivity type; The first conductivity type low concentration impurity layer is formed in contact with the semiconductor substrate and contains the first conductivity type impurities at a concentration lower than the first conductivity type impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer; The source region of the first conductivity type is formed in the body region; A source electrode electrically connected to the body region and the source region; A first gate trench is formed from the upper surface of the low-concentration impurity layer to penetrate the body region to a depth reaching a portion of the low-concentration impurity layer, has a portion in contact with the source region, and extends in a first direction parallel to the upper surface of the low-concentration impurity layer; A second gate trench, which penetrates the body region from the upper surface of the low-concentration impurity layer and is formed deeper than the first gate trench, has a portion in contact with the source region, and extends in the first direction; A first gate insulating film is formed inside the first gate trench; A first gate conductor formed on the first gate insulating film; A second gate insulating film is formed inside the second gate trench; and a second gate conductor formed on the second gate insulating film; The first gate conductor and the second gate conductor have the same potential, When the number of the first gate trenches is n, the number of the second gate trenches is greater than or equal to 2 and less than or equal to n+1, where n is an integer greater than or equal to 1. The second gate trench is provided at the end of the region where the first gate trench and the second gate trench are provided in a second direction parallel to the upper surface of the low-concentration impurity layer and orthogonal to the first direction. In the second direction, the region where the first gate trench and the second gate trench are provided is formed by periodically providing the unit structure with the structure in which the most adjacent pair of the second gate trenches sandwiches one of the first gate trenches therebetween as a unit structure, The second gate trench provided at the end of the unit structure is shared by adjacent unit structures. The second gate insulating film has a portion that is thicker than the first gate insulating film.

3. The semiconductor device according to claim 2, wherein: The thickness of the second gate insulating film at a lower portion of the second gate trench is partially thicker than the thickness of the second gate insulating film at an upper portion of the second gate trench.

4. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized in that: It is a vertical field effect transistor with: a semiconductor substrate of the first conductivity type containing the impurities of the first conductivity type; The first conductivity type low concentration impurity layer is formed in contact with the semiconductor substrate and contains the first conductivity type impurities at a concentration lower than the first conductivity type impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer; The source region of the first conductivity type is formed in the body region; A source electrode electrically connected to the body region and the source region; A first gate trench is formed from the upper surface of the low-concentration impurity layer to penetrate the body region to a depth reaching a portion of the low-concentration impurity layer, has a portion in contact with the source region, and extends in a first direction parallel to the upper surface of the low-concentration impurity layer; A second gate trench, which penetrates the body region from the upper surface of the low-concentration impurity layer and is formed deeper than the first gate trench, has a portion in contact with the source region, and extends in the first direction; A first gate insulating film is formed inside the first gate trench; A first gate conductor formed on the first gate insulating film; A second gate insulating film is formed inside the second gate trench; and a second gate conductor formed on the second gate insulating film; The first gate conductor and the second gate conductor have the same potential, When the number of the first gate trenches is n, the number of the second gate trenches is greater than or equal to 2 and less than or equal to n+1, where n is an integer greater than or equal to 1. The second gate trench is provided at the end of the region where the first gate trench and the second gate trench are provided in a second direction parallel to the upper surface of the low-concentration impurity layer and orthogonal to the first direction. In the second direction, the region where the first gate trench and the second gate trench are provided is formed by periodically providing the unit structure with the structure in which the most adjacent pair of the second gate trenches sandwiches one of the first gate trenches therebetween as a unit structure, The second gate trench provided at the end of the unit structure is shared by adjacent unit structures. The low-concentration impurity layer is formed by stacking, from the upper surface side, a first low-concentration impurity layer having a relatively low impurity concentration of the first conductivity type and a second low-concentration impurity layer having a relatively high impurity concentration of the first conductivity type. The bottom end of the first gate trench is located inside the first low-concentration impurity layer. The bottom end of the second gate trench is located inside the second low-concentration impurity layer.

5. The semiconductor device according to any one of claims 2 to 4, wherein: The first gate trenches and the second gate trenches are alternately arranged one by one in the second direction. The interval between the first gate trench and the second gate trench in the second direction is constant.

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