High-speed column-level digital correlated double sampling circuit, analog-to-digital converter and electronic equipment

Abstract

The present invention provides a high-speed column-level digital correlated double sampling circuit, an analog-to-digital converter, and an electronic device, and relates to the field of integrated circuits. Each pixel integration unit corresponds to a pixel one-to-one, and the output end of a column of pixel integration units is electrically connected to a column-level digital correlated double sampling unit. The input end of the double sampling unit is electrically connected to the output end of a column of pixel integration units; the two output ends of the double sampling unit are electrically connected to the input ends of two comparators, respectively. The output ends of each of the two comparators are electrically connected to the input end of a counter; the two output ends of the counter are electrically connected to the input ends of each of the two memories, respectively; the output ends of each of the two memories are electrically connected to the input end of a subtractor; the output end of the subtractor outputs a digital quantity corresponding to the integrated voltage of a column of pixel integration units. The present invention does not need to implement a more complex structure at the pixel level, and is relatively easy to implement in a pixel circuit even if the pixel area becomes smaller and smaller.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a high-speed column-level digital correlated double sampling circuit, an analog-to-digital converter and electronic equipment. Background Art

[0002] At present, infrared thermal imagers are widely used in thermal imaging fields such as medical imaging, surveillance, and night vision. In recent years, readout circuits (ROICs) with on-chip analog-to-digital converters (ADCs) have been widely used due to their better noise performance and reduced system complexity, and they have shorter analog signal paths compared to traditional analog readouts.

[0003] In the current infrared readout circuits, most of them perform correlated double sampling in the pixel circuit to eliminate flicker noise. The method is to sample the reset voltage and the integration voltage separately, and then transmit the voltage signal in the pixel circuit to the column circuit, and then directly convert it into a digital signal through the analog-to-digital converter of the column circuit.

[0004] However, the above structure requires a relatively complex structure to be implemented in the pixel-level circuit, further compressing the area of ​​the integrating capacitor and the source follower tube in the pixel circuit. As the pixel area becomes smaller and smaller, this structure is difficult to implement in the pixel circuit.

[0005] Therefore, there is an urgent need to propose a high-speed column-level digital correlated double sampling circuit suitable for small pixel sizes. Summary of the invention

[0006] In view of the above problems, the present invention is proposed to provide a high-speed column-level digital correlated double sampling circuit, analog-to-digital converter and electronic device that solve the above problems or partially solve the above problems.

[0007] A first aspect of an embodiment of the present invention provides a high-speed column-level digital correlated double sampling circuit, which is applied to a large-scale array readout circuit with a small pixel size. The high-speed column-level digital correlated double sampling circuit includes: a plurality of pixel integration units, a plurality of column-level digital correlated double sampling units;

[0008] Each of the pixel integration units corresponds to a pixel one by one, and the output ends of a column of pixel integration units are electrically connected to a column-level digital correlated double sampling unit;

[0009] The column-level digital correlated double sampling unit comprises: a double sampling unit, two comparators, a counter, two memories and a subtractor;

[0010] The input end of the dual sampling unit is electrically connected to the output end of the one column pixel integration unit;

[0011] The two output terminals of the dual sampling unit are electrically connected to the input terminals of the two comparators respectively;

[0012] The output terminals of the two comparators are electrically connected to the input terminals of the counter;

[0013] The two output terminals of the counter are electrically connected to the input terminals of the two memories respectively;

[0014] The output terminals of the two memories are electrically connected to the input terminals of the subtractor;

[0015] The output end of the subtractor outputs a digital value corresponding to the integrated voltage of the column of pixel integration units.

[0016] Optionally, the dual sampling unit includes: a signal voltage sampling unit and a reset voltage sampling unit;

[0017] The input ends of the signal voltage sampling unit and the reset voltage sampling unit are electrically connected to the output ends of the pixel integration unit of one column;

[0018] The output end of the signal voltage sampling unit is electrically connected to the input end of the first comparator of the two comparators;

[0019] The output end of the reset voltage sampling unit is electrically connected to the input end of the second comparator of the two comparators;

[0020] The signal voltage sampling unit is configured to sample an integrated voltage obtained by integrating the photocurrent detected by each pixel in the column of pixel integration units to obtain a signal voltage, and transmit the signal voltage to the first comparator;

[0021] The reset voltage sampling unit is configured to sample the voltage of each pixel in the column of pixel integration units when the integration is reset, obtain the reset voltage, and transmit it to the second comparator.

[0022] Optionally, the first comparator includes two input terminals: a first non-inverting terminal and a first inverting terminal; the second comparator includes two input terminals: a second non-inverting terminal and a second inverting terminal;

[0023] The first in-phase terminal receives the signal voltage, the first inverting terminal receives a single slope voltage, and the output terminal of the first comparator is electrically connected to the input terminal of the counter;

[0024] The second non-inverting terminal receives the reset voltage, the second inverting terminal receives the single slope voltage, and the output terminal of the second comparator is electrically connected to the input terminal of the counter;

[0025] The first comparator is configured to compare the signal voltage with the single slope voltage to obtain a first comparison result;

[0026] The second comparator is configured to compare the reset voltage with the single slope voltage to obtain a second comparison result.

[0027] Optionally, the counter is configured to count the first comparison result, obtain a first counting code value and transmit it to a first memory of the two memories;

[0028] The counter is further configured to count the second comparison result to obtain a second counting code value and transmit the second counting code value to the second memory of the two memories.

[0029] Optionally, the first memory is configured to store the first counting code value and transmit it to the subtractor;

[0030] The second memory is configured to store the second counting code value and transmit the second counting code value to the subtractor.

[0031] Optionally, the subtractor is configured to perform a subtraction operation on the first counting code value and the second counting code value to obtain the digital value and output it outside the chip.

[0032] Optionally, in the first half of the sampling period, the signal voltage sampling unit samples the integrated voltage to obtain a signal voltage, and transmits the signal voltage to the first comparator;

[0033] In the second half of the sampling period, the reset voltage sampling unit samples the voltage of each pixel in the column of pixel integration units when the integration is reset, obtains the reset voltage, and transmits it to the second comparator.

[0034] Optionally, during the period from the beginning to the end of the first half cycle, the counter counts the first comparison result output by the first comparator of the two comparators to obtain a first counting code value and transmits it to the first memory of the two memories;

[0035] During the period from the beginning to the end of the second half cycle, the counter counts the second comparison result output by the second comparator of the two comparators to obtain a second counting code value and transmits it to the second memory of the two memories.

[0036] A second aspect of an embodiment of the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising a high-speed column-level digital correlated double sampling circuit as described in any one of the first aspects.

[0037] A third aspect of an embodiment of the present invention provides an electronic device, comprising: the analog-to-digital converter as described in the second aspect.

[0038] The high-speed column-level digital correlated double sampling circuit provided by the present invention is applied to a large-scale array readout circuit with a small pixel size, and comprises: a plurality of pixel integration units and a plurality of column-level digital correlated double sampling units. Each pixel integration unit corresponds to a pixel one-to-one, and the output end of a column of pixel integration units is electrically connected to a column-level digital correlated double sampling unit.

[0039] The column-level digital correlated double sampling unit includes: a double sampling unit, two comparators, a counter, two memories and a subtractor; the input end of the double sampling unit is electrically connected to the output end of a column of pixel integration units; the two output ends of the double sampling unit are electrically connected to the input ends of the two comparators respectively.

[0040] The output ends of the two comparators are electrically connected to the input end of the counter; the two output ends of the counter are electrically connected to the input ends of the two memories respectively; the output ends of the two memories are electrically connected to the input end of the subtractor; the output end of the subtractor outputs a digital quantity corresponding to the integrated voltage of a column of pixel integration units.

[0041] The high-speed column-level digital correlated double sampling circuit of the present invention, based on the traditional column-level digital correlated double sampling circuit, creatively proposes a structure of configuring two groups of parallel sampling and synchronous quantization at the column level, using double sampling units to sample respectively to obtain signal voltage and reset voltage, two comparators to compare and process the signal voltage and reset voltage respectively, a counter counts the comparison results of the two comparators, obtains respective counting results and stores them respectively by two memories. Finally, a subtractor subtracts the two counting results to obtain a quantized digital quantity. Since only the integral voltage needs to be obtained in the pixel-level circuit, and there is no need to sample the integral voltage and reset voltage, there is no need to implement a more complex structure, and naturally there is no need to compress the area of ​​the integral capacitor and the source follower tube in the pixel circuit. Even if the pixel area is getting smaller and smaller, it is easier to implement in the pixel circuit, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0043] Figure 1 It is a schematic diagram of the architecture of a traditional column-level digital correlated double sampling circuit;

[0044] Figure 2is a schematic structural diagram of an exemplary high-speed column-level digital correlated double sampling circuit in an embodiment of the present invention;

[0045] Figure 3 1 is a timing diagram of the sampling signal RS<1>, the reset signal RS_d<1> and quantization in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The inventors found that most of the current infrared readout circuits perform correlated double sampling in the pixel circuit to eliminate flicker noise. The method is to sample the reset voltage and the integration voltage separately, and then transmit the voltage signal in the pixel circuit to the column circuit, and then directly convert it into a digital signal through the analog-to-digital converter of the column circuit. However, this structure requires a more complex structure to be implemented in the pixel circuit, further compressing the area of ​​the integration capacitor and source follower tube in the pixel circuit. As the pixel area becomes smaller and smaller, this structure is difficult to implement in the pixel circuit.

[0048] Reference Figure 1 The schematic diagram of the architecture of the traditional column-level digital correlated double sampling circuit is shown. Figure 1 For simplicity of illustration, only a structure corresponding to a pixel circuit and a column-level circuit structure are shown, which includes: a photodetector for detecting the pixel to obtain a photocurrent I DET , and is integrated by the integration unit during the integration period to obtain the integrated voltage V INT At the same time, a reset operation is required during integration. During the reset operation, the reset switch is controlled by the reset signal RST to close, and the reset voltage V RST The reset voltage V is transmitted to the capacitor through the reset switch. INT_D .

[0049] Depend on Figure 1 It can be seen that the sampling unit needs to reset the voltage V INT_D and the integrated voltage V INT Sampling is performed separately and subtracted to obtain the sampled voltage V SH , and then the comparator compares it with the single ramp voltage V RAMP The comparison result CMP is obtained OUT The counter is the comparison result CMP OUT Count and transfer the counting result to the memory for storage, and finally the memory outputs the quantized digital value DOUT To outside the film.

[0050] The above structure needs to realize a more complex structure in the pixel level circuit, further compressing the capacitor and source follower tube in the pixel circuit ( Figure 1 As the pixel area becomes smaller and smaller, this structure is difficult to implement in the pixel circuit.

[0051] In view of the above problems, the inventors have creatively proposed a high-speed column-level digital correlated double sampling circuit, analog-to-digital converter and electronic device of the present invention after in-depth research. The technical solution of the present invention is explained and illustrated in detail below.

[0052] The high-speed column-level digital correlated double sampling circuit of the present invention is particularly suitable for large-scale array readout circuits with small pixel sizes. The high-speed column-level digital correlated double sampling circuit comprises: multiple pixel integration units and multiple column-level digital correlated double sampling units.

[0053] Each pixel integration unit corresponds to a pixel one-to-one, and the pixel in the pixel integration unit detects the photocurrent of the pixel and integrates it to obtain the integrated voltage corresponding to the pixel. The output end of a column of pixel integration units is electrically connected to a column-level digital correlated double sampling unit, so the integrated voltage corresponding to a column of pixels will be sampled by the column-level digital correlated double sampling unit.

[0054] The column-level digital correlated double sampling unit includes: a double sampling unit, two comparators, a counter, two memories and a subtractor. The input end of the double sampling unit is electrically connected to the output end of a column of pixel integration units; the two output ends of the double sampling unit are electrically connected to the input ends of the two comparators respectively.

[0055] The output ends of the two comparators are electrically connected to the input end of the counter; the two output ends of the counter are electrically connected to the input ends of the two memories respectively; the output ends of the two memories are electrically connected to the input end of the subtractor; the output end of the subtractor outputs a digital quantity corresponding to the integrated voltage of a column of pixel integration units.

[0056] Specifically: the dual sampling unit includes: a signal voltage sampling unit and a reset voltage sampling unit. The input ends of the signal voltage sampling unit and the reset voltage sampling unit are electrically connected to the output end of a column of pixel integration units. The output end of the signal voltage sampling unit is electrically connected to the input end of the first comparator of the two comparators. The output end of the reset voltage sampling unit is electrically connected to the input end of the second comparator of the two comparators.

[0057] Among them, the signal voltage sampling unit is configured to sample the integrated voltage obtained by integrating the photocurrent detected by each pixel in a column of pixel integration units, obtain the signal voltage, and transmit it to the first comparator; the reset voltage sampling unit is configured to sample the voltage when each pixel in a column of pixel integration units is integrated and reset, obtain the reset voltage, and transmit it to the second comparator.

[0058] For the two comparators, the first comparator includes two input terminals: a first non-inverting terminal and a first inverting terminal; the second comparator includes two input terminals: a second non-inverting terminal and a second inverting terminal.

[0059] The first non-inverting terminal receives a signal voltage, the first inverting terminal receives a single slope voltage, and the output terminal of the first comparator is electrically connected to the input terminal of the counter; the second non-inverting terminal receives a reset voltage, the second inverting terminal also receives a single slope voltage, and the output terminal of the second comparator is also electrically connected to the input terminal of the counter.

[0060] The first comparator is configured to compare the signal voltage with the single slope voltage to obtain a first comparison result; the second comparator is configured to compare the reset voltage with the single slope voltage to obtain a second comparison result.

[0061] The counter is configured to count the first comparison result, obtain a first counting code value and transmit it to the first memory of the two memories; the counter is also configured to count the second comparison result, obtain a second counting code value and transmit it to the second memory of the two memories.

[0062] It should be noted that if power consumption and area overhead are not considered, there can also be two counters, one counter only counts the first comparison result, obtains the first counting code value and transmits it to the first memory, and the other counter only counts the second comparison result, obtains the second counting code value and transmits it to the first memory.

[0063] The first memory is configured to store the first counting code value and transmit it to the subtractor; the second memory is configured to store the second counting code value and transmit it to the subtractor. The subtractor is configured to perform a subtraction operation on the first counting code value and the second counting code value, and finally obtain a digital value corresponding to the integrated voltage obtained by integrating a column of pixel integration units and output it to the outside of the chip.

[0064] The traditional column-level digital correlated double sampling circuit, because it realizes the digital-level analog-to-digital converter at the column level, needs to transmit both the signal voltage and the reset voltage to the column level and then perform quantization. This results in that if two complete quantization processes are directly performed at the column level, the quantization time will be too long, and a lot of time will be wasted. The structure of the high-speed column-level digital correlated double sampling circuit based on the present invention is equivalent to configuring two sets of parallel sampling and synchronous quantization structures at the column level, using parallel processing to obtain two digital quantization results, and then subtracting the two results, and finally completing the digital correlated double sampling in the same time. That is, compared with the traditional column-level digital correlated double sampling circuit, the high-speed column-level digital correlated double sampling circuit of the present invention completes sampling and quantization in the same time, but no longer requires a complex correlated double sampling structure in the pixel circuit, and there is no need to compress the area of ​​the integral capacitor and the source follower tube in the pixel circuit.

[0065] In the first half of the sampling period, the signal voltage sampling unit samples the integrated voltage to obtain the signal voltage, and transmits it to the first comparator; in the second half of the sampling period, the reset voltage sampling unit samples the voltage at the time of integral reset to obtain the reset voltage, and transmits it to the second comparator.

[0066] It can be understood that during the period from the beginning to the end of the first half cycle, the counter counts the first comparison result output by the first comparator of the two comparators, obtains the first counting code value and transmits it to the first memory of the two memories; during the period from the beginning to the end of the second half cycle, the counter counts the second comparison result output by the second comparator of the two comparators, obtains the second counting code value and transmits it to the second memory of the two memories. Since the counting is performed at different time periods, only one counter is needed to count two different comparison results, so there is no need to set two counters to count separately.

[0067] In order to better understand the structure of the high-speed column-level digital correlated double sampling circuit, refer to Figure 2 A schematic diagram of an exemplary high-speed column-level digital correlated double sampling circuit is shown in FIG. Figure 2 For the sake of simplicity, only the structure corresponding to one pixel circuit and one column-level circuit structure are shown. For more pixel circuits and more column-level circuits, refer to Figure 2 The structure shown can be obtained through simple reasoning and will not be elaborated on here.

[0068] Figure 2 Combination Figure 1 It can be seen that in the pixel, the pixel circuit no longer samples the integral voltage and the reset voltage separately. Instead, the photodetector detects the pixel to obtain the photocurrent I DET , and is integrated by the integration unit during the integration period to obtain the integrated voltage VINT , and when the integral is reset, the reset signal RS_d<1> is used to control the switch to close, and the reset voltage V RST Just reset it.

[0069] The signal voltage sampling unit integrates the photocurrent detected by each pixel in a column of pixel integration units to obtain an integrated voltage V INT Sampling is performed to obtain the signal voltage V SH1 , and transmitted to the first comparator; the reset voltage sampling unit is the voltage V when each pixel in a column of pixel integration units is integrated and reset RST Sampling is performed to obtain the reset voltage V SH2 , and transmitted to the second comparator.

[0070] The first non-inverting terminal of the first comparator receives the signal voltage V SH1 , the first inverting terminal receives a single ramp voltage V RAMP The second in-phase terminal of the second comparator receives the reset voltage V SH2 The second inverting terminal also receives a single ramp voltage V RAMP .

[0071] The first comparator is used to detect the signal voltage V SH1 and a single ramp voltage V RAMP Compare and get the first comparison result CMP OUT1 ; The second comparator resets the voltage V SH2 and a single ramp voltage V RAMP Compare and obtain the second comparison result CMP OUT2 The two comparison results CMP OUT1 、CMP OUT2 All are counted by the counter.

[0072] The counter compares the first result CMP OUT1 Counting is performed to obtain a first counting code value and transmit it to the first memory; the counter performs a second comparison on the second comparison result CMP OUT2 Counting is performed to obtain a second counting code value and transmit it to the second memory.

[0073] The first memory stores the first counting code value and transmits it to the subtractor; the second memory stores the second counting code value and transmits it to the subtractor. The subtractor performs a subtraction operation on the first counting code value and the second counting code value, that is, subtracts the second counting code value from the first counting code value, and finally obtains a digital value D corresponding to the integrated voltage obtained by integrating a column of pixel integration units. OUT And output outside the chip.

[0074] The corresponding sampling signal RS<1> and reset signal RS_d<1> and the quantization timing diagram refer to Figure 3As shown. The first half of the sampling period is for signal voltage transmission (that is, the signal voltage sampling unit obtains the signal voltage), and the second half of the sampling period is for reset voltage transmission (that is, the reset voltage sampling unit obtains the reset voltage, and the reset signal RS_d<1> needs to be high level during this half period). At the same time, the corresponding quantization is also completed within this period, realizing parallel sampling and synchronous quantization.

[0075] Through the above structure, the entire high-speed column-level digital correlated double sampling circuit configures two sets of parallel sampling and synchronous quantization structures at the column level, samples the signal voltage and reset voltage respectively, and the comparator compares and processes the signal voltage and reset voltage respectively, and then the counter counts the comparison results of the two comparators to obtain the respective counting results and stores them respectively by the memory. Finally, the subtractor subtracts the two counting results to obtain the quantized digital quantity, realizing parallel sampling and synchronous quantization. Since only the integral voltage needs to be obtained in the pixel-level circuit, and there is no need to sample the integral voltage and reset voltage, there is no need to implement a more complex structure, and naturally there is no need to compress the area of ​​the integral capacitor and the source follower tube in the pixel circuit. Even if the pixel area is getting smaller and smaller, it is easier to implement in the pixel circuit.

[0076] Based on the above high-speed column-level digital correlated double sampling circuit, an embodiment of the present invention further provides an analog-to-digital converter, which includes any of the above high-speed column-level digital correlated double sampling circuits.

[0077] Based on the above high-speed column-level digital correlated double sampling circuit, an embodiment of the present invention further provides an electronic device, which includes: the above analog-to-digital converter.

[0078] Through the above embodiments, the high-speed column-level digital correlated double sampling circuit provided by the present invention is applied to a large-scale array readout circuit, and includes: a plurality of pixel integration units and a plurality of column-level digital correlated double sampling units. Each pixel integration unit corresponds to a pixel one-to-one, and the output end of a column of pixel integration units is electrically connected to a column-level digital correlated double sampling unit.

[0079] The column-level digital correlated double sampling unit includes: a double sampling unit, two comparators, a counter, two memories and a subtractor; the input end of the double sampling unit is electrically connected to the output end of a column of pixel integration units; the two output ends of the double sampling unit are electrically connected to the input ends of the two comparators respectively.

[0080] The output ends of the two comparators are electrically connected to the input end of the counter; the two output ends of the counter are electrically connected to the input ends of the two memories respectively; the output ends of the two memories are electrically connected to the input end of the subtractor; the output end of the subtractor outputs a digital quantity corresponding to the integrated voltage of a column of pixel integration units.

[0081] The high-speed column-level digital correlated double sampling circuit of the present invention, based on the traditional column-level digital correlated double sampling circuit, creatively proposes a structure of configuring two groups of parallel sampling and synchronous quantization at the column level, using double sampling units to sample respectively to obtain signal voltage and reset voltage, two comparators to compare and process the signal voltage and reset voltage respectively, a counter counts the comparison results of the two comparators, obtains respective counting results and stores them respectively by two memories. Finally, a subtractor subtracts the two counting results to obtain a quantized digital quantity. Since only the integral voltage needs to be obtained in the pixel-level circuit, and there is no need to sample the integral voltage and reset voltage, there is no need to implement a more complex structure, and naturally there is no need to compress the area of ​​the integral capacitor and the source follower tube in the pixel circuit. Even if the pixel area is getting smaller and smaller, it is easier to implement in the pixel circuit, and has high practicality.

[0082] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0083] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A high-speed column-level digital correlated double sampling circuit, characterized in that: The high-speed column-level digital correlated double sampling circuit is applied to a large-scale array readout circuit with a small pixel size. The high-speed column-level digital correlated double sampling circuit comprises: a plurality of pixel integration units, a plurality of column-level digital correlated double sampling units; Each of the pixel integration units corresponds to a pixel one by one, and the output ends of a column of pixel integration units are electrically connected to a column-level digital correlated double sampling unit; The column-level digital correlated double sampling unit comprises: a double sampling unit, two comparators, a counter, two memories and a subtractor; The input end of the dual sampling unit is electrically connected to the output end of the one column pixel integration unit; The two output terminals of the dual sampling unit are electrically connected to the input terminals of the two comparators respectively; The output terminals of the two comparators are electrically connected to the input terminals of the counter; The two output terminals of the counter are electrically connected to the input terminals of the two memories respectively; The output terminals of the two memories are electrically connected to the input terminals of the subtractor; The output end of the subtractor outputs a digital value corresponding to the integrated voltage of the pixel integration unit of the column; Wherein, the dual sampling unit includes: a signal voltage sampling unit and a reset voltage sampling unit; The input ends of the signal voltage sampling unit and the reset voltage sampling unit are electrically connected to the output ends of the pixel integration unit of one column; The output end of the signal voltage sampling unit is electrically connected to the input end of the first comparator of the two comparators; The output end of the reset voltage sampling unit is electrically connected to the input end of the second comparator of the two comparators; The signal voltage sampling unit is configured to sample the integrated voltage obtained by integrating the photocurrent detected by each pixel in the column of pixel integration units to obtain a signal voltage, and transmit it to the first comparator; The reset voltage sampling unit is configured to sample the voltage of each pixel in the column of pixel integration units when the integration is reset, obtain the reset voltage, and transmit it to the second comparator.

2. The high-speed column-level digital correlated double sampling circuit according to claim 1, characterized in that: The first comparator includes two input terminals: a first non-inverting terminal and a first inverting terminal; the second comparator includes two input terminals: a second non-inverting terminal and a second inverting terminal; The first in-phase terminal receives the signal voltage, the first inverting terminal receives a single slope voltage, and the output terminal of the first comparator is electrically connected to the input terminal of the counter; The second non-inverting terminal receives the reset voltage, the second inverting terminal receives the single slope voltage, and the output terminal of the second comparator is electrically connected to the input terminal of the counter; The first comparator is configured to compare the signal voltage with the single slope voltage to obtain a first comparison result; The second comparator is configured to compare the reset voltage with the single slope voltage to obtain a second comparison result.

3. The high-speed column-level digital correlated double sampling circuit according to claim 2, characterized in that: The counter is configured to count the first comparison result, obtain a first counting code value and transmit it to a first memory of the two memories; The counter is further configured to count the second comparison result to obtain a second counting code value and transmit the second counting code value to the second memory of the two memories.

4. The high-speed column-level digital correlated double sampling circuit according to claim 3, characterized in that: The first memory is configured to store the first counting code value and transmit it to the subtractor; The second memory is configured to store the second counting code value and transmit the second counting code value to the subtractor.

5. The high-speed column-level digital correlated double sampling circuit according to claim 4, characterized in that: The subtractor is configured to perform a subtraction operation on the first counting code value and the second counting code value to obtain the digital value and output it outside the chip.

6. The high-speed column-level digital correlated double sampling circuit according to claim 1, characterized in that: In the first half of the sampling period, the signal voltage sampling unit samples the integrated voltage to obtain a signal voltage, and transmits the signal voltage to the first comparator; In the second half of the sampling period, the reset voltage sampling unit samples the voltage of each pixel in the column of pixel integration units when the integration is reset, obtains the reset voltage, and transmits it to the second comparator.

7. The high-speed column-level digital correlated double sampling circuit according to claim 6, characterized in that: During the period from the beginning to the end of the first half cycle, the counter counts the first comparison result output by the first comparator of the two comparators to obtain a first counting code value and transmits it to the first memory of the two memories; During the period from the beginning to the end of the second half cycle, the counter counts the second comparison result output by the second comparator of the two comparators to obtain a second counting code value and transmits it to the second memory of the two memories.

8. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a high-speed column-level digital correlated double sampling circuit as described in any one of claims 1-7.

9. An electronic device, characterized in that: The electronic device comprises: the analog-to-digital converter as claimed in claim 8.

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