Semiconductor device manufacturing method and semiconductor device

Abstract

The embodiment of the present application relates to a method for preparing a semiconductor device and a semiconductor device, comprising: providing a first substrate, the first substrate comprising a first surface and a second surface opposite to each other, the first substrate comprising a first semiconductor material layer, a sacrificial layer, and a second semiconductor material layer stacked in sequence from the first surface to the second surface; forming a groove on the second surface side, the groove extending from the second surface to the first surface and penetrating the sacrificial layer; filling the groove with material to form a support structure; forming a front device structure on the second surface side, the front device structure comprising a transistor; forming a release hole on the first surface side, the release hole extending from the first surface to the second surface until the sacrificial layer is exposed; removing at least part of the sacrificial layer through the release hole to form a cavity at the position of the removed sacrificial layer, the cavity being used to form isolation between the transistor and the first semiconductor material layer. Thus, it is beneficial to avoid device collapse, reduce process difficulty, and ensure device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] In recent years, with the advancement of semiconductor technology, SOI (Silicon-On-Insulator)-based devices have been widely used in RF switches and low-noise amplifiers due to their good RF performance such as better isolation, lower substrate coupling, high speed, and low power consumption.

[0003] However, in devices manufactured using SOI transistors, parasitic coupling will still occur between the source, drain, etc. of the transistor and the SOI substrate, generating parasitic capacitance, and this parasitic capacitance will change with the device voltage, thereby further affecting the overall performance of the transistor and ultimately the performance of the entire device.

[0004] At present, the industry forms a cavity between the semiconductor material layers of the SOI substrate so that the source and drain of the SOI transistor are suspended on the cavity to eliminate the parasitic capacitance between the source and drain and the SOI substrate. However, there are still many problems to be overcome in the process, and the reliability and yield of the product still need to be improved. Summary of the invention

[0005] In view of this, embodiments of the present application provide a method for manufacturing a semiconductor device and a semiconductor device to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor device, comprising:

[0007] Providing a first substrate, the first substrate comprising a first surface and a second surface opposite to each other, the first substrate comprising a first semiconductor material layer, a sacrificial layer, and a second semiconductor material layer sequentially stacked from the first surface to the second surface;

[0008] forming a groove on the second surface side, wherein the groove extends from the second surface to the first surface and penetrates the sacrificial layer;

[0009] filling the groove with material to form a support structure;

[0010] forming a front-side device structure on the second surface side, the front-side device structure comprising a transistor;

[0011] forming a release hole on the first surface side, wherein the release hole extends from the first surface to the second surface until the sacrificial layer is exposed;

[0012] At least a portion of the sacrificial layer is removed through the release hole to form a cavity at a location of the removed sacrificial layer, wherein the cavity is used to form isolation between the transistor and the first semiconductor material layer.

[0013] In conjunction with the first aspect of the present application, in an optional implementation manner, the process of removing at least part of the sacrificial layer includes a wet etching process;

[0014] Before forming the groove on the second surface side, the method also includes: performing an ion implantation process on the sacrificial layer, wherein the etching rate of the sacrificial layer after the ion implantation process in the wet etching process is greater than the etching rate of the sacrificial layer without the ion implantation process in the wet etching process.

[0015] In combination with the first aspect of the present application, in an optional implementation manner, the groove divides a cavity preset formation area in the sacrificial layer;

[0016] The removing at least a portion of the sacrificial layer comprises: removing at least the sacrificial layer located in the preset cavity formation area to form a cavity at the location of the preset cavity formation area; and the sidewall of the cavity is formed by the supporting structure.

[0017] In conjunction with the first aspect of the present application, in an optional implementation manner, forming a front device structure on the second surface side includes:

[0018] forming a gate structure on the second surface;

[0019] A doping process is performed with a portion of the second semiconductor material layer corresponding to the preset cavity formation area as the active area to form a source area in one side of the gate structure and a drain area in the other side of the active area.

[0020] In combination with the first aspect of the present application, in an optional embodiment, after forming the front device structure on the second surface side and before forming the release hole on the first surface side, the method further includes: bonding the second substrate on the side of the front device structure away from the first substrate; and thinning the first semiconductor material layer on the first surface side.

[0021] In combination with the first aspect of the present application, in an optional implementation, the material of the support structure includes AlN and / or Al2O3.

[0022] In a second aspect, an embodiment of the present application provides a semiconductor device, including:

[0023] A first substrate, comprising a first surface and a second surface opposite to each other, and in a direction from the first surface to the second surface, the first substrate comprises a first semiconductor material layer and a second semiconductor material layer arranged at intervals;

[0024] A front device structure, located on the second surface side, the front device structure comprising a transistor;

[0025] a cavity, located between the first semiconductor material layer and the second semiconductor material layer, for forming isolation between the transistor and the first semiconductor material layer;

[0026] A support structure extending from the second surface through the cavity to support the first semiconductor material layer and the second semiconductor material layer that are spaced apart;

[0027] A release hole extends from the first surface until it is communicated with the cavity.

[0028] In combination with the second aspect of the present application, in an optional implementation, the side wall of the cavity is formed by the supporting structure.

[0029] In conjunction with the second aspect of the present application, in an optional implementation manner, the front device structure includes:

[0030] An active region is a portion of the second semiconductor material layer corresponding to the cavity;

[0031] A gate structure, located on the active area;

[0032] a source region located in the active region on one side of the gate structure;

[0033] A drain region is located in the active region on the other side of the gate structure.

[0034] In conjunction with the second aspect of the present application, in an optional implementation, the material of the support structure includes AlN and / or Al2O3.

[0035] On the one hand, the method for preparing a semiconductor device provided in an embodiment of the present application forms isolation between the transistor and the first semiconductor material layer through a cavity, which is beneficial to eliminating the parasitic capacitance between the source, drain, etc. of the transistor and the first semiconductor material layer; by pre-forming a support structure before forming the cavity, the support structure can prevent the structure above the sacrificial layer from collapsing during the process of removing the sacrificial layer to form the cavity; by filling a material in a groove to form a support structure, the position and shape of the support structure can be preset by the groove, thereby reducing the process difficulty and facilitating improving production efficiency; after forming the front device structure on the second surface side, a release hole is formed from the first surface side, so that the front device structure and the release hole are located on different sides of the first substrate, thereby avoiding the step of forming the release hole from damaging the structure on the second surface side, thereby ensuring the performance of the device; and the process of removing the sacrificial layer is performed on the first surface of the first substrate, that is, on the back side of the first substrate, thereby avoiding the process from affecting the front device structure. On the other hand, the semiconductor device provided in the embodiment of the present application forms isolation between the transistor and the first semiconductor material layer through the cavity, which is beneficial to eliminating the parasitic capacitance between the source, drain, etc. of the transistor and the first semiconductor material layer; the first semiconductor material layer and the second semiconductor material layer can be spaced apart through the supporting structure, and provide better support for the structure above the cavity; the release hole and the front device structure are located on different sides of the first substrate, which can avoid damage to the front device structure caused by the formation of the release hole, and is beneficial to ensuring the performance of the device.

[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0038] Figures 1 to 3 It is a schematic diagram of the cross-sectional structure of a semiconductor device during the preparation process in the related art;

[0039] Figure 4 A schematic diagram of a process for preparing a semiconductor device according to an embodiment of the present application;

[0040] Figures 5 to 18 A schematic diagram of the cross-sectional structure of a semiconductor device during the preparation process provided by an embodiment of the present application;

[0041] Fig.19 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present application;

[0042] Fig. 20 For Figure 6 A top view corresponding to the structure shown;

[0043] Fig.21 For Figure 7 A top view corresponding to the structure shown;

[0044] Fig. 22 For Fig.19 The structure shown corresponds to a top perspective view. DETAILED DESCRIPTION

[0045] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0046] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0047] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0049] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0050] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0052] Please refer to Figures 1 to 3 In the related art, the manufacturing process of the semiconductor device is generally as follows: forming a plurality of release holes 170 extending from the second surface 102 to expose the sacrificial layer 120 on the first substrate 100; removing part of the sacrificial layer 120 by selective etching to form a cavity region 121s in the sacrificial layer 120; filling the release holes 170 with a material to form an isolation plug 171 to isolate the cavity region 121s into a plurality of cavities 121. It can be understood that Figure 1 Specifically, the release holes 170 extend from the second surface 102 through the sacrificial layer 120 until the first semiconductor material layer 110 is exposed. When removing part of the sacrificial layer 120 , the part of the sacrificial layer 120 between different release holes 170 may be removed.

[0053] In this preparation process, please refer to Figure 2 During the etching process of the sacrificial layer 120, most of the second semiconductor material layer 130 is in a suspended state (e.g. Figure 2 The second semiconductor material layer 130 is only supported by the unremoved portion of the sacrificial layer (such as Figure 2 The support force is weak and prone to collapse; and the cavity region 121s is formed by selective etching, which requires strict control of process parameters, otherwise the sacrificial layer 120 may be over-etched or even completely removed, causing the structure above the cavity region 121s to lose support and collapse. At the same time, in the related art, the second surface 102 side is used as the front side of the first substrate 100, and the front device structure will be prepared on the second surface 102 side later. It can be understood that in the actual production process, before the process step of forming the release hole 170 is performed, a part of the front device structure has been formed on the second surface 102 side. At this time, the process of forming the release hole 170 extending from the second surface 102 is very likely to cause damage to the front device structure also located on the second surface side, thereby affecting the performance of the device.

[0054] Please refer to Figure 3The isolation plug 171 is formed through the release hole 170 after the cavity area 121s is formed. During this process, the shape of the isolation plug 171 located in the cavity area 121s is difficult to control, which can easily cause material waste, affect production efficiency, and even affect device performance; and the isolation plug 171 is mainly used to isolate an entire cavity area 121s into multiple cavities 121. On the basis of the difficulty in controlling the shape, its supporting effect is also difficult to guarantee. When the front device structure continues to be formed on the second semiconductor material layer 130, collapse is very likely to occur.

[0055] Based on this, the present application embodiment provides a method for preparing a semiconductor device, please refer to Figure 4 , the preparation method comprises:

[0056] S401: providing a first substrate, the first substrate comprising a first surface and a second surface opposite to each other, the first substrate comprising a first semiconductor material layer, a sacrificial layer, and a second semiconductor material layer sequentially stacked from the first surface to the second surface;

[0057] S402: forming a groove on the second surface side, the groove extending from the second surface to the first surface and penetrating the sacrificial layer;

[0058] S403: Filling the groove with material to form a support structure;

[0059] S404: forming a front device structure on the second surface side, the front device structure including a transistor;

[0060] S405: forming a release hole on the first surface side, the release hole extending from the first surface to the second surface until the sacrificial layer is exposed;

[0061] S406: removing at least a portion of the sacrificial layer through the release hole to form a cavity at the location of the removed sacrificial layer, wherein the cavity is used to form isolation between the transistor and the first semiconductor material layer.

[0062] In the embodiment of the present application, a cavity is used to form an isolation between the transistor and the first semiconductor material layer, which is beneficial to eliminating the parasitic capacitance between the source, drain, etc. of the transistor and the first semiconductor material layer; a support structure is pre-formed before the cavity is formed, so that in the process of removing the sacrificial layer to form the cavity, the support structure can prevent the structure above the sacrificial layer from collapsing; a support structure is formed by filling a material in a groove, so that the position and shape of the support structure can be preset by the groove, thereby reducing the process difficulty and facilitating improving production efficiency; after the front device structure is formed on the second surface side, a release hole is formed from the first surface side, so that the front device structure and the release hole are not on the same side, thereby avoiding the step of forming the release hole causing damage to the structure on the second surface side, thereby ensuring the performance of the device; and the process of removing the sacrificial layer is performed on the first surface of the first substrate, that is, on the back side of the first substrate, thereby avoiding the process from affecting the front device structure.

[0063] Please refer to Figure 5 , perform step S401: provide a first substrate 100, the first substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, and the first substrate 100 includes a first semiconductor material layer 110, a sacrificial layer 120, and a second semiconductor material layer 130 stacked in sequence from the first surface 101 to the second surface 102.

[0064] It can be understood that the materials of the first semiconductor material layer 110 and the second semiconductor material layer 130 can be any suitable semiconductor material well known to those skilled in the art. In this embodiment, the first substrate 100 is specifically, for example, an SOI substrate. The SOI substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked in sequence. The first semiconductor material layer 110 of the first substrate 100 can be regarded as the bottom silicon layer of the SOI substrate, the sacrificial layer 120 of the first substrate 100 can be regarded as the buried oxide layer of the SOI substrate, and the second semiconductor material layer 130 of the first substrate 100 can be regarded as the top silicon layer of the SOI substrate. Of course, this embodiment does not exclude that the SOI substrate also includes other material layers located between the bottom silicon layer and the top silicon layer, except for the buried oxide layer, such as a trap-rich layer located between the bottom silicon layer and the buried oxide layer, and thus, the sacrificial layer 120 of the first substrate 100 can be regarded as a buried oxide layer and / or a trap-rich layer of the SOI substrate. In the following, the sacrificial layer 120 of the first substrate 100 is taken as an example of a buried oxide layer of the SOI substrate for specific description.

[0065] Optionally, the process of removing at least part of the sacrificial layer 120 includes a wet etching process; before forming the groove on the second surface 102 side, the preparation method further includes: performing an ion implantation process on the sacrificial layer 120, and the etching rate of the sacrificial layer 120 after the ion implantation process in the wet etching process is greater than the etching rate of the sacrificial layer 120 without the ion implantation process in the wet etching process. It can be understood that in the subsequent steps, a wet etching process can be used to remove at least part of the sacrificial layer 120 to form a cavity, and the lattice structure of the sacrificial layer 120 can be destroyed by the ion implantation process, and the etching rate of the wet etching solution on the sacrificial layer 120 after the ion implantation process is accelerated, which is conducive to improving production efficiency.

[0066] Optionally, the ions implanted into the sacrificial layer 120 include phosphorus ions. Of course, the present application does not exclude that the ions implanted into the sacrificial layer 120 are other ions known to those skilled in the art that can destroy the lattice structure, and this embodiment does not limit this.

[0067] In this embodiment, the etching solution of the wet etching process may include a BOE (Buffered Oxide Etch) solution.

[0068] Please refer to Figure 6 , step S402 is performed: a groove 150 is formed on the second surface 102 side, and the groove 150 extends from the second surface 102 to the first surface 101 and penetrates the sacrificial layer 120. Thus, the position and shape of the support structure formed in the subsequent steps are defined by the groove 150, the process is simple, and it is conducive to improving production efficiency.

[0069] In this embodiment, the process of forming the groove 150 may include a photolithography process and an etching process.

[0070] Please refer to Figure 6 and Figure 7 , perform step S403: fill the groove 150 with material to form a support structure 160. Thus, the support structure 160 is formed in advance, and in the subsequent process of forming the cavity, the support structure 160 can provide a good support force to prevent the structure above the sacrificial layer 120 from collapsing; by filling the groove 150 with material to form the support structure 160, the groove 150 defines the formation position and shape of the support structure 160, so that the formation process of the support structure 160 is simple, which is conducive to improving production efficiency.

[0071] Optionally, the material of the support structure 160 includes AlN and / or Al2O3. Both AlN and Al2O3 have good corrosion resistance. When removing the sacrificial layer 120, AlN and Al2O3 are not easily affected by the process to ensure the structural strength of the support structure 160. In addition, AlN and Al2O3 have good mechanical properties and can provide good support force.

[0072] Next, please refer to Fig.15 , step S404 is performed: forming a front device structure 300 on the second surface 102 side, the front device structure 300 including the transistor 200. Therefore, before forming the cavity, the preparation of the front device structure 300 is completed first, so that in the process of forming the front device structure 300, the first substrate 100 can provide a better support force to avoid collapse during the process.

[0073] In an alternative implementation, please refer to Figures 7 to 11 as well as Fig. 20 The groove 150 divides a cavity preset formation area 121a in the sacrificial layer 120; a front device structure is formed on the second surface 102 side, including: forming a gate structure 220 on the second surface 102; using a portion 132a of the second semiconductor material layer corresponding to the cavity preset formation area as the active area 132, performing a doping process, forming a source area 251 in one side of the gate structure 220 of the active area 132, and forming a drain area 252 in the other side.

[0074] Understandably, please combine Fig. 20 and Fig.21The groove 150 divides a cavity preset formation area 121a in the sacrificial layer 120. At the same time, since the groove 150 is extended from the second surface 102, the groove 150 divides a portion 132a of the second semiconductor material layer corresponding to the cavity preset formation area, so that the portions 132a of the two adjacent second semiconductor material layers corresponding to the cavity preset formation area can be spaced apart from each other; the support structure 160 formed at the position of the groove 150 also surrounds the cavity preset formation area 121a. At the same time, since the groove 150 is extended from the second surface 102, the support structure 160 also surrounds the portion 132a of the second semiconductor material layer corresponding to the cavity preset formation area, so that the portions 132a of the two adjacent second semiconductor material layers corresponding to the cavity preset formation area can be spaced apart from each other. In this embodiment, the portion 132a of the second semiconductor material layer corresponding to the preset cavity formation area is the active area 132, the groove 150 is a Stephigh structure (shallow groove structure), and the support structure 160 serves as a medium filled in the Stephigh structure. The groove 150 and the support structure 160 together form a shallow trench isolation structure. There is no need to perform additional shallow trench isolation structure preparation steps to achieve isolation between two adjacent active areas 132, which saves process and is conducive to improving production efficiency.

[0075] Specifically, please refer to Figures 8 to 12 , forming a transistor 200 on the second surface 102 side may include:

[0076] forming a gate dielectric layer 210 on the second surface 102;

[0077] forming a gate structure 220 on the gate dielectric layer 210;

[0078] Using the gate structure 220 as a mask, a portion 132a of the second semiconductor material layer corresponding to the predetermined cavity forming area is used as the active area 132, and a doping process is performed to form a well area 230 in the active area 132;

[0079] Forming a sidewall spacer 240 on a sidewall of the gate structure 220;

[0080] Using the sidewall 240 as a mask, a doping process is performed to form a source region 251 in one side of the active region 132 located at the gate structure 220, and a drain region 252 in the other side; wherein a portion of the source region 251 is located in the well region 230, and a portion of the drain region 252 is located in the well region 230;

[0081] A metal layer 260 is formed, and the metal layer 260 covers the top surface of the gate structure 220 , the source region 251 , and the drain region 252 .

[0082] Optionally, the transistor 200 includes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Of course, the present application does not exclude the case where the transistor 200 is other transistors known to those skilled in the art, and this embodiment does not limit this.

[0083] Optionally, refer to Fig.13 , a front device structure is formed on the second surface 102 side, including: forming a transistor 200 on the second surface 102 side; forming an interlayer dielectric layer 270 on the second surface 102 side, and the interlayer dielectric layer 270 covers the transistor 200. Thus, the transistor 200 is insulated and isolated by the interlayer dielectric layer 270.

[0084] Optionally, the material of the interlayer dielectric layer 270 includes PEOX (Plasma Enhanced Oxide). Of course, the present application does not exclude the case where the material of the interlayer dielectric layer 270 is other interlayer dielectric materials known to those skilled in the art, and this embodiment does not limit this.

[0085] Optionally, refer to Fig.14 and Fig.15 , forming a front device structure 300 on the second surface 102 side, and also including: performing a semiconductor back-end process (BEOL) to form a conductive structure 272 penetrating the interlayer dielectric layer 270 and a wiring layer 280 covering the interlayer dielectric layer 270; wherein one end of the conductive structure 272 is conductively connected to the transistor 200, and the other end is conductively connected to the wiring layer 280. It can be understood that the BEOL process belongs to the Final stage of device preparation. In actual production, after the BEOL process is completed, the front process is basically completed. In this embodiment, the cavity is formed after the BEOL process, which is more conducive to preventing the cavity from being affected by other processes.

[0086] Specifically, performing semiconductor back-end processes may include:

[0087] A through hole 271 is formed penetrating the interlayer dielectric layer 270 , wherein the through hole 271 exposes a portion of the metal layer 260 ;

[0088] Filling material in the through hole 271 to form a conductive structure 272, one end of the conductive structure 272 is conductively connected to the metal layer 260, for conductively leading out the transistor 200;

[0089] A wiring layer 280 covering the interlayer dielectric layer 270 is formed, and the other end of the conductive structure 272 is conductively connected to the wiring layer 280 .

[0090] Optionally, forming the front device structure 300 on the second surface 102 side also includes: forming a passivation layer (not shown) covering the dielectric layer 270 and the wiring layer 280. Thus, the passivation layer prevents the front device structure 300 from being affected in the subsequent process of removing the sacrificial layer 120.

[0091] Optionally, the material of the passivation layer includes SiN. SiN has good corrosion resistance. In the subsequent process of removing the sacrificial layer 120, SiN can better protect the device structure such as the transistor 200 and avoid being affected by the process.

[0092] Optionally, refer to Fig.16 and Fig.17 After forming the front device structure 300 on the second surface 102 side and before forming the release hole on the first surface 101 side, the preparation method further includes: bonding the second substrate 400 on the side of the front device structure 300 away from the first substrate 100; thinning the first semiconductor material layer 110 on the first surface 101 side. Thus, the second substrate 400 can avoid the impact on the front device structure 300 when the device is flipped to perform the thinning process; and as the first semiconductor material layer 110 is thinned, the overall thickness of the device is also continuously reduced. In this process, the device is very likely to warp or even break, and the second substrate 400 can provide better support. After bonding the second substrate 400, the overall thickness of the device increases. Even if the first semiconductor material layer 110 is thinned, the overall thickness of the device can still be guaranteed, reducing the risk of device damage; at the same time, in the subsequent process steps of forming the release hole, the second substrate 400 can also provide better support.

[0093] It can be understood that in actual production, the second substrate 400 is used as a temporary bonding structure, and the second substrate 400 will be removed when the device is packaged.

[0094] Please refer to Fig.18 , step S405 is performed: a release hole 170 is formed on the first surface 101 side, and the release hole 170 extends from the first surface 101 to the second surface 102 until the sacrificial layer 120 is exposed. Therefore, it is convenient to remove the sacrificial layer 120 through the release hole 170 to form a cavity; after the front device structure 300 is formed on the second surface 102 side, the release hole 170 is formed from the first surface 101 side, and the release hole 170 and the front device structure 300 are located on different sides of the first substrate 100, so as to avoid the process of forming the release hole 170 from causing damage to the front device structure 300, which is conducive to ensuring the performance of the device.

[0095] In this embodiment, the process of forming the release hole 170 may include a photolithography process and an etching process.

[0096] Optionally, the aspect ratio of the release hole 170 is in a range of 6 to 10. It is understandable that if the aspect ratio of the release hole 170 is too small, the release hole 170 is too wide, which is very likely to affect the structural strength of the first semiconductor material layer 110, causing the risk of peeling or cracking in other subsequent processes; if the aspect ratio of the release hole 170 is too large, the release hole 170 is too narrow, which is very likely to cause the impurities generated when removing the sacrificial layer 120 to block the release hole 170, resulting in incomplete removal of the sacrificial layer 120, thereby affecting production efficiency and even device performance.

[0097] Please refer to Fig.19 , perform step S406: remove at least part of the sacrificial layer 120 through the release hole 170 to form a cavity 121 at the position of the removed sacrificial layer 120, and the cavity 121 is used to form isolation between the transistor 200 and the first semiconductor material layer 110. Thus, isolation is formed between the transistor 200 and the first semiconductor material layer 110 through the cavity 121, which is conducive to eliminating the parasitic capacitance between the source and drain of the transistor 200 and the first semiconductor material layer 110; under the support of the support structure 160, it is possible to avoid the collapse of the structure located above the sacrificial layer 120 in this step; and the process of removing the sacrificial layer 120 is performed on the first surface 101 of the first substrate 100, that is, on the back of the first substrate 100, which can avoid the process from affecting the front device structure 300.

[0098] As an optional implementation, please Figure 20 to Figure 22 The groove 150 divides a cavity preset formation area 121a in the sacrificial layer 120; removing at least a portion of the sacrificial layer 120, including: at least removing the sacrificial layer 120 located in the cavity preset formation area 121a to form a cavity 121 at the position of the cavity preset formation area 121a; the sidewall of the cavity 121 is formed by the support structure 160. Thus, the cavity preset forming area 121a is divided in the sacrificial layer 120 by the groove 150, and the cavity 121 can be directly formed at the position of the cavity preset forming area 121a, so that the shape of the cavity 121 is controllable and the formation process is simple; the support structure 160 formed at the position of the groove 150 surrounds the cavity preset forming area 121a, so that the side wall of the prepared cavity 121 is formed by the support structure 160, and the support structure 160 serves as a spacing structure between two adjacent cavities 121; and the support structure 160 surrounds the cavity preset forming area 121a. In the process of removing the sacrificial layer 120 located in the cavity preset forming area 121a, the support structure 160 can be used as a barrier layer, so that the requirements for this process are reduced. Under the action of the support structure 160, the problem of process complexity caused by selective etching can be avoided.

[0099] The present application also provides a semiconductor device. Fig.19, semiconductor devices include:

[0100] The first substrate 100 includes a first surface 101 and a second surface 102 opposite to each other. From the first surface 101 to the second surface 102, the first substrate 100 includes a first semiconductor material layer 110 and a second semiconductor material layer 130 arranged at intervals.

[0101] A front device structure 300 , located on the second surface 102 side, the front device structure 300 includes a transistor 200 ;

[0102] The cavity 121 is located between the first semiconductor material layer 110 and the second semiconductor material layer 130 and is used to form isolation between the transistor 200 and the first semiconductor material layer 110;

[0103] A support structure 160 extends from the second surface 102 through the cavity 121 to support the first semiconductor material layer 110 and the second semiconductor material layer 130 that are spaced apart;

[0104] The release hole 170 extends from the first surface 101 until it communicates with the cavity 121 .

[0105] In the embodiment of the present application, the cavity 121 is used to form isolation between the transistor 200 and the first semiconductor material layer 110, which is beneficial to eliminating the parasitic capacitance between the source, drain, etc. of the transistor 200 and the first semiconductor material layer 110; the support structure 160 allows the first semiconductor material layer 110 and the second semiconductor material layer 120 to be spaced apart and provides better support for the structure above the cavity 121; the release hole 170 and the front device structure 300 are located on different sides of the first substrate 100, so as to avoid damage to the front device structure 300 caused by the formation of the release hole 170, which is beneficial to ensuring the performance of the device.

[0106] Optionally, refer to Fig. 22 , the sidewall of the cavity 121 is formed by the support structure 160 . Thus, the support structure 160 serves as an isolation structure between two adjacent cavities 121 .

[0107] It can be understood that in order to clearly show the relationship between the various structures in the semiconductor device, the shape of the gate structure has been changed to a certain extent. Fig. 22 The gate structure is shown as an interdigitated structure. Fig.19 Only a portion of the interdigitated structure is shown schematically.

[0108] Further, the front device structure 300 includes: an active area 132, which is a portion of the second semiconductor material layer corresponding to the cavity; a gate structure 220, which is located on the active area 132; a source area 251, which is located in the active area 132 on one side of the gate structure 220; and a drain area 252, which is located in the active area 132 on the other side of the gate structure 220. It can be understood that since the support structure 160 extends from the second surface 102 through the cavity 121, the support structure 160 surrounds the portion of the second semiconductor material layer corresponding to the cavity, so that the portions of the two adjacent second semiconductor material layers corresponding to the cavity can be spaced from each other. Therefore, the portion of the second semiconductor material layer corresponding to the cavity is the active area 132, and the support structure 160 serves as a shallow trench isolation structure between the two adjacent active areas 132, and there is no need to perform additional shallow trench isolation structure preparation steps, which saves processes and is conducive to improving production efficiency.

[0109] Specifically, the front device structure 300 includes: an active area 132, which is the portion of the second semiconductor material layer corresponding to the cavity; a gate dielectric layer 210, located on the active area 132; a gate structure 220, located on the gate dielectric layer 210; a sidewall 240, located on the sidewall of the gate structure 220; a well region 230, located in the active area 132 on both sides of the gate structure 220; a source region 251, located in the active area 132 on one side of the gate structure 220; a drain region 252, located in the active area 132 on the other side of the gate structure 220; and a metal layer 260, covering the top surface of the gate structure 220, the source region 251 and the drain region 252.

[0110] Optionally, the front device structure 300 further includes an interlayer dielectric layer 270 covering the transistor 200 . Thus, the transistor 200 is insulated and isolated by the interlayer dielectric layer 270 .

[0111] Optionally, the material of the interlayer dielectric layer 270 includes PEOX (Plasma Enhanced Oxide). Of course, the present application does not exclude the case where the material of the interlayer dielectric layer 270 is other interlayer dielectric materials known to those skilled in the art, and this embodiment does not limit this.

[0112] Optionally, the front device structure 300 further includes: a conductive structure 272 penetrating the interlayer dielectric layer 270 and a wiring layer 280 covering the interlayer dielectric layer 270; wherein one end of the conductive structure 272 is conductively connected to the transistor 200, and the other end is conductively connected to the wiring layer 280. It can be understood that the conductive structure 272 and the wiring layer 280 are formed in the semiconductor back end of line (BEOL) process, and the BEOL process belongs to the final stage of device preparation. In actual production, after the BEOL process is completed, the front process is basically completed. In this embodiment, the cavity 121 is formed after the BEOL process, which is more conducive to preventing the cavity 121 from being affected by other processes.

[0113] Optionally, the front device structure 300 further includes a passivation layer (not shown) covering the interlayer dielectric layer 270 and the wiring layer 280. Thus, the front device structure 300 is protected from being affected by the process by the passivation layer.

[0114] Optionally, the material of the passivation layer includes SiN. SiN has good corrosion resistance. In the process of removing the sacrificial layer 120 in actual preparation, SiN can better protect the device structure such as the transistor 200 and avoid being affected by the process.

[0115] Optionally, the aspect ratio of the release hole 170 is in a range of 6 to 10. It is understandable that if the aspect ratio of the release hole 170 is too small, the release hole 170 is too wide, which is very likely to affect the structural strength of the first semiconductor material layer 110, causing the risk of peeling or cracking in other subsequent processes; if the aspect ratio of the release hole 170 is too large, the release hole 170 is too narrow, which is very likely to cause the impurities generated when removing the sacrificial layer 120 to block the release hole 170, resulting in incomplete removal of the sacrificial layer 120, thereby affecting production efficiency and even device performance.

[0116] Optionally, the material of the support structure 160 includes AlN and / or Al2O3. Both AlN and Al2O3 have good corrosion resistance. When forming the cavity 121, AlN and Al2O3 are not easily affected by the process to ensure the structural strength of the support structure 160; and AlN and Al2O3 have good mechanical properties and can provide good support force.

[0117] It should be noted that the semiconductor device embodiment and the semiconductor device preparation method embodiment provided in the present application belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes can be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments can also be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a first substrate, the first substrate comprising a first surface and a second surface opposite to each other, the first substrate comprising a first semiconductor material layer, a sacrificial layer, and a second semiconductor material layer sequentially stacked from the first surface to the second surface; forming a groove on the second surface side, wherein the groove extends from the second surface to the first surface and penetrates the sacrificial layer; filling the groove with material to form a support structure; forming a front-side device structure on the second surface side, the front-side device structure comprising a transistor; forming a release hole on the first surface side, wherein the release hole extends from the first surface to the second surface until the sacrificial layer is exposed; At least a portion of the sacrificial layer is removed through the release hole to form a cavity at a location of the removed sacrificial layer, wherein the cavity is used to form isolation between the transistor and the first semiconductor material layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: The process of removing at least part of the sacrificial layer comprises a wet etching process; Before forming the groove on the second surface side, the method also includes: performing an ion implantation process on the sacrificial layer, wherein the etching rate of the sacrificial layer after the ion implantation process in the wet etching process is greater than the etching rate of the sacrificial layer without the ion implantation process in the wet etching process.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The groove divides a preset cavity formation area in the sacrificial layer; The removing at least part of the sacrificial layer comprises: removing at least the sacrificial layer located in the cavity preset forming area to form a cavity at the position of the cavity preset forming area; The side walls of the cavity are formed by the support structure.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The forming of a front device structure on the second surface side comprises: forming a gate structure on the second surface; A doping process is performed with a portion of the second semiconductor material layer corresponding to the preset cavity formation area as the active area to form a source area in one side of the gate structure and a drain area in the other side of the active area.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: After forming the front device structure on the second surface side and before forming the release hole on the first surface side, the method further includes: bonding a second substrate on a side of the front device structure away from the first substrate; and thinning the first semiconductor material layer on the first surface side.

6. The method for preparing a semiconductor device according to claim 1, wherein: The material of the support structure includes AlN and / or Al2O3.

7. A semiconductor device, characterized in that: include: A first substrate, comprising a first surface and a second surface opposite to each other, and in a direction from the first surface to the second surface, the first substrate comprises a first semiconductor material layer and a second semiconductor material layer arranged at intervals; a front device structure, located on the second surface side, specifically on the surface side of the second semiconductor material layer away from the first semiconductor material layer, the front device structure comprising a transistor; a cavity, located between the first semiconductor material layer and the second semiconductor material layer, for forming isolation between the transistor and the first semiconductor material layer; A support structure extending from the second surface through the cavity to support the first semiconductor material layer and the second semiconductor material layer that are spaced apart; A release hole extends from the first surface until it is connected with the cavity, and the release hole is used to form the cavity after the support structure is formed.

8. The semiconductor device according to claim 7, characterized in that The side walls of the cavity are formed by the support structure.

9. The semiconductor device according to claim 8, characterized in that The front device structure comprises: An active region is a portion of the second semiconductor material layer corresponding to the cavity; A gate structure, located on the active area; a source region located in the active region on one side of the gate structure; A drain region is located in the active region on the other side of the gate structure.

10. The semiconductor device according to claim 7, wherein: The material of the support structure includes AlN and / or Al2O3.

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