Test piece for detecting etching uniformity, use of test piece and preparation method thereof

Abstract

The present invention provides a test piece for detecting etching uniformity, use of the test piece and a preparation method thereof, which relates to the field of semiconductor technology, and includes: an original wafer, a through silicon via unit is arranged on the front side of the original wafer, the through silicon via unit includes a radial through silicon via unit arranged in the direction of a dividing line that divides the original wafer into equal parts along the radial direction, and a center through silicon via unit arranged at the center of the original wafer, wherein the radial spacing of two adjacent radial through silicon via units in the same dividing line direction is the same; each through silicon via unit includes a plurality of through silicon via groups arranged at equal intervals, each through silicon via group includes a plurality of through silicon holes, each through silicon hole is filled with a filler, and the filler forms a columnar structure in the through silicon hole; a carrier wafer, the carrier wafer is bonded to the front side of the original wafer. Using the test piece provided by the embodiment of the present invention, the etching uniformity of the wafer can be quickly and conveniently detected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test piece for detecting etching uniformity, and a use and preparation method of the test piece. Background Art

[0002] Etching process is an indispensable part of microelectronics processing. When manufacturing various chips and devices, the etching process can process and improve materials. However, the quality and efficiency of the etching process are affected by factors such as etching uniformity.

[0003] The traditional method of testing etching uniformity is to calculate the etching rate of a single point by measuring the thickness difference before and after a fixed position, and then compare the etching rates of different positions evenly distributed on the wafer to obtain the etching uniformity.

[0004] Etching rate = (thickness before etching - thickness after etching) / etching time;

[0005] Etching uniformity = (maximum etching value - minimum etching value) / (maximum etching value + minimum etching value).

[0006] This testing method is highly dependent on precision measuring instruments, and it is difficult to confirm the same position before and after etching. At the same time, the data needs to be calculated complexly, which is time-consuming, labor-intensive and inefficient. Summary of the invention

[0007] In view of this, the embodiments of this specification provide a test piece for detecting etching uniformity, and a method for using and preparing the test piece, so as to achieve the purpose of quickly and conveniently detecting etching uniformity and calculating etching amount.

[0008] This application provides the following technical solutions:

[0009] A detection sheet for detecting etching uniformity, comprising:

[0010] An original wafer, wherein a through silicon via unit is arranged on the front side of the original wafer, wherein the through silicon via unit comprises a radial through silicon via unit arranged in the direction of a dividing line that divides the original wafer into equal parts along a radial direction, and a central through silicon via unit arranged at the center of the original wafer, wherein radial spacings of two adjacent radial through silicon via units in the same dividing line direction are the same;

[0011] Each through silicon via unit includes a plurality of through silicon via groups arranged at equal intervals, each through silicon via group includes a plurality of through silicon vias, each through silicon via is filled with a filler, and the filler forms a columnar structure in the through silicon via;

[0012] Carrier wafer, the front side of the carrier wafer is bonded to the original wafer.

[0013] Furthermore, in each TSV group, the depths of the TSVs decrease in sequence according to the order of their arrangement positions, and the depth difference between two adjacent TSVs is the same, and the depth difference is a preset etching amount error.

[0014] Furthermore, in each TSV group, the distances between two adjacent TSVs are the same.

[0015] A method for using a detection sheet for detecting etching uniformity, using the detection sheet to detect etching uniformity, comprising:

[0016] Select etching solution or etching gas according to the material of the original wafer and the material of the filler;

[0017] Use etching solution or etching gas to etch the detection piece;

[0018] The etching uniformity is calculated by detecting the number of columnar structures exposed in each TSV unit in the wafer.

[0019] Furthermore, it also includes:

[0020] The depth difference between two adjacent through silicon vias is set as a hole depth difference a, and the etching amount is calculated according to the number of exposed columnar structures and the hole depth difference a, wherein the etching amount=the number of exposed columnar structures×the hole depth difference a.

[0021] Furthermore, the etching uniformity is calculated by detecting the number of columnar structures exposed in each through silicon via unit in the wafer, including:

[0022] Taking the through silicon via group as a unit, the number of columnar structures exposed on the original wafer surface is taken as the exposed number of the through silicon via group;

[0023] Taking the TSV unit as a unit, the maximum value of the exposed quantity of all TSV groups in each TSV unit is used as the maximum exposed quantity of each TSV unit, and the minimum value is used as the minimum exposed quantity of each TSV unit;

[0024] Taking the original wafer as a unit, the maximum value of the maximum exposed number of all through silicon via units is taken as the maximum etching value, and the minimum value of the minimum exposed number of all through silicon via units is taken as the minimum etching value;

[0025] The maximum etching value and the minimum etching value are brought into the uniformity calculation formula to calculate the etching uniformity.

[0026] Furthermore, according to the material of the original wafer and the material of the filler, the etching solution or etching gas is selected, including:

[0027] When the same etching solution or etching gas is used, the ratio of the etching amount of the original wafer to the etching amount of the filler is greater than or equal to 10:1.

[0028] A method for preparing a test piece for detecting etching uniformity, comprising:

[0029] On the front side of the original wafer, the original wafer is punched using the TSV process to generate a wafer containing through-silicon vias;

[0030] Filling or electroplating a filler into the through silicon vias of the original wafer to generate a filled wafer;

[0031] Bonding the front side of the filled wafer to the carrier wafer using a bonding process to generate a bonded wafer;

[0032] The back side of the bonded wafer is thinned until the deepest through-silicon via is exposed to produce a test wafer.

[0033] Furthermore, the filler is a non-metallic medium or a metal.

[0034] Furthermore, it also includes:

[0035] After the filler is filled or electroplated into the through silicon vias of the original wafer, the original wafer is annealed.

[0036] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0037] The dividing line divides the disk of the original wafer into equal parts, and the radial through silicon via unit is set on the dividing line. The radial spacing between two adjacent radial through silicon via units in the same radial direction is the same. A center through silicon via unit is set at the center of the original wafer, so that each position of the original wafer is provided with a through silicon via, and the distribution of the through silicon vias is uniform, which improves the accuracy of the etching amount and uniformity calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 is a schematic diagram of a test piece for detecting etching uniformity according to an embodiment of the present invention;

[0040] Figure 2 yes Figure 1 Schematic diagram of a through silicon via unit in a test piece;

[0041] Figure 3 is a schematic diagram of a method for using a test piece according to an embodiment of the present invention;

[0042] Figure 4 is a schematic diagram of a method for preparing a test piece according to an embodiment of the present invention;

[0043] Figure 5 is a schematic diagram of a method for calculating etching uniformity according to an embodiment of the present invention;

[0044] Figure 6 is a schematic diagram of a method for calculating etching amount according to an embodiment of the present invention;

[0045] Figure 7 Schematic diagram of a through silicon via unit portion of a film according to an embodiment of the present invention.

[0046] Reference numerals in the figure: 1, original wafer; 2, through silicon via unit; 3, through silicon via group; 301, through silicon via; 302, columnar structure; 4, carrier wafer. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] like Figure 1 and Figure 2 As shown, the test piece for detecting etching uniformity according to the embodiment of the present invention comprises:

[0050] The original wafer 1 is provided with a through silicon via unit 2 on the front side of the original wafer 1. The through silicon via unit 2 includes a radial through silicon via unit provided in the direction of a dividing line that divides the original wafer 1 in the radial direction, and a center through silicon via unit provided at the center of the original wafer 1, wherein the radial spacing of two adjacent radial through silicon via units in the same radial direction is the same. The dividing line divides the disk of the original wafer 1 in half, and the radial through silicon via unit is provided on the dividing line. At the same time, the radial spacing of two adjacent radial through silicon via units in the same radial direction is the same. Finally, the center through silicon via unit is also provided at the center of the original wafer 1, so that each position of the original wafer 1 is distributed with through silicon vias 301, and the distribution of the through silicon vias 301 is relatively uniform, thereby improving the accuracy of the calculation of the etching amount and uniformity.

[0051] like Figure 2 As shown, each TSV unit 2 includes a plurality of TSV groups 3 arranged at equal intervals, each TSV group 3 includes a plurality of TSVs 301 , and each TSV 301 is filled with a filler, which forms a columnar structure 302 in the TSV 301 .

[0052] The carrier wafer 4 is bonded to the front side of the original wafer 1 .

[0053] In each TSV group 3, the depths of the TSVs 301 decrease in sequence according to the order of their positions, and the depth difference between two adjacent TSVs 301 is the same, which is the error value of the etching amount. In each TSV group 3, the TSVs 301 are arranged at equal intervals.

[0054] like Figure 3 As shown, the method for using the detection sheet according to the embodiment of the present invention includes:

[0055] According to the material of the original wafer 1 and the material of the filler, an etching solution or an etching gas is selected; the test piece is etched using the etching solution or the etching gas; and the etching uniformity is calculated by the number of columnar structures 302 exposed in each silicon via unit in the test piece.

[0056] The etching uniformity is calculated using the detection sheet. The etching uniformity calculation formula is: etching uniformity = (etching maximum value - etching minimum value) / (etching maximum value + etching minimum value).

[0057] like Figure 4 As shown, the method for preparing the etching uniformity detection sheet includes:

[0058] On the front side of the original wafer 1, the TSV process is used to perform a drilling operation on the original wafer 1 to generate a wafer containing a through-silicon via; the filler is filled or electroplated into the through-silicon via of the original wafer to generate a filled wafer; after the filler is filled or electroplated into the through-silicon via 301 of the original wafer 1, the original wafer 1 is annealed; the front side of the filled wafer (i.e., the front side of the original wafer 1) is bonded to the carrier wafer 4 using a bonding process to generate a bonded wafer; the back side of the bonded wafer is thinned until the deepest through-silicon via 301 is exposed to produce a test piece.

[0059] After the filler is filled or electroplated into the through silicon via 301 of the original wafer 1, an annealing process is required. The annealing process is used to reorganize the lattice of the original wafer 1, remove stress, and restore lattice damage.

[0060] Specifically, the carrier wafer 4 may be a silicon wafer or a wafer made of other materials. The filler may be silicon nitride.

[0061] Specifically, the diameter of the through silicon via 301 may be slightly larger, so as to facilitate the inspection of the number of exposed columnar structures 302 , and the process difficulty of manufacturing the through silicon via 301 with a large diameter may be reduced.

[0062] In one embodiment, the deeper side of the through silicon via 301 is close to the outer diameter of the original wafer 1, and the shallower side of the through silicon via 301 is close to the center of the original wafer 1. In other embodiments, the shallower side of the through silicon via 301 is close to the outer diameter of the original wafer 1, and the deeper side of the through silicon via 301 is close to the center of the original wafer 1.

[0063] In one embodiment, the filler (including a non-metallic dielectric layer or a metal electroplating layer) in the through silicon via 301 should be selected such that the material does not react with the etching solution or etching gas to avoid uniformity calculation errors caused by etching of the filler. Preferably, the color of the filler may be different from the color of the original wafer 1, so that the columnar structure 302 formed by the filler is easier to identify.

[0064] In one embodiment, an etching solution or etching gas is selected according to the material of the original wafer 1 and the material of the columnar structure 302. The etching ratio of the material of the original wafer 1 to the filler is ≥10:1. That is, when the same etching solution or etching gas is used, the ratio of the etching amount of the original wafer 1 to the etching amount of the filler is greater than or equal to 10:1. Preferably, the etching ratio is greater than 20:1, and after etching, it is confirmed whether the columnar structures 302 exposed in each silicon through-hole unit 2 are consistent to determine the uniformity.

[0065] The etching amount is the number of exposed columnar structures 302×the hole depth difference a. Figure 5 As shown, when one columnar structure 302 is exposed during etching, the etching amount is a. When two columnar structures 302 are exposed during etching, the etching amount is 2a.

[0066] The depth difference between two adjacent through silicon vias 301 is the error value of the etching amount (preset etching amount error). If the etching amount needs to be calculated, the hole depth difference a should be set to be less than 1 / 3 times the allowable etching amount tolerance. The allowable etching amount tolerance is a parameter set in the manufacturing process.

[0067] In one embodiment, the steps of calculating etching uniformity are:

[0068] Taking the TSV group as a unit, the number of columnar structures 302 exposed on the original wafer surface is taken as the exposed number of the TSV group 3; taking the TSV unit 2 as a unit, the maximum value of the exposed number of all TSV groups 3 in each TSV unit 2 is taken as the maximum exposed number of each TSV unit 2, and the minimum value is taken as the minimum exposed number of each TSV unit 2; taking the original wafer 1 as a unit, the maximum value of the maximum exposed number of all TSV units 2 is taken as the maximum etching value, and the minimum value of the minimum exposed number of all TSV units 2 is taken as the minimum etching value; the maximum etching value and the minimum etching value are brought into the uniformity calculation formula to calculate the etching uniformity.

[0069] like Figure 1 and Figure 6 As shown, use Figure 1 The test piece, Figure 6 For example, a through silicon via unit 2 in the figure includes four through silicon via groups 3, and the exposed numbers of the four through silicon via groups 3 are 11, 10, 11, and 11 respectively. Taking the through silicon via unit 2 in the figure as a unit, the maximum exposed number of the unit is 11, and the minimum exposed number of the unit is 10. Figure 6 The list in the lower right middle is the list of the maximum exposed number of units and the minimum exposed number of units for all units. The maximum value of the maximum exposed number of units (11 in the figure) is used as the maximum etching value, and the minimum value of the minimum exposed number of units (10 in the figure) is used as the minimum etching value.

[0070] According to the etching uniformity calculation formula, the etching uniformity is calculated. Etching uniformity = (etching maximum value - etching minimum value) / (etching maximum value + etching minimum value), substituting the values, the etching uniformity is calculated to be 4.77%.

[0071] like Figure 1 and Figure 7 As shown, the manufacturing method of the detection sheet of the embodiment of the present invention can also be used to make a transparent film, such as Figure 1 As shown, the structure of the film is the same as that of the test piece. Figure 7 This is an enlarged view of the through silicon via unit, such as Figure 7 As shown, each aperture position on the film has a ring-shaped marked position and hole depth value that is larger than the designed aperture, which is convenient for checking the etching status.

[0072] After the detection sheet of the embodiment of the present invention is used, it can be ground and thinned again (the thinning depth is: the change in the number of columns etched during the detection × the set hole depth difference a) and reused. When it is used again, the exposed number of columnar structures 302 at each position needs to be calibrated (etched number - exposed number).

[0073] In one embodiment, Figure 1 and Figure 2As shown, 25 units are set in the original wafer 1. Except for one (center silicon via unit) distributed at the center of the circle, the other units (radial silicon via units) are evenly distributed on the original wafer 1 according to the center of the circle. The aperture of the silicon via 301 on the silicon via unit 2 is 10um, and the hole depth of the silicon via 301 is 10-50um, which is evenly reduced according to the set value of 1um (depth difference). There are four silicon vias 301 in each hole depth. Among them, the depth difference of adjacent holes 1um is the error value of the etching amount. The columnar structure 302 is silicon nitride. If the columnar structure 302 is silicon nitride, the annealing temperature is 1000℃ (the temperature is 1000℃ when the columnar structure 302 is a non-metallic dielectric layer, and the temperature is 700℃ when the filler is an electroplated metal layer), and the processing time is 20s. The carrier wafer 4 is bonded to the original wafer 1, and the carrier wafer 4 is a silicon wafer. After the original wafer 1 is thinned to a 50um hole, annealing is performed to eliminate stress and restore lattice damage. After the test piece is manufactured according to the above steps, when testing the etching uniformity, Cl2 and HBr dry etching wafers are selected, and the etching ratio of wafer silicon material to silicon nitride is ≥20:1. After etching, confirm whether the number of exposed columns in each module is consistent to judge the uniformity. Specifically, if the etching amount needs to be calculated, it can be calculated based on the change in the number of exposed columnar structures 302 × the set hole depth difference of 1um. 11 columnar structures 302 are etched at the position of maximum etching, and the difference between the columnar structures 302 is 1um, so the etching amount is 11um.

[0074] Beneficial effects of the embodiments of the present invention:

[0075] The embodiment of the present invention calculates uniformity by comparing the difference in the number of columnar structures exposed before and after etching through a detection sheet, and calculates the etching amount at the corresponding position by multiplying the change in the number of columnar structures by the difference in hole depth a. This is convenient and simple, and the entire detection process is visualized, which reduces the demand for high-order detection instruments and saves instrument costs in the research and development stage or the small batch stage. It overcomes the problems of high dependence on precision measuring instruments, difficulty in confirming the same position before and after etching, complex data processing and calculation, and low measurement efficiency in the traditional etching uniformity confirmation process; by using TSV to make uniformly distributed holes on the front side of the original wafer, the holes are evenly distributed on the original wafer according to the through silicon via units, and the through silicon via depths of the through silicon via groups in the through silicon via units are evenly reduced from large to small according to the set value. After electroplating or filling in the through silicon vias, they are temporarily bonded, and then the back side of the original wafer is thinned to expose the deepest hole as a test sheet. The method for making the test sheet is simple; the test sheet can be reused after polishing, which can effectively save costs.

[0076] The above is only a specific embodiment of the present invention, and cannot be used to limit the scope of the invention. Therefore, the replacement of equivalent components, or equivalent changes and modifications made according to the scope of protection of the patent of the present invention, should still fall within the scope of this patent. In addition, the technical features of the present invention can be freely combined with each other, with each other, and with each other.

Claims

1. A test piece for detecting etching uniformity, characterized in that: include: An original wafer (1), wherein a through silicon via unit (2) is arranged on the front side of the original wafer (1), and the through silicon via unit (2) comprises a radial through silicon via unit arranged in the direction of a dividing line that divides the original wafer (1) into equal parts along a radial direction, and a center through silicon via unit arranged at the center of the original wafer (1), wherein the radial spacing between two adjacent radial through silicon via units in the same dividing line direction is the same; Each of the through silicon via units comprises a plurality of through silicon via groups (3) arranged at equal intervals, each through silicon via group (3) comprises a plurality of through silicon holes (301), each through silicon hole (301) is filled with a filler, the filler forms a columnar structure (302) in the through silicon hole (301), and in each through silicon via group (3), the depths of the through silicon holes (301) decrease in sequence according to the order of arrangement positions, and the depth difference between two adjacent through silicon holes (301) is the same, and the depth difference is a preset etching amount error; A carrier wafer (4), the carrier wafer (4) is bonded to the front side of the original wafer (1).

2. The test piece for detecting etching uniformity according to claim 1, characterized in that: In each through silicon via group (3), the through silicon vias (301) are arranged at equal intervals.

3. A method for using a test piece, using the test piece for detecting etching uniformity according to any one of claims 1 to 2 to detect etching uniformity, characterized in that: include: Selecting etching solution or etching gas according to the material of the original wafer (1) and the material of the filler; Using the etching solution or the etching gas to etch the test piece; The etching uniformity is calculated by the number of columnar structures (302) exposed in each of the through silicon via units in the test piece.

4. The method of use according to claim 3, characterized in that: Also includes: The depth difference between two adjacent silicon through holes (301) is set as a hole depth difference a, and the etching amount is calculated according to the number of exposed columnar structures (302) and the hole depth difference a, wherein the etching amount = the number of exposed columnar structures (302) × the hole depth difference a.

5. The method of use according to claim 3, characterized in that: The etching uniformity is calculated by the number of columnar structures (302) exposed in each of the through silicon via units in the test piece, including: Taking the through silicon via group (3) as a unit, the number of columnar structures (302) exposed on the surface of the original wafer (1) is taken as the exposed number of the through silicon via group (3); Taking the through silicon via unit (2) as a unit, the maximum value of the exposed number of all through silicon via groups (3) in each through silicon via unit (2) is used as the maximum exposed number of each through silicon via unit (2), and the minimum value is used as the minimum exposed number of each through silicon via unit (2); Taking the original wafer (1) as a unit, the maximum value of the maximum exposed number of all the through silicon via units (2) is taken as the maximum etching value, and the minimum value of the minimum exposed number of all the through silicon via units (2) is taken as the minimum etching value; The maximum etching value and the minimum etching value are brought into a uniformity calculation formula to calculate the etching uniformity.

6. The method of use according to claim 3, characterized in that: According to the material of the original wafer (1) and the material of the filler, an etching solution or an etching gas is selected, including: When the same etching solution or etching gas is used, the ratio of the etching amount of the original wafer (1) to the etching amount of the filler is greater than or equal to 10:

1.

7. A method for preparing a test piece for detecting etching uniformity, the method being used for preparing the test piece according to any one of claims 1 to 2, characterized in that: include: On the front side of the original wafer (1), a drilling operation is performed on the original wafer (1) using a TSV process to generate a wafer including a through silicon via; Filling or electroplating the filler into the through silicon via (301) of the original wafer (1) to generate a filled wafer; Bonding the front side of the filled wafer to a carrier wafer (4) using a bonding process to generate a bonded wafer; The back side of the bonded wafer is thinned until the deepest through silicon via (301) is exposed, thereby manufacturing the test piece.

8. The preparation method according to claim 7, characterized in that: The filler is a non-metallic medium or a metal.

9. The preparation method according to claim 7, characterized in that: Also includes: After the filler is filled or electroplated into the through silicon via (301) of the original wafer (1), the original wafer (1) is annealed.

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