OFDR fast demodulation system and method based on FPGA

Abstract

The present invention discloses an OFDR fast demodulation system and method based on FPGA. A multi-channel high-speed parallel data cache and data processing device is constructed based on the FPGA chip and the DDR chip. The cache space of the DDR chip is artificially divided into four cache blocks, and four data channels are constructed therefrom. The FPGA chip writes various types of data generated in the wavelength drift demodulation process into different cache blocks for cache through the four data channels, and reads various types of data from different cache blocks for corresponding data processing. The four data channels can work simultaneously to perform data cache and data processing in different algorithm stages of wavelength drift demodulation without affecting each other, thereby greatly improving the data processing speed of wavelength drift demodulation.

Description

Technical Field

[0001] The present invention relates to OFDR demodulation technology, and in particular to an OFDR fast demodulation system and method based on FPGA. Background Art

[0002] Optical frequency domain reflectometry (OFDR) technology has attracted the attention of many scholars and R&D personnel of technology companies due to its extremely high spatial resolution and sensitivity. It has been widely used in aerospace, deep-sea sensing, ecological environment monitoring, medical diagnosis and other fields. The advantages of OFDR sensing technology are high spatial resolution and high measurement sensitivity. The disadvantage is that a large amount of data needs to be processed to obtain the target sensing quantity. The amount of sensor demodulation data is hundreds of thousands or even millions of points. The traditional data processing method is to directly use a personal computer to process, but this method takes a long time and is slow, so the sensing speed of OFDR has been criticized by scholars from all sides. Summary of the invention

[0003] In order to solve the above-mentioned deficiencies in the prior art, the present invention provides an OFDR fast demodulation system and method based on FPGA to improve the demodulation speed of OFDR.

[0004] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] An OFDR fast demodulation system based on FPGA, comprising an FPGA chip and a DDR chip, wherein the DDR chip comprises a first cache block, a second cache block, a third cache block and a fourth cache block, and a first data channel, a second data channel, a third data channel and a fourth data channel arranged in parallel are constructed between the FPGA chip and the DDR chip;

[0006] The FPGA chip writes the time domain data of the reference signal and the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel;

[0007] The FPGA chip reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip through the read channel of the first data channel, and then performs column FFT processing on the time domain data of the reference signal and the measurement signal and multiplies them by the rotation factor, and then writes the product data of the reference signal and the measurement signal into the second cache block of the DDR chip through the write channel of the second data channel;

[0008] The FPGA chip reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip through the read channel of the second data channel, and then performs row FFT processing on the product data of the reference signal and the measurement signal, and then writes the distance domain data of the reference signal and the measurement signal into the third cache block and the fourth cache block of the DDR chip through the write channels of the third data channel and the fourth data channel respectively;

[0009] The FPGA chip reads the distance domain data of the reference signal and the measurement signal from the third cache block and the fourth cache block of the DDR chip respectively through the read channels of the third data channel and the fourth data channel, and then performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity.

[0010] Furthermore, the FPGA chip includes:

[0011] The two-dimensional FFT module is used to perform two-dimensional FFT processing on the reference signal and the measurement signal in the first data channel and the second data channel.

[0012] Furthermore, the FPGA chip also includes:

[0013] A windowing and zero-filling module is used to perform windowing and zero-filling processing on the distance domain data of the reference signal and the measurement signal during wavelength drift demodulation;

[0014] An inverse FFT module, used for performing inverse FFT processing on the distance domain data of the reference signal and the measurement signal after the windowing and zero-filling processing during wavelength drift demodulation to obtain the spectrum domain data of the reference signal and the measurement signal;

[0015] A mean filtering module, used for performing mean filtering processing on the spectral domain data of the reference signal and the measurement signal during wavelength drift demodulation;

[0016] A cross-correlation module, used for performing cross-correlation processing on the spectral domain data of the reference signal and the measurement signal after the mean filtering processing during wavelength drift demodulation to obtain a cross-correlation spectrum between the reference signal and the measurement signal;

[0017] A peak detection module, used for performing peak detection on the cross-correlation spectrum between the reference signal and the measurement signal during wavelength drift demodulation to obtain the peak position of the cross-correlation spectrum;

[0018] The drift demodulation module is used to determine the spectral drift amount between the reference signal and the measurement signal according to the peak position during wavelength offset demodulation, and then calculate the target sensing amount.

[0019] Furthermore, the FPGA chip also includes an arbitration control module and an AXI bus module, the arbitration control module includes a write arbitration controller and a read arbitration controller, the AXI bus module includes an AXI write data bus and an AXI read data bus, wherein

[0020] The write arbitration controller is used to identify the source channels of various types of data of the reference signal and the measurement signal, and generate write target addresses for various types of data according to the source channels;

[0021] The AXI write data bus is used to write various types of data of the reference signal and the measurement signal into a cache block corresponding to the write target address through the AXI4 data transmission protocol;

[0022] The read arbitration controller is used to identify a request channel of a data read instruction and generate a read target address according to the request channel;

[0023] The AXI read data bus is used to read various types of data of the reference signal and the measurement signal from the cache block corresponding to the read target address through the AXI4 data transmission protocol.

[0024] Furthermore, the read arbitration controller includes an address transformation module. When the read arbitration controller reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a column-first manner and then read the time domain data; when the read arbitration controller reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a row-first manner and then read the product data.

[0025] An OFDR fast demodulation method based on FPGA is applied to the above-mentioned OFDR fast demodulation system; the steps of the OFDR fast demodulation method are as follows:

[0026] Step 100: the FPGA chip writes the time domain data of the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel;

[0027] Step 200: the FPGA chip reads the time domain data of the reference signal from the first cache block of the DDR chip through the read channel of the first data channel, then performs column FFT processing on the time domain data of the reference signal and multiplies it by the rotation factor, and then writes the product data of the reference signal into the second cache block of the DDR chip through the write channel of the second data channel;

[0028] Step 300: the FPGA chip reads the product data of the reference signal from the second cache block of the DDR chip through the read channel of the second data channel, performs row FFT processing on the product data of the reference signal, and then writes the distance domain data of the reference signal into the third cache block of the DDR chip through the write channel of the third data channel;

[0029] Step 400: the FPGA chip writes the time domain data of the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel;

[0030] Step 500: the FPGA chip reads the time domain data of the measurement signal from the first cache block of the DDR chip through the read channel of the first data channel, then performs column FFT processing on the data of the measurement signal and multiplies it by a rotation factor, and then writes the product data of the measurement signal into the second cache block of the DDR chip;

[0031] Step 600: the FPGA chip reads the product data of the measurement signal from the second cache block of the DDR chip through the read channel of the second data channel, performs row FFT processing on the product data of the measurement signal, and writes the distance domain data of the measurement signal into the fourth cache block of the DDR chip;

[0032] Step 700: The FPGA chip reads the distance domain data of the reference signal and the measurement signal from the third cache block and the fourth cache block of the DDR chip through the read channels of the third data channel and the fourth data channel, respectively, and then performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity.

[0033] Furthermore, in step 200 and step 300 and step 500 and step 600, the FPGA chip uses a two-dimensional FFT module to perform two-dimensional FFT processing on the reference signal and the measurement signal in the first data channel and the second data channel respectively.

[0034] Further, in step 700, the FPGA chip performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity in the following steps:

[0035] Step 710: the FPGA chip uses a windowing and zero-filling module to perform windowing and zero-filling processing on the distance domain data of the reference signal and the measurement signal;

[0036] Step 720: the FPGA chip uses an inverse FFT module to perform inverse FFT processing on the distance domain data of the reference signal and the measurement signal that have undergone windowing and zero-filling processing to obtain spectrum domain data of the reference signal and the measurement signal;

[0037] Step 730: the FPGA chip uses a mean filter module to perform mean filtering on the spectral domain data of the reference signal and the measurement signal;

[0038] Step 740: the FPGA chip uses a cross-correlation module to perform cross-correlation processing on the spectral domain data of the reference signal and the measurement signal after the mean filtering process, to obtain a cross-correlation spectrum between the reference signal and the measurement signal;

[0039] Step 750: The FPGA chip uses a peak detection module to perform peak detection on the cross-correlation spectrum between the reference signal and the measurement signal to obtain the peak position of the cross-correlation spectrum;

[0040] Step 760: The FPGA chip uses a drift demodulation module to determine the spectral drift between the reference signal and the measurement signal according to the peak position, and then calculates the target sensing value.

[0041] Furthermore, the steps of the FPGA chip writing various data of the reference signal and the measurement parameters into the DDR chip are as follows:

[0042] The FPGA chip uses a write arbitration controller to identify source channels of various types of data of the reference signal and the measurement signal, and generates write target addresses for various types of data according to the source channels;

[0043] The FPGA chip uses the AXI write data bus to write various data of the reference signal and the measurement signal into the cache block corresponding to the write target address through the AXI4 data transmission protocol;

[0044] The steps of the FPGA chip reading various data of the reference signal and measurement parameters from the DDR chip are as follows:

[0045] The FPGA chip uses a read arbitration controller to identify a request channel for a data read instruction, and generates a read target address according to the request channel;

[0046] The FPGA chip uses an AXI read data bus to read various types of data of the reference signal and the measurement signal from a cache block corresponding to the read target address through an AXI4 data transmission protocol.

[0047] Furthermore, the read arbitration controller includes an address transformation module. When the read arbitration controller reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a column-first manner and then read the time domain data; when the read arbitration controller reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a row-first manner and then read the product data.

[0048] The present invention has the following beneficial effects:

[0049] The OFDR fast demodulation system of the present invention adopts the first beat frequency signal of the auxiliary interference arm as the sampling clock signal of the ADC data acquisition circuit board, which can reduce the influence of the nonlinear frequency sweeping light of the tunable laser TLS on the wavelength drift demodulation result; the FPGA circuit board is used for data processing, and a complete OFDR demodulation algorithm based on wavelength drift demodulation is deployed in the FPGA circuit board, so a single FPGA chip can be used to complete OFDR sensor demodulation, without the need for other data processing chips to participate in the data processing of the system, thereby improving the demodulation speed and the system integration;

[0050] The present invention uses a two-dimensional FFT algorithm to perform FFT processing on the time domain data of the reference signal and the measurement signal, and can realize FFT of a very large number of points at a relatively low resource cost, thereby ensuring the accuracy of system sensing; in order to realize the two-dimensional FFT algorithm in the FPGA, the present invention divides the cache space of the DDR chip into four cache blocks, and constructs four parallel data channels between the FPGA chip and the DDR chip for data caching and dimensional conversion. The four cache blocks have similar structures, and can cache large number of data and realize data dimension conversion, so as to realize high-speed parallel data throughput of very large number of data;

[0051] The OFDR fast demodulation system of the present invention constructs a multi-channel high-speed parallel data cache and data processing device based on the FPGA chip and the DDR chip, artificially divides the cache space of the DDR chip into four cache blocks, and constructs four data channels. The FPGA chip writes various types of data generated in the wavelength drift demodulation process into different cache blocks for caching through the four data channels, and reads various types of data from different cache blocks for corresponding data processing. The four data channels can work simultaneously to perform data caching and data processing in different algorithm stages of wavelength drift demodulation without affecting each other, thereby greatly improving the data processing speed of wavelength drift demodulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a connection diagram of the optical frequency domain reflectometer, fast demodulation system and host computer provided by the present invention.

[0053] Figure 2 This is a schematic diagram of the principle structure of the optical frequency domain reflectometer provided by the present invention.

[0054] Figure 3 This is a schematic diagram of the principle architecture of the fast demodulation system provided by the present invention.

[0055] Figure 4 This is a flowchart of the algorithm processing of the FPGA chip in the fast demodulation system provided by the present invention.

[0056] Figure 5 This is a data storage flow chart of a DDR chip in the fast demodulation system provided by the present invention.

[0057] Figure 6 The schematic diagram of the arbitration control module and the AXI bus module in the fast demodulation system provided by the invention.

[0058] Figure 7 A flowchart of the steps of the fast demodulation method provided by the present invention. DETAILED DESCRIPTION

[0059] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments, examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0060] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0061] In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0062] In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix", "set" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] Embodiment 1

[0064] like Figure 1 As shown, an OFDR fast demodulation system based on FPGA is used to perform wavelength drift demodulation on an optical frequency domain reflectometer, thereby obtaining a target sensing value of the optical frequency domain reflectometer.

[0065] The optical frequency domain reflectometer is used to measure and sense the target environment, such as Figure 2As shown, it includes a tunable laser TLS, a fiber coupler OC1, an auxiliary interferometer arm, a main interferometer arm, a fiber to be tested FUT and a detector array, wherein the auxiliary interferometer arm includes a fiber circulator CIR1, a fiber coupler OC3, a delay fiber DF, a Faraday rotator reflector FRM1 and a Faraday rotator reflector FRM2, the main interferometer arm includes a fiber coupler OC2, a polarization controller PC, a fiber circulator CIR2, a fiber coupler OC4, a polarization beam splitter PBS1 and a polarization beam splitter PBS2, and the detector array includes a photoelectric balanced detector BPD1, a photoelectric balanced detector BPD2 and a photoelectric balanced detector BPD3; the first port of the fiber coupler OC1 is connected to the emission port of the tunable laser TLS, the second port of the fiber coupler OC1 is connected to the first port of the fiber circulator CIR1, and the third port of the fiber coupler OC1 is connected to the first port of the fiber coupler OC2; the second port of the fiber circulator CIR1 is connected to the first port of the fiber coupler OC3, and the third port of the fiber circulator CIR1 is connected to the first input port of the photoelectric balanced detector BPD1. input port; the second port of the optical fiber coupler OC3 is connected to the second input port of the photoelectric balanced detector BPD1, the third port of the optical fiber coupler OC3 is connected to the Faraday rotator reflector FRM1 via the delay optical fiber DF, and the fourth port of the optical fiber coupler OC3 is connected to the Faraday rotator reflector FRM2; the second port of the optical fiber coupler OC2 is connected to the first port of the optical fiber coupler OC4 via the polarization controller PC, and the third port of the optical fiber coupler OC2 is connected to the first port of the optical fiber circulator CIR2; the second port of the optical fiber circulator CIR2 is connected to one end of the optical fiber to be tested FUT, and the third port of the optical fiber circulator CIR2 is connected to the second port of the optical fiber coupler OC4; the third port of the optical fiber coupler OC4 is connected to the first input ports of the photoelectric balanced detector BPD2 and the photoelectric balanced detector BPD3 respectively via the polarization beam splitter PBS1, and the fourth port of the optical fiber coupler OC4 is connected to the second input ports of the photoelectric balanced detector BPD2 and the photoelectric balanced detector BPD3 respectively via the polarization beam splitter PBS2.

[0066] During measurement and sensing, the swept-frequency light emitted by the tunable laser TLS passes through the optical fiber coupler OC1 and is split at a ratio of 1:99, wherein 1% of the swept-frequency light enters the auxiliary interference arm, and the other 99% of the swept-frequency light enters the main interference arm; the swept-frequency light in the auxiliary interference arm is divided into two beams after passing through the optical fiber circulator CIR1 and the optical fiber coupler OC3, wherein one of the swept-frequency light beams passes through the delay optical fiber DF and reaches the Faraday rotator reflector FRM1, and the other swept-frequency light beam directly reaches the Faraday rotator reflector FRM2, and after being respectively reflected by the Faraday rotator reflector FRM1 and the Faraday rotator reflector FRM2, the two swept-frequency light beams return to the optical fiber coupler OC3 along the original path to generate a first beat-frequency interference light, which is finally input into the photoelectric balance detector BPD1 for optical The electrical signal is converted to form a first beat frequency signal; the swept frequency light in the main interference arm is split by the optical fiber coupler OC2, and one beam of the swept frequency light passes through the polarization controller PC and enters the optical fiber coupler OC4, and the other beam of the swept frequency light passes through the optical fiber circulator CIR2 and enters the optical fiber FUT to be tested, and after forming backscattered light in the optical fiber FUT to be tested, it passes through the optical fiber circulator CIR2 and enters the optical fiber coupler OC4, the backscattered light and the swept frequency light generate a second beat frequency interference light in the optical fiber coupler OC4, the second beat frequency interference light is split by the optical fiber coupler OC4, and then polarized by the first polarization beam splitter and the second polarization beam splitter respectively, and finally input into the photoelectric balance detector BPD1 and the photoelectric balance detector BPD2 for photoelectric signal conversion to form a second beat frequency signal.

[0067] The OFDR fast demodulation system uses the first beat frequency signal as a sampling clock signal, collects the second beat frequency signal, and obtains time domain data of a reference signal and a measurement signal. When the measurement parameters such as temperature and strain in the target environment do not change, the time domain data collected by the OFDR fast demodulation system is the reference signal, and when the measurement parameters such as temperature and strain in the target environment change, the time domain data collected by the OFDR fast demodulation system is the measurement signal.

[0068] like Figure 3As shown, the OFDR fast demodulation system includes an ADC data acquisition circuit board and an FPGA circuit board, wherein the ADC data acquisition circuit board is connected to the FPGA circuit board; the ADC data acquisition circuit board is used to use the first beat frequency signal output by the optical frequency domain reflectometer as a sampling clock signal, collect and perform analog-to-digital conversion on the second beat frequency signal output by the optical frequency domain reflectometer, and obtain time domain data of the reference signal and the measurement signal; the FPGA circuit board is used to perform wavelength drift demodulation on the time domain data of the reference signal and the measurement signal, and obtain the target sensing quantity of the optical frequency domain reflectometer.

[0069] The OFDR fast demodulation system of the present invention adopts the first beat frequency signal of the auxiliary interference arm as the sampling clock signal of the ADC data acquisition circuit board, which can reduce the influence of the nonlinear frequency sweeping light of the tunable laser TLS on the wavelength drift demodulation result; the FPGA circuit board is used for data processing, and a complete OFDR demodulation algorithm based on wavelength drift demodulation is deployed in the FPGA circuit board. Therefore, a single FPGA chip can be used to complete OFDR sensor demodulation without the need for other data processing chips to participate in the data processing of the system, thereby improving the demodulation speed and the system integration.

[0070] In this embodiment, the ADC data acquisition circuit board is connected to the FPGA circuit board via the FMC interface, and uses the JESD204 protocol to transmit data with the FPGA circuit board to reduce the number of interfaces required for the FPGA circuit board, thereby avoiding the impact of different data channels due to different delay problems when transmitting data.

[0071] Preferably, the FPGA circuit board can also be connected to a host computer, and the host computer is used to display the target sensor quantity. It is particularly noted that the host computer of the present invention is only used to provide a software interface to display various types of data generated by the FPGA circuit board during the wavelength drift demodulation process and the target sensor quantity, and does not participate in the data processing during the wavelength drift demodulation process. The data processing during the wavelength drift demodulation process is all completed by the FPGA circuit board.

[0072] In this embodiment, the host computer may be, but is not limited to, a personal computer, which is connected to the FPGA circuit board via a PCIe bus for data transmission.

[0073] like Figure 3-5 As shown, the FPGA circuit board includes an FPGA chip and a DDR chip, the DDR chip includes a first cache block, a second cache block, a third cache block and a fourth cache block, and a first data channel, a second data channel, a third data channel and a fourth data channel arranged in parallel are constructed between the FPGA chip and the DDR chip;

[0074] The FPGA chip writes the time domain data of the reference signal and the measurement signal into the first buffer block of the DDR chip through the first data channel;

[0075] The FPGA chip reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip through the read channel of the first data channel, and then performs column FFT processing on the time domain data of the reference signal and the measurement signal and multiplies them by the rotation factor, and then writes the product data of the reference signal and the measurement signal into the second cache block of the DDR chip through the write channel of the second data channel;

[0076] The FPGA chip reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip through the read channel of the second data channel, and then performs row FFT processing on the product data of the reference signal and the measurement signal, and then writes the distance domain data of the reference signal and the measurement signal into the third cache block and the fourth cache block of the DDR chip through the write channels of the third data channel and the fourth data channel respectively;

[0077] The FPGA chip reads the distance domain data of the reference signal and the measurement signal from the third cache block and the fourth cache block of the DDR chip respectively through the read channels of the third data channel and the fourth data channel, and then performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity.

[0078] The OFDR fast demodulation system of the present invention constructs a multi-channel high-speed parallel data cache and data processing device based on the FPGA chip and the DDR chip, artificially divides the cache space of the DDR chip into four cache blocks, and constructs four data channels. The FPGA chip writes various types of data generated in the wavelength drift demodulation process into different cache blocks for caching through the four data channels, and reads various types of data from different cache blocks for corresponding data processing. The four data channels can work simultaneously to perform data caching and data processing in different algorithm stages of wavelength drift demodulation without affecting each other, thereby greatly improving the data processing speed of wavelength drift demodulation.

[0079] Preferably, the FPGA chip comprises:

[0080] The two-dimensional FFT module is used to perform two-dimensional FFT processing on the reference signal and the measurement signal in the first data channel and the second data channel.

[0081] The two-dimensional FFT module is an extension of the one-dimensional FFT module and can transform two-dimensional data from the time domain to the distance domain for processing.

[0082] When the FPGA chip reads the time domain data of the reference signal and the measurement signal from the first cache block, the time domain data of the reference signal and the measurement signal are respectively converted into two-dimensional data matrices, and then the two-dimensional FFT module is used to perform one-dimensional FFT processing on each column of data in the two-dimensional data matrix of the reference signal and the measurement signal and multiply it by the rotation factor, and then the processed product data is written into the second cache block. Then, when the FPGA chip reads the product data of the reference signal and the measurement signal from the second cache block, the product data of the reference signal and the measurement signal are respectively converted into two-dimensional data matrices, and then the two-dimensional FFT module is used to perform one-dimensional FFT processing on each row of data in the two-dimensional data matrix of the reference signal and the measurement signal to complete the conversion of the reference signal and the measurement signal from the time domain to the distance domain, and finally the distance domain data of the reference signal and the measurement signal are written into the third cache block and the fourth cache block respectively.

[0083] The number of sampling points of the optical frequency domain reflectometer determines the spatial resolution of the sensing system. The present invention uses a two-dimensional FFT algorithm to perform FFT processing on the time domain data of the reference signal and the measurement signal, which can realize FFT of a very large number of points at a relatively low resource cost, thereby ensuring the accuracy of system sensing. In order to realize the two-dimensional FFT algorithm in the FPGA, the present invention divides the cache space of the DDR chip into four cache blocks, and constructs four parallel data channels between the FPGA chip and the DDR chip for data caching and dimensional conversion. The four cache blocks have similar structures, can cache large-point data and realize data dimension conversion, and can realize high-speed parallel data throughput of very large-point data.

[0084] The FPGA chip also includes:

[0085] A windowing and zero-filling module is used to perform windowing and zero-filling processing on the distance domain data of the reference signal and the measurement signal during wavelength drift demodulation;

[0086] An inverse FFT module, used for performing inverse FFT processing on the distance domain data of the reference signal and the measurement signal after the windowing and zero-filling processing during wavelength drift demodulation to obtain the spectrum domain data of the reference signal and the measurement signal;

[0087] A mean filtering module, used for performing mean filtering processing on the spectral domain data of the reference signal and the measurement signal during wavelength drift demodulation;

[0088] A cross-correlation module, used for performing cross-correlation processing on the spectral domain data of the reference signal and the measurement signal after the mean filtering processing during wavelength drift demodulation to obtain a cross-correlation spectrum between the reference signal and the measurement signal;

[0089] A peak detection module, used for performing peak detection on the cross-correlation spectrum between the reference signal and the measurement signal during wavelength drift demodulation to obtain the peak position of the cross-correlation spectrum;

[0090] The drift demodulation module is used to determine the spectral drift amount between the reference signal and the measurement signal according to the peak position during wavelength offset demodulation, and then calculate the target sensing amount.

[0091] After converting the reference signal and measurement information from the time domain to the distance domain, the FPGA chip of the present invention sequentially performs windowing and zero-filling processing, inverse FFT processing, mean filtering processing, cross-correlation processing and peak detection on the reference signal and the measurement information, and finally determines the spectral drift amount between the reference signal and the measurement signal, wherein the spectral drift amount is the difference (frequency) between the horizontal coordinate of the peak position in the cross-correlation spectrum and the median, and then substitutes the spectral drift amount into the drift amount-sensing amount correlation curve to solve and obtain the target sensing amount corresponding to the spectral drift amount.

[0092] The drift-sensing quantity correlation curve can be obtained by curve fitting in advance through a large amount of drift quantity data and sensing quantity data.

[0093] like Figure 6 As shown, the FPGA chip also includes an arbitration control module and an AXI bus module, the arbitration control module includes a write arbitration controller and a read arbitration controller, the AXI bus module includes an AXI write data bus and an AXI read data bus, wherein

[0094] The write arbitration controller is used to identify the source channels of various types of data of the reference signal and the measurement signal, and generate write target addresses for various types of data according to the source channels;

[0095] The AXI write data bus is used to write various types of data of the reference signal and the measurement signal into a cache block corresponding to the write target address through the AXI4 data transmission protocol;

[0096] The read arbitration controller is used to identify a request channel of a data read instruction and generate a read target address according to the request channel;

[0097] The AXI read data bus is used to read various types of data of the reference signal and the measurement signal from the cache block corresponding to the read target address through the AXI4 data transmission protocol.

[0098] When the FPGA chip writes data into the DDR chip or reads data from the DDR chip, the arbitration control module and the AXI bus module are used to perform data reading and writing processing.

[0099] For example, when the FPGA chip needs to write the time domain data of the reference signal and the measurement signal into the first cache block, the FPGA chip sends the time domain data to the write arbitration controller. After the write arbitration controller recognizes that the time domain data comes from the first data channel, it generates a write target address corresponding to the first cache block for the time domain data, and puts the time domain data and the write target address into the FIFO cache area between the AXI write data bus. Then the AXI write data bus obtains the time domain data and the write target address from the FIFO cache area, and writes the time domain data into the first cache block through the memory management module of the FPGA chip according to the write target address.

[0100] For another example, when the FPGA chip needs to read the time domain data of the reference signal and the measurement signal from the first cache block, the FPGA chip first sends a data read instruction to the read arbitration controller, in which the first data channel is written. After receiving the data read instruction, the read arbitration controller generates a read target address corresponding to the first cache block, and then puts the first data channel and the read target address into the FIFO cache area between the AXI read data bus in the format of [channel:addr]. Then, the AXI read data bus obtains the first data channel and the read target address from the FIFO cache area, and reads the corresponding time domain data from the first cache block through the memory management module of the FPGA chip according to the read target address, and then puts the first data channel and the time domain data into the FIFO cache area between the read arbitration controller in the format of [channel:data]. Then, the read arbitration controller obtains the first data channel and the time domain data from the FIFO cache area, and provides the time domain data to the first data channel.

[0101] The FPGA chip also uses the above method when reading and writing data in other cache blocks.

[0102] Preferably, the read arbitration controller includes an address transformation module. When the read arbitration controller reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a column-first manner and then read the time domain data; when the read arbitration controller reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a row-first manner and then read the product data.

[0103] Specifically, assuming that there are 16 time domain data of the reference signal, namely 1, 2, 3, 6, 5 ... 13, 14, 15, 16, and these 16 data need to be converted into a 4*4 two-dimensional data matrix, then the write arbitration controller continuously allocates addresses to write these 16 time domain data into the first cache block in the processing order, and the corresponding relationship between the data and the address is as follows:

[0104] address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

[0105] When the read arbitration controller reads the 16 data from the first cache block after transforming the read target address in a column-first manner, the data is read once every N (the number of columns of the two-dimensional data matrix) addresses, which are 1, 5, 9, 13...4, 8, 12, 16 in sequence, which is equivalent to the two-dimensional data matrix shown below:

[0106]

[0107] Then the two-dimensional FFT module performs one-dimensional FFT processing on the 16 data read from the first cache block and multiplies them by the rotation factor, and the obtained product data are 1', 5', 9', 13'...4', 8', 12', 16' in sequence.

[0108] Next, the write arbitration controller writes the product data into the second cache block by continuously allocating addresses according to the processing order, and the corresponding relationship between the data and the address is as follows:

[0109] address 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data 1' 5' 9' 13' 2' 6' 10' 14' 3' 7' 11' 15' 4' 8' 12' 16'

[0110] When the read arbitration controller reads the 16 data from the second cache block after transforming the read target address in a row-first manner, data is read once every M (the number of rows of the two-dimensional data matrix) addresses, which are 1', 2', 3', 4'... 13', 14', 15', 16', which is equivalent to the two-dimensional data matrix shown below:

[0111]

[0112] Then the two-dimensional FFT module performs one-dimensional FFT processing on the 16 data read from the second buffer block, and the obtained distance domain data are 1", 2", 3", 4"...13", 14", 15", 16" in sequence.

[0113] Finally, the write arbitration controller continuously allocates addresses to write the distance domain data into the third cache block in the processing order, and the corresponding relationship between the data and the address is as follows:

[0114] address 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 data 1” 2” 3” 4” 5” 6” 7” 8” 9” 10” 11” 12” 13” 14” 15” 16”

[0115] The time domain data of the measurement signal is also processed and transformed using the above method and finally written into the fourth cache block.

[0116] Embodiment 2

[0117] like Figure 7 As shown, an OFDR fast demodulation method based on FPGA is applied to the OFDR fast demodulation system described in Example 1; the steps of the OFDR fast demodulation method are as follows:

[0118] Step 100: the FPGA chip writes the time domain data of the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel;

[0119] Step 200: the FPGA chip reads the time domain data of the reference signal from the first cache block of the DDR chip through the read channel of the first data channel, then performs column FFT processing on the time domain data of the reference signal and multiplies it by the rotation factor, and then writes the product data of the reference signal into the second cache block of the DDR chip through the write channel of the second data channel;

[0120] Step 300: the FPGA chip reads the product data of the reference signal from the second cache block of the DDR chip through the read channel of the second data channel, performs row FFT processing on the product data of the reference signal, and then writes the distance domain data of the reference signal into the third cache block of the DDR chip through the write channel of the third data channel;

[0121] Step 400: the FPGA chip writes the time domain data of the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel;

[0122] Step 500: the FPGA chip reads the time domain data of the measurement signal from the first cache block of the DDR chip through the read channel of the first data channel, then performs column FFT processing on the data of the measurement signal and multiplies it by a rotation factor, and then writes the product data of the measurement signal into the second cache block of the DDR chip;

[0123] Step 600: the FPGA chip reads the product data of the measurement signal from the second cache block of the DDR chip through the read channel of the second data channel, performs row FFT processing on the product data of the measurement signal, and writes the distance domain data of the measurement signal into the fourth cache block of the DDR chip;

[0124] Step 700: The FPGA chip reads the distance domain data of the reference signal and the measurement signal from the third cache block and the fourth cache block of the DDR chip through the read channels of the third data channel and the fourth data channel, respectively, and then performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing value.

[0125] In step 200 and step 300 and step 500 and step 600, the FPGA chip uses a two-dimensional FFT module to perform two-dimensional FFT processing on the reference signal and the measurement signal in the first data channel and the second data channel respectively.

[0126] In step 700, the FPGA chip performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity in the following steps:

[0127] Step 710: the FPGA chip uses a windowing and zero-filling module to perform windowing and zero-filling processing on the distance domain data of the reference signal and the measurement signal;

[0128] Step 720: the FPGA chip uses an inverse FFT module to perform inverse FFT processing on the distance domain data of the reference signal and the measurement signal that have undergone windowing and zero-filling processing to obtain spectrum domain data of the reference signal and the measurement signal;

[0129] Step 730: the FPGA chip uses a mean filter module to perform mean filtering on the spectral domain data of the reference signal and the measurement signal;

[0130] Step 740: the FPGA chip uses a cross-correlation module to perform cross-correlation processing on the spectral domain data of the reference signal and the measurement signal after the mean filtering process, to obtain a cross-correlation spectrum between the reference signal and the measurement signal;

[0131] Step 750: The FPGA chip uses a peak detection module to perform peak detection on the cross-correlation spectrum between the reference signal and the measurement signal to obtain the peak position of the cross-correlation spectrum;

[0132] Step 760: The FPGA chip uses a drift demodulation module to determine the spectral drift between the reference signal and the measurement signal according to the peak position, and then calculates the target sensing value.

[0133] The steps of the FPGA chip writing the reference signal and various data of the measurement parameters into the DDR chip are as follows:

[0134] The FPGA chip uses a write arbitration controller to identify source channels of various types of data of the reference signal and the measurement signal, and generates write target addresses for various types of data according to the source channels;

[0135] The FPGA chip uses the AXI write data bus to write various data of the reference signal and the measurement signal into the cache block corresponding to the write target address through the AXI4 data transmission protocol;

[0136] The steps of the FPGA chip reading various data of the reference signal and measurement parameters from the DDR chip are as follows:

[0137] The FPGA chip uses a read arbitration controller to identify a request channel for a data read instruction, and generates a read target address according to the request channel;

[0138] The FPGA chip uses an AXI read data bus to read various types of data of the reference signal and the measurement signal from a cache block corresponding to the read target address through an AXI4 data transmission protocol.

[0139] The read arbitration controller includes an address transformation module. When the read arbitration controller reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a column-first manner and then read the time domain data; when the read arbitration controller reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a row-first manner and then read the product data.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention rather than to limit them. Although the embodiments of the present invention have been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the embodiments of the present invention can still be modified or replaced by equivalents, and these modifications or equivalent replacements cannot cause the modified technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An OFDR fast demodulation system based on FPGA, characterized in that: It comprises an FPGA chip and a DDR chip, wherein the DDR chip comprises a first cache block, a second cache block, a third cache block and a fourth cache block, and a first data channel, a second data channel, a third data channel and a fourth data channel arranged in parallel are constructed between the FPGA chip and the DDR chip; The FPGA chip writes the time domain data of the reference signal and the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel; The FPGA chip reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip through the read channel of the first data channel, and then performs column FFT processing on the time domain data of the reference signal and the measurement signal and multiplies them by the rotation factor, and then writes the product data of the reference signal and the measurement signal into the second cache block of the DDR chip through the write channel of the second data channel; The FPGA chip reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip through the read channel of the second data channel, and then performs row FFT processing on the product data of the reference signal and the measurement signal, and then writes the distance domain data of the reference signal and the measurement signal into the third cache block and the fourth cache block of the DDR chip through the write channels of the third data channel and the fourth data channel respectively; The FPGA chip reads the distance domain data of the reference signal and the measurement signal from the third cache block and the fourth cache block of the DDR chip respectively through the read channels of the third data channel and the fourth data channel, and then performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity.

2. The OFDR fast demodulation system according to claim 1, characterized in that: The FPGA chip comprises: The two-dimensional FFT module is used to perform two-dimensional FFT processing on the reference signal and the measurement signal in the first data channel and the second data channel.

3. The OFDR fast demodulation system according to claim 1 or 2, characterized in that: The FPGA chip also includes: A windowing and zero-filling module is used to perform windowing and zero-filling processing on the distance domain data of the reference signal and the measurement signal during wavelength drift demodulation; An inverse FFT module, used for performing inverse FFT processing on the distance domain data of the reference signal and the measurement signal after the windowing and zero-filling processing during wavelength drift demodulation to obtain the spectrum domain data of the reference signal and the measurement signal; A mean filtering module, used for performing mean filtering processing on the spectral domain data of the reference signal and the measurement signal during wavelength drift demodulation; A cross-correlation module, used for performing cross-correlation processing on the spectral domain data of the reference signal and the measurement signal after the mean filtering processing during wavelength drift demodulation to obtain a cross-correlation spectrum between the reference signal and the measurement signal; A peak detection module, used for performing peak detection on the cross-correlation spectrum between the reference signal and the measurement signal during wavelength drift demodulation to obtain the peak position of the cross-correlation spectrum; The drift demodulation module is used to determine the spectral drift amount between the reference signal and the measurement signal according to the peak position during wavelength offset demodulation, and then calculate the target sensing amount.

4. The OFDR fast demodulation system according to claim 1, characterized in that: The FPGA chip also includes an arbitration control module and an AXI bus module. The arbitration control module includes a write arbitration controller and a read arbitration controller. The AXI bus module includes an AXI write data bus and an AXI read data bus. The write arbitration controller is used to identify the source channels of various types of data of the reference signal and the measurement signal, and generate write target addresses for various types of data according to the source channels; The AXI write data bus is used to write various types of data of the reference signal and the measurement signal into a cache block corresponding to the write target address through the AXI4 data transmission protocol; The read arbitration controller is used to identify a request channel of a data read instruction and generate a read target address according to the request channel; The AXI read data bus is used to read various types of data of the reference signal and the measurement signal from the cache block corresponding to the read target address through the AXI4 data transmission protocol.

5. The OFDR fast demodulation system according to claim 4, characterized in that: The read arbitration controller includes an address transformation module. When the read arbitration controller reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a column-first manner and then read the time domain data; when the read arbitration controller reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a row-first manner and then read the product data.

6. An OFDR fast demodulation method based on FPGA, characterized in that: Applicable to the OFDR fast demodulation system of claim 1; the steps of the OFDR fast demodulation method are as follows: Step 100: the FPGA chip writes the time domain data of the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel; Step 200: the FPGA chip reads the time domain data of the reference signal from the first cache block of the DDR chip through the read channel of the first data channel, then performs column FFT processing on the time domain data of the reference signal and multiplies it by the rotation factor, and then writes the product data of the reference signal into the second cache block of the DDR chip through the write channel of the second data channel; Step 300: the FPGA chip reads the product data of the reference signal from the second cache block of the DDR chip through the read channel of the second data channel, performs row FFT processing on the product data of the reference signal, and then writes the distance domain data of the reference signal into the third cache block of the DDR chip through the write channel of the third data channel; Step 400: the FPGA chip writes the time domain data of the measurement signal into the first buffer block of the DDR chip through the write channel of the first data channel; Step 500: the FPGA chip reads the time domain data of the measurement signal from the first cache block of the DDR chip through the read channel of the first data channel, then performs column FFT processing on the data of the measurement signal and multiplies it by a rotation factor, and then writes the product data of the measurement signal into the second cache block of the DDR chip; Step 600: the FPGA chip reads the product data of the measurement signal from the second cache block of the DDR chip through the read channel of the second data channel, performs row FFT processing on the product data of the measurement signal, and writes the distance domain data of the measurement signal into the fourth cache block of the DDR chip; Step 700: The FPGA chip reads the distance domain data of the reference signal and the measurement signal from the third cache block and the fourth cache block of the DDR chip through the read channels of the third data channel and the fourth data channel, respectively, and then performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing value.

7. The OFDR fast demodulation method according to claim 6, characterized in that: In step 200 and step 300 and step 500 and step 600, the FPGA chip uses a two-dimensional FFT module to perform two-dimensional FFT processing on the reference signal and the measurement signal in the first data channel and the second data channel respectively.

8. The OFDR fast demodulation method according to claim 6 or 7, characterized in that: In step 700, the FPGA chip performs wavelength drift demodulation on the distance domain data of the reference signal and the measurement signal to obtain the target sensing quantity in the following steps: Step 710: the FPGA chip uses a windowing and zero-filling module to perform windowing and zero-filling processing on the distance domain data of the reference signal and the measurement signal; Step 720: the FPGA chip uses an inverse FFT module to perform inverse FFT processing on the distance domain data of the reference signal and the measurement signal that have undergone windowing and zero-filling processing to obtain spectrum domain data of the reference signal and the measurement signal; Step 730: the FPGA chip uses a mean filter module to perform mean filtering on the spectral domain data of the reference signal and the measurement signal; Step 740: the FPGA chip uses a cross-correlation module to perform cross-correlation processing on the spectral domain data of the reference signal and the measurement signal after the mean filtering process, to obtain a cross-correlation spectrum between the reference signal and the measurement signal; Step 750: The FPGA chip uses a peak detection module to perform peak detection on the cross-correlation spectrum between the reference signal and the measurement signal to obtain the peak position of the cross-correlation spectrum; Step 760: The FPGA chip uses a drift demodulation module to determine the spectral drift between the reference signal and the measurement signal according to the peak position, and then calculates the target sensing value.

9. The OFDR fast demodulation method according to claim 6, characterized in that: The steps of the FPGA chip writing the reference signal and various data of the measurement parameters into the DDR chip are as follows: The FPGA chip uses a write arbitration controller to identify source channels of various types of data of the reference signal and the measurement signal, and generates write target addresses for various types of data according to the source channels; The FPGA chip uses the AXI write data bus to write various data of the reference signal and the measurement signal into the cache block corresponding to the write target address through the AXI4 data transmission protocol; The steps of the FPGA chip reading various data of the reference signal and measurement parameters from the DDR chip are as follows: The FPGA chip uses a read arbitration controller to identify a request channel for a data read instruction, and generates a read target address according to the request channel; The FPGA chip uses an AXI read data bus to read various types of data of the reference signal and the measurement signal from a cache block corresponding to the read target address through an AXI4 data transmission protocol.

10. The OFDR fast demodulation method according to claim 9, characterized in that: The read arbitration controller includes an address transformation module. When the read arbitration controller reads the time domain data of the reference signal and the measurement signal from the first cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a column-first manner and then read the time domain data; when the read arbitration controller reads the product data of the reference signal and the measurement signal from the second cache block of the DDR chip, the address transformation module controls the read arbitration controller to transform the read target address in a row-first manner and then read the product data.

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