Transposition operation processing device, method and artificial intelligence chip

Abstract

The present disclosure provides a processing device, method and artificial intelligence chip for transposition operation, which relates to the field of artificial intelligence technology. The processing device for transposition operation includes K groups of registers, the kth group of registers includes M registers, and each register includes N storage units. The i-th register in the kth group of registers is configured to receive the i-th row element of the kth matrix to be transposed, and store the j-th element in the i-th row element in the j-th storage unit of the i-th register in the kth group of registers, the kth matrix to be transposed is an M×N matrix, and the N elements in the i-th row element are arranged in sequence from 1 to N; the M registers in the kth group of registers are configured to output the N column elements of the kth matrix to be transposed in sequence from 1 to N or from N to 1, and the j-th column element includes the j-th element in the j-th storage unit of each register in the kth group of registers.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to a processing device and method for a transposition operation and an artificial intelligence chip. Background Art

[0002] The transpose operation is a common operation in neural network algorithms, that is, swapping the rows and columns of a matrix to rearrange the elements in the matrix in preparation for subsequent operations. For example, in a matrix multiplication operation, a matrix is ​​transposed and then multiplied and added with another matrix to obtain the matrix multiplication result.

[0003] In the related art, a central processing unit (CPU) is usually used to move the elements in the matrix to be transposed one by one to complete the transposition. For example, the CPU reads the elements in the matrix to be transposed one by one from the memory area A in the row direction, then calculates the storage address of each element after transposition, and writes the elements one by one into the memory area B in the row direction according to the calculated storage address. Summary of the invention

[0004] The inventors noticed that, under the method in the related art, the CPU is required to frequently perform memory access and address calculation to read and write elements one by one, resulting in low processing efficiency of the transposition operation.

[0005] In order to solve the above problems, the embodiments of the present disclosure provide the following technical solutions.

[0006] According to one aspect of an embodiment of the present disclosure, a processing device for a transposition operation is provided, comprising: K groups of registers, the kth group of registers comprising M registers, each register comprising N storage units, N≥2, M≥2, K≥1, 1≤k≤K, wherein: the i-th register in the k-th group of registers is configured to receive the i-th row element of the k-th matrix to be transposed, and store the j-th element of the i-th row element of the k-th matrix to be transposed in the j-th storage unit of the i-th register in the k-th group of registers, the k-th matrix to be transposed is an M×N matrix, the N elements of the i-th row element of the k-th matrix to be transposed are arranged in sequence from 1 to N, 1≤i≤M, 1≤j≤N; the M registers in the k-th group of registers are configured to output the N column elements of the k-th matrix to be transposed in sequence from 1 to N or from N to 1, and the j-th column element of the k-th matrix to be transposed includes the j-th element in the j-th storage unit of each register in the k-th group of registers.

[0007] In some embodiments, each register includes N input terminals, and the processing device also includes: K first multiplexers, the kth first multiplexer is connected to the N input terminals of each register in the kth group of registers, and is configured to respond to a first signal representing i, and transmit the jth element of the i-th row element of the received k-th matrix to be transposed to the j-th storage unit of the i-th register of the k-th group of registers through the j-th input terminal of the i-th register of the k-th group of registers.

[0008] In some embodiments, the processing device further comprises: a first counter connected to the K first demultiplexers and configured to send a first signal representing i when the processing device receives the i-th row element of the k-th matrix to be transposed.

[0009] In some embodiments, K≥2, the processing device also includes: a second multiplexer, connected to the K first multiplexers, and configured to transmit the i-th row element of the received k-th transposed matrix to the k-th first multiplexer in response to a first indication signal corresponding to the k-th first multiplexer.

[0010] In some embodiments, the processing device also includes: a second counter, which is connected to the K first multiplexers and is configured to send a first flag signal corresponding to the kth matrix to be transposed when the second multiplexer receives the i-th row element of the kth matrix to be transposed; a first controller, which is connected to the second counter and the second multiplexer and is configured to send a first indication signal corresponding to the kth first multiplexer to the second multiplexer in response to the first flag signal corresponding to the kth matrix to be transposed.

[0011] In some embodiments, each register includes N output terminals corresponding one-to-one to the N storage units of the register, the kth group of registers includes N groups of output terminals, and the jth group of output terminals includes the jth output terminal corresponding to the jth storage unit of each register in the kth group of registers; the processing device also includes: K first multiplexers, the kth first multiplexer is connected to the N groups of output terminals of the kth group of registers, and is configured to output the jth column element of the kth matrix to be transposed output by the jth group of output terminals of the kth group of registers in response to a second signal representing j.

[0012] In some embodiments, the processing device also includes: a third counter, connected to the K first multiplexers, and configured to output a second signal representing j in sequence from 1 to N or from N to 1 when the kth group of registers has received M rows of elements of the kth matrix to be transposed.

[0013] In some embodiments, the processing device also includes: a second controller, configured to output a first control signal when the kth group of registers has received M rows of elements of the kth matrix to be transposed; wherein the third counter is also connected to the second controller and configured to output a second signal representing j in sequence from 1 to N or from N to 1 in response to the first control signal.

[0014] In some embodiments, the second controller is also configured to output a second control signal when the third counter outputs a second signal representing N in a sequence from 1 to N or outputs a second signal representing 1 in a sequence from N to 1; the third counter is also configured to stop outputting the second signal representing j in response to the second control signal.

[0015] In some embodiments, each register includes N input terminals, and the processing device also includes: K first multiplexers, the kth first multiplexer is connected to the N input terminals of each register in the kth group of registers, and is configured to respond to the first signal representing i, and transmit the jth element of the i-th row element of the kth matrix to be transposed to the j-th storage unit of the i-th register of the k-th group of registers through the j-th input terminal of the i-th group of input terminals of the k-th group of registers; a first counter is connected to the K first multiplexers and is configured to send a first signal representing i when the processing device receives the i-th row element of the k-th matrix to be transposed; wherein the second controller is connected to the first counter and is configured to output the first control signal in response to the first signal representing M from the first counter.

[0016] In some embodiments, K≥2, the processing device also includes: a second multiplexer, connected to all of the K first multiplexers, and configured to select the j-th column element output of the k-th matrix to be transposed from the k-th first multiplexer in response to a second indication signal corresponding to the k-th first multiplexer.

[0017] In some embodiments, the processing device also includes: a fourth counter, which is connected to all of the K first multiplexers and is configured to send a second flag signal corresponding to the kth matrix to be transposed when the kth group of registers has received M rows of elements of the kth matrix to be transposed; a third controller, which is connected to all of the fourth counter and the second multiplexer and is configured to send a second indication signal corresponding to the kth first multiplexer to the second multiplexer in response to the second flag signal corresponding to the kth matrix to be transposed.

[0018] In some embodiments, the K group of registers includes an mth group of registers and an nth group of registers, the time when the mth group of registers receives the M row elements of the mth matrix to be transposed at least partially overlaps with the time when the nth group of registers outputs the N column elements of the nth matrix to be transposed, 1≤m≤K, 1≤n≤K, m and n are different.

[0019] In some embodiments, the kth matrix to be transposed is obtained by dividing the original matrix in the neural network algorithm, and the division makes the number of rows of the original matrix an integer multiple of the number of rows of the kth matrix to be transposed, and the number of columns of the original matrix is ​​an integer multiple of the number of columns of the kth matrix to be transposed.

[0020] According to another aspect of the embodiments of the present disclosure, there is provided an artificial intelligence chip, comprising: a processing device as described in any one of the above embodiments.

[0021] In some embodiments, the chip also includes: a first storage device, configured to receive the j-th column element of the k-th matrix to be transposed from the processing device, and store the j-th column element of the k-th matrix to be transposed as the j-th row element of the k-th transposed matrix in a first memory of the first storage device.

[0022] In some embodiments, the chip further includes: a second storage device configured to read M row elements of the kth matrix to be transposed row by row from a second memory of the second storage device, and transmit the M row elements of the kth matrix to be transposed row by row to the processing device.

[0023] According to another aspect of the embodiments of the present disclosure, there is provided an accelerator, comprising: the chip described in any one of the above embodiments.

[0024] According to another aspect of an embodiment of the present disclosure, a method for processing a transposition operation is provided, comprising: an i-th register in a k-th group of registers of K groups of registers receives an i-th row element of a k-th matrix to be transposed, and stores a j-th element of the i-th row element of the k-th matrix to be transposed in a j-th storage unit of the i-th register in the k-th group of registers, wherein the k-th group of registers includes M registers, each register includes N storage units, the k-th matrix to be transposed is an M×N matrix, and the N elements of the i-th row element of the k-th matrix to be transposed are arranged in sequence from 1 to N, N≥2, M≥2, K≥1, 1≤i≤M, 1≤j≤N, 1≤k≤K; and the M registers in the k-th group of registers sequentially output N column elements of the k-th matrix to be transposed in sequence from 1 to N or from N to 1, wherein the j-th column element of the k-th matrix to be transposed includes the j-th element in the j-th storage unit of each register in the k-th group of registers.

[0025] The transposition operation processing device provided by the embodiment of the present disclosure can store the M row elements in the kth matrix to be transposed one by one through the M registers in the kth group of registers, and can output the N column elements in the kth matrix to be transposed in sequence, so that the N column elements in the kth matrix to be transposed can be stored as the N row elements of the kth matrix after transposition when storing in the row direction later, thereby realizing the transposition operation of the matrix. In this way, on the one hand, there is no need for the CPU to participate in the transposition operation of the matrix, which reduces the CPU's working time and resource occupation and improves resource utilization; on the other hand, the transposition operation processing device can receive and store multiple rows of elements in the matrix to be transposed in units of rows, and can output multiple columns of elements in the matrix to be transposed in units of columns. Compared with the method of carrying elements one by one, the number of accesses to the memory is reduced, thereby improving the processing efficiency of the transposition operation.

[0026] Other features, aspects and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings constitute a part of this specification, and illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0028] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0029] Figure 1 is a structural schematic diagram of a processing device for transposition operation according to some embodiments of the present disclosure;

[0030] Figure 2 is a schematic diagram of a matrix to be transposed according to some embodiments of the present disclosure;

[0031] Figure 3 is a structural schematic diagram of a processing device for transposition operation according to other embodiments of the present disclosure;

[0032] Figure 4 is a structural schematic diagram of a processing device for transposition operation according to some other embodiments of the present disclosure;

[0033] Figure 5 is a schematic diagram of an original matrix according to some embodiments of the present disclosure;

[0034] Figure 6 It is a schematic diagram of the structure of an artificial intelligence chip according to some embodiments of the present disclosure.

[0035] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0036] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0037] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0039] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0040] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0041] Figure 1 is a structural diagram of a processing device for transposition operation according to some embodiments of the present disclosure.

[0042] like Figure 1As shown, the processing device 100 includes K groups of registers 110 , each group of registers includes M registers 111 , each register 111 includes N storage units 112 , N≥2, M≥2, K≥1, 1≤k≤K. Figure 1 A register set 110 including three registers 111 is schematically shown, and each register 111 includes four storage units 112 .

[0043] The i-th register 111 in the k-th group of registers 110 may be configured to receive the i-th row elements of the k-th matrix to be transposed, and store the j-th element of the i-th row elements of the k-th matrix to be transposed in the j-th storage unit 112 of the i-th register 111 in the k-th group of registers 110 .

[0044] Here, the kth matrix to be transposed is a matrix of M (rows) × N (columns), and the N elements in the i-th row of the kth matrix to be transposed are arranged in order from 1 to N, 1≤i≤M, 1≤j≤N. It should be understood that M, N, K, i, j and k are all integers. For example, the N elements in the i-th row are arranged in order from left to right or from right to left as the 1st, 2nd ... Nth elements.

[0045] It should also be understood that the processing device 100 may include more groups of registers 110 in addition to the K groups of registers 110 for processing the K matrices to be transposed.

[0046] It should also be understood that the N elements in the i-th row of the k-th matrix to be transposed are stored in the N storage units 112 of the i-th register 111 in the k-th group of registers 110 in a one-to-one correspondence.

[0047] Figure 2 is a schematic diagram of a matrix to be transposed according to some embodiments of the present disclosure.

[0048] like Figure 2 As shown, the matrix 20 to be transposed is a 3×4 matrix. The three row elements of the matrix 20 to be transposed can be stored in a one-to-one correspondence. Figure 1 In the three registers 111 shown, the four elements in each row of elements can be stored in the four storage units 112 of the corresponding registers 111 in a one-to-one correspondence. For example, the first to fourth storage units 112 of the first register 111 can store the four elements of the first row of elements {0, 1, 2, 3} in a one-to-one correspondence, the first to fourth storage units 112 of the second register 111 can store the four elements of the second row of elements {8, 9, 10, 11} in a one-to-one correspondence, and the first to fourth storage units 112 of the third register 111 can store the four elements of the third row of elements {16, 17, 18, 19} in a one-to-one correspondence.

[0049] In some embodiments, each register 111 may use bytes as storage units, and the capacity of each storage unit 112 may be 1 byte or multiple bytes. For example, a 64-byte register 111 may include 64 storage units 112, and the capacity of each storage unit 112 is 1 byte.

[0050] In some embodiments, the number of registers 111 in different groups of registers 110 may be the same or different, and the number of storage units 112 in different registers 111 may be the same or different, that is, the processing device 100 may receive and store matrices to be transposed of the same or different sizes. For example, the first group of registers 110 includes 3 registers 111, and each register 111 includes 4 storage units 112, then the first group of registers 110 may receive and store the first matrices to be transposed of sizes of 3×4, 3×3, 3×2, etc.; the second group of registers 110 includes 4 registers 111, and each register 111 includes 3 storage units 112, then the second group of registers 110 may receive and store the second matrices to be transposed of sizes of 4×3, 4×2, 3×3, etc.

[0051] In some embodiments, the number of registers 111 in the same group of registers 110 may be the same as the number of storage units 112 in the registers 111, that is, M may be equal to N. For example, the first group of registers 110 includes three registers 111, and each register 111 includes three storage units 112, then the first group of registers 110 may receive and store the first matrix to be transposed of sizes such as 3×3 and 2×2.

[0052] In other embodiments, the number of registers 111 in the same register group 110 and the number of storage units 112 in the registers 111 may be different, that is, M and N may be different. For example, considering that more resources are required for hardware implementation when the number of registers is greater, M may be smaller than N to facilitate hardware implementation of the processing device 100.

[0053] The M registers 111 in the k-th group of registers 110 may be configured to sequentially output N column elements of the k-th matrix to be transposed in an order from 1 to N or from N to 1.

[0054] Here, the j-th column element of the k-th matrix to be transposed includes the j-th element in the j-th storage unit 112 of each register 111 in the k-th group of registers 110 .

[0055] For example, please refer to Figure 2, the three registers 111 can sequentially output the 4 columns of elements of the matrix 20 to be transposed in the order of the 1st to the 4th, and the jth column element includes the jth element in the jth storage unit 112 of each register 111, that is, the three registers 111 can sequentially output the 4 columns of elements {0, 8, 16}, {1, 9, 17}, {2, 10, 18} and {3, 11, 19}. It should be understood that the manner in which the three registers 111 sequentially output the 4 columns of elements of the matrix 20 to be transposed in the order from the 4th to the 1st is similar to this, and will not be repeated here.

[0056] In the above embodiment, the processing device for the transposition operation can store the M row elements in the kth matrix to be transposed in a one-to-one correspondence through the M registers in the kth group of registers, and can output the N column elements in the kth matrix to be transposed in sequence, so that when storing in the row direction later, the N column elements in the kth matrix to be transposed can be stored as the N row elements of the kth matrix after transposition, thereby realizing the transposition operation of the matrix. In this way, on the one hand, there is no need for the CPU to participate in the transposition operation of the matrix, which reduces the CPU's working time and resource occupation and improves resource utilization; on the other hand, the processing device for the transposition operation can receive and store multiple rows of elements in the matrix to be transposed in units of rows, and can output multiple columns of elements in the matrix to be transposed in units of columns. Compared with the method of carrying elements one by one, the number of accesses to the memory is reduced, thereby improving the processing efficiency of the transposition operation.

[0057] Figure 3 It is a structural schematic diagram of a processing device for transposition operation according to other embodiments of the present disclosure.

[0058] like Figure 3 As shown, each register 111 may include N input terminals. The processing device 100 may further include K first demultiplexers 120. The K first demultiplexers 120 are connected to the K groups of registers 110 in a one-to-one correspondence. Figure 3 A group of registers 110 and a first demultiplexer 120 are schematically shown. The group of registers 110 includes three registers 111 . Each register 111 includes two storage units 112 and two input terminals 1121 a and 1121 b corresponding to the two storage units 112 .

[0059] The k-th first demultiplexer 120 may be connected to the N input terminals of each register 111 in the k-th group of registers 110 .

[0060] For example, Figure 3 As shown, the first demultiplexer 120 may include three output terminals connected to the three registers 111 in one-to-one correspondence, and each output terminal is connected to both the input terminal 1121 a and the input terminal 1121 b of the corresponding register 111 .

[0061] It should be understood that the K groups of registers 110 can receive and store the K matrices to be transposed in a one-to-one correspondence through the K first demultiplexers 120. The kth first demultiplexer 120 can directly receive the kth matrix to be transposed, or the kth first demultiplexer 120 can receive the kth matrix to be transposed through other components. This will be further described later.

[0062] It should also be understood that the kth group of registers 110 may include M groups of input terminals, and the i-th group of input terminals may include N input terminals of the i-th register 111 in the kth group of registers 110. The kth first demultiplexer 120 may include M output terminals connected one-to-one with the M groups of input terminals of the kth group of registers 110. The kth first demultiplexer 120 may transmit the received M row elements of the kth matrix to be transposed to the M registers 111 of the kth group of registers 110 through the M output terminals one-to-one.

[0063] The kth first multiplexer 120 can be configured to transmit the jth element of the i-th row elements of the received kth matrix to be transposed to the j-th storage unit 112 of the i-th register 111 of the k-th group of registers 110 through the j-th input terminal of the i-th register 111 of the k-th group of registers 110 in response to the first signal representing i.

[0064] For example, if the first row of elements of the matrix to be transposed received by the first demultiplexer 120 includes two elements, the first demultiplexer 120 may transmit the first element of the first row of elements of the matrix to be transposed received to the first storage unit 112 of the first register 111 through the first input terminal 1121a in the first register 111 in response to the first signal indicating 1, and transmit the second element of the first row of elements of the matrix to be transposed received to the second storage unit 112 of the first register 111 through the second input terminal 1121b in the first register 111. That is, the first demultiplexer 120 may transmit the two elements of the first row of elements to the two storage units 112 of the first register 111 through the first group of input terminals (the two input terminals 1121a and 1121b of the first register 111 in the first group of registers 110) in response to the first signal indicating 1.

[0065] It should be understood that the kth first demultiplexer 120 can transmit the N elements in the i-th row of elements to the N storage units 112 of the i-th register in one-to-one correspondence through the i-th group input terminal of the k-th group register 110 (i.e., the N input terminals of the i-th register 111 in the k-th group register 110) in response to the first signal representing i. For example, the input terminal of the kth first demultiplexer 120 can input the N elements in the i-th row of elements of the matrix to be transposed at one time, and transmit the N elements in the i-th row of elements of the k-th matrix to be transposed to the N storage units 112 of the i-th register in one-to-one correspondence through the N input terminals of the i-th register 111 according to the first signal representing i.

[0066] In the above embodiment, the kth first demultiplexer is connected to the N input terminals of each register in the kth group of registers, and can distribute the M rows of elements of the kth matrix to be transposed and the N elements in each row according to the signal representing i. In this way, it can not only ensure that the M rows of elements of the kth matrix to be transposed can be transmitted one-to-one to the M registers of the kth group of registers, but also ensure that the N elements in the i-th row of elements of the kth matrix to be transposed can be transmitted one-to-one to the N storage units of the i-th register of the kth group of registers, thereby improving the reliability of the transposition operation.

[0067] Figure 4 is a structural schematic diagram of a processing device for transposition operation according to some other embodiments of the present disclosure.

[0068] like Figure 4 As shown, Figure 4 Two groups of registers 110 and two first demultiplexers 120 connected to the two groups of registers 110 in a one-to-one correspondence are schematically shown. Each group of registers 110 includes three registers 111.

[0069] In some embodiments, the processing device 100 may further include a first counter 140. The first counter 140 may be connected to the K first demultiplexers 120 and configured to send a first signal representing i when the processing device 100 receives the i-th row element of the k-th matrix to be transposed.

[0070] For example, the first counter 140 may include an input terminal 1141 a and an input terminal 1141 b .

[0071] When the processing device 100 receives the first row element of the kth matrix to be transposed, the first counter 140 can receive the total row value M of the kth matrix to be transposed through the input terminal 1141a, and receive the corresponding control signal through the input terminal 1141b, so as to know that the processing device 100 has received the first row element of the kth matrix to be transposed. In this case, the first counter 140 will send a first signal representing 1, so that the kth first demultiplexer 120 will transmit the N elements of the first row element of the kth matrix to be transposed to the N storage units 112 of the first register 111 in response to the first signal representing 1.

[0072] When the processing device 100 receives the second row element of the kth matrix to be transposed, the first counter 140 can receive the corresponding control signal through the input terminal 1141b to know that the processing device 100 receives the second row element of the kth matrix to be transposed. In this case, the first counter 140 will send a first signal representing 2, so that the kth first demultiplexer 120 responds to the first signal representing 2 and transmits N elements of the second row element of the kth matrix to be transposed to the N storage units 112 of the second register 111 in a one-to-one correspondence.

[0073] By analogy, when the processing device 100 receives the Mth row element of the kth matrix to be transposed, the first counter 140 can receive the corresponding control signal through the input terminal 1141b to know that the processing device 100 receives the Mth row element of the kth matrix to be transposed. In this case, the first counter 140 will send a first signal representing M, so that the kth first demultiplexer 120 responds to the first signal representing M and transmits N elements of the Mth row element of the kth matrix to be transposed to the N storage units 112 of the Mth register 111 in a one-to-one correspondence.

[0074] In some embodiments, Figure 4 As shown, in the case where K≥2, the processing device 100 may further include a second demultiplexer 150 .

[0075] The second demultiplexer 150 may be connected to K first demultiplexers 120 , and may be configured to transmit the i-th row element of the received k-th matrix to be transposed to the k-th first demultiplexer 120 in response to a first indication signal corresponding to the k-th first demultiplexer 120 .

[0076] For example, the second demultiplexer 150 may include an input terminal and K output terminals connected one-to-one with the K first demultiplexers 120. The second demultiplexer 150 may receive the i-th row element of the k-th matrix to be transposed via the input terminal, and transmit the received i-th row element of the k-th matrix to be transposed to the k-th first demultiplexer 120 via the k-th output terminal connected with the k-th first demultiplexer 120 according to the first indication signal corresponding to the k-th first demultiplexer 120.

[0077] In some embodiments, when K≥2, the kth first demultiplexer 120 may receive the i-th row element of the kth matrix to be transposed through the second demultiplexer 150. In this case, the second demultiplexer 150 receiving the i-th row element of the kth matrix to be transposed is equivalent to the processing device 100 receiving the i-th row element of the kth matrix to be transposed.

[0078] When K=1, the kth first demultiplexer 120 can directly receive the i-th row element of the kth matrix to be transposed. In this case, the kth first demultiplexer 120 receiving the i-th row element of the kth matrix to be transposed is equivalent to the processing device 100 receiving the i-th row element of the kth matrix to be transposed.

[0079] In some embodiments, when K≥2, the processing device 100 may further include a second counter and a first controller 160 .

[0080] The second counter may be connected to all K first demultiplexers 120 , and may be configured to send a first flag signal corresponding to the kth matrix to be transposed when the second demultiplexer 150 receives the i-th row element of the kth matrix to be transposed.

[0081] The first controller 160 may be connected to both the second counter and the second demultiplexer 150 , and may be configured to send a first indication signal corresponding to the kth first demultiplexer 120 to the second demultiplexer 150 in response to a first flag signal corresponding to the kth matrix to be transposed.

[0082] In this way, when the processing device includes multiple groups of registers, it can be ensured that the second demultiplexer accurately distributes the multiple matrices to be transposed to the corresponding multiple groups of registers, thereby further improving the reliability of the transposition operation.

[0083] In some embodiments, the second counter may be another counter different from the first counter 140 .

[0084] In other embodiments, Figure 4 As shown, the second counter is integrally arranged with the first counter 140 , that is, the two can be the same counter.

[0085] For example, the first counter 140 (i.e., the second counter) can receive a corresponding control signal through the input terminal 1141b to know that the second multiplexer 150 has received the i-th row element of the k-th matrix to be transposed (i.e., the processing device 100 has received the i-th row element of the k-th matrix to be transposed), thereby sending a first signal representing i to the k-th first multiplexer 120 and a first flag signal corresponding to sending the k-th matrix to be transposed to the first controller 160.

[0086] The first controller 160 may send a first indication signal corresponding to the kth first demultiplexer 120 to the second demultiplexer 150 in response to the first flag signal corresponding to the kth matrix to be transposed from the first counter 140 .

[0087] The second demultiplexer 150 may transmit the received i-th row element of the k-th matrix to be transposed to the k-th first demultiplexer 120 in response to the first indication signal corresponding to the k-th first demultiplexer 120 from the first controller 160 .

[0088] It can be seen that the first controller 160 can control the second demultiplexer 150 to distribute the kth matrix to be transposed to the kth first demultiplexer 120 accordingly according to the instruction of the first counter 140 .

[0089] Correspondingly, the kth first multiplexer 120 can receive the i-th row elements of the k-th matrix to be transposed from the second multiplexer 150, and transmit the received i-th row elements of the k-th matrix to be transposed to the i-th register of the k-th group of registers according to the first signal representing i from the first counter 140.

[0090] In the above embodiment, through a counter, a first signal representing i can be sent to control the kth first demultiplexer to distribute multiple rows of elements of the kth matrix to be transposed, and a first flag signal corresponding to the kth matrix to be transposed can be sent to control the second demultiplexer to distribute multiple matrices to be transposed. In this way, it can not only ensure that the multiple rows of elements of each matrix to be transposed are accurately distributed to the corresponding registers, but also ensure that the multiple matrices to be transposed are accurately distributed to the corresponding multiple groups of registers, thereby saving hardware resources to help reduce the size of the processing device, and further improving the reliability of the transposition operation.

[0091] In some embodiments, please refer to Figure 3 , each register 111 may include N output terminals corresponding one-to-one to the N storage units 112 of the register 111 . Figure 3Two output terminals 1122a and 1122b of each register 111 are schematically shown.

[0092] The k-th group of registers 110 may include N groups of output terminals, and the j-th group of output terminals may include the j-th output terminal corresponding to the j-th storage unit 112 of each register 111 in the k-th group of registers 110 .

[0093] The processing device 100 may further include K first multiplexers 130. The K first multiplexers 130 are connected to the K groups of registers 110 in a one-to-one correspondence. Figure 3 A first multiplexer 130 connected to a group of registers 110 is schematically shown.

[0094] The kth first multiplexer 130 can be connected to all N groups of output terminals of the kth group of registers 110, and can be configured to output the jth column element of the kth matrix to be transposed outputted by the jth group of output terminals of the kth group of registers 110 in response to a second signal representing j.

[0095] For example, Figure 3 As shown, the first group of output ends may include three output ends 1122 a corresponding to the first storage units 112 of the three registers 111 , and the second group of output ends may include three output ends 1122 b corresponding to the second storage units 112 of the three registers 111 .

[0096] The first multiplexer 130 can respond to the second signal representing 1 and select the first element output from the output terminal 1122a of the first storage unit 112 of each register 111, that is, output the first column element of the matrix to be transposed from the first group of output terminals; the first multiplexer 130 can respond to the second signal representing 2 and select the second element output from the output terminal 1122b of the second storage unit 112 of each register 111, that is, output the second column element of the matrix to be transposed from the second group of output terminals.

[0097] In the above embodiment, the kth first multiplexer can select the jth column element of the kth matrix to be transposed from the jth group output terminal of the kth group register to output according to the signal indicating j. In this way, it can be ensured that the N column elements of the kth matrix to be transposed can be output in sequence from 1 to N or from N to 1, and further ensure the accuracy of the arrangement order of the N row elements in the kth transposed matrix obtained after the N column elements are subsequently stored in the row direction, thereby further improving the reliability of the transposition operation.

[0098] In some embodiments, please refer to Figure 4, the processing device 100 may further include a third counter 170. The third counter 170 may be connected to all K first multiplexers 130, and may be configured to output a second signal representing j in sequence from 1 to N or from N to 1 when the kth group of registers 110 has received M rows of elements of the kth matrix to be transposed.

[0099] It should be understood that when the kth group of registers 110 has received M rows of elements of the kth matrix to be transposed, it means that the kth group of registers 110 has received all elements of the kth matrix to be transposed.

[0100] In this way, it can be ensured that the kth first multiplexer will output the N column elements of the kth matrix to be transposed in sequence only when the kth group of registers has received the M row elements of the kth matrix to be transposed, thereby reducing the possibility of missing individual elements in each column of the output caused by the kth first multiplexer outputting when the kth group of registers only receives part of the row elements of the kth matrix to be transposed, thereby further improving the reliability of the transposition operation.

[0101] In some embodiments, please refer to Figure 4 The processing device 100 may further include a second controller 180. The second controller 180 may be configured to output a first control signal when the kth group of registers has received M rows of elements of the kth matrix to be transposed.

[0102] In these embodiments, the third counter 170 may also be connected to the second controller 180 and may be configured to sequentially output second signals representing j in a sequence from 1 to N or from N to 1 in response to a first control signal from the second controller 180 .

[0103] For example, the third counter 170 may include an input terminal 1171a and an input terminal 1171b, wherein the input terminal 1171a may be connected to the second controller 180. The third counter 170 may receive the first control signal from the second controller 180 through the input terminal 1171a to learn that the kth group of registers has received the M row elements of the kth matrix to be transposed, and may receive the column value N of the kth matrix to be transposed through the input terminal 1171b. Thus, the third counter 170 may output the second signal representing j in sequence from 1 to N or from N to 1 according to the first control signal output by the second controller 180, so that the kth first multiplexer 130 may select and output the jth column element of the kth matrix to be transposed according to the second signal representing j.

[0104] In some embodiments, the second controller 180 may be further configured to output the second control signal when the third counter 170 outputs the second signal indicating N in sequence from 1 to N or outputs the second signal indicating 1 in sequence from N to 1.

[0105] In these embodiments, the third counter 170 may also be configured to stop outputting the second signal representing j in response to the second control signal from the second controller 180 .

[0106] For example, the second controller 180 may be connected to an output terminal of the third counter 170 for outputting a second signal representing j. In the case of receiving a second signal representing N from the third counter 170 in the order from 1 to N, or receiving a second signal representing 1 from the third counter 170 in the order from N to 1, the second controller 180 may send a second control signal to the third counter 170 so that the third counter 170 stops outputting the second signal representing j.

[0107] It should be understood that if the third counter 170 has output a second signal representing N in the order from 1 to N or has output a second signal representing 1 in the order from N to 1, it means that the kth first multiplexer 130 has output the last column of elements of the kth matrix to be transposed.

[0108] In this way, through a controller, not only can the third counter be controlled to start outputting the second signal representing j in sequence after all elements of the matrix to be transposed have been stored in the corresponding registers, but the third counter can also be controlled to stop outputting the second signal representing j after all elements of the matrix to be transposed have been output from the corresponding registers, thereby further improving the reliability of the transposition operation while saving hardware resources.

[0109] In some embodiments, the second controller 180 may be connected to the first counter 140 , and may be configured to output a first control signal in response to a first signal indicating M from the first counter 140 .

[0110] For example, the second controller 180 may be connected to an output terminal of the first counter 140 for outputting a first signal representing i. Upon receiving a first signal representing M from the first counter 140, the second controller 180 may output a first control signal so that the third counter 170 sequentially outputs a second signal representing j in the order from 1 to N or from N to 1.

[0111] It should be understood that the first counter 140 can make the kth first demultiplexer 120 transmit the Mth row element of the kth matrix to be transposed to the Mth register 111 of the kth group of registers 110 by sending the first signal representing M. Therefore, when the second controller 180 receives the first signal representing M from the first counter 140, it can be known that the kth group of registers has received the Mth row element of the kth matrix to be transposed.

[0112] In this way, the second controller can accurately know that the kth group of registers has received the Mth row elements of the kth matrix to be transposed through the first signal representing M from the first counter, thereby improving the accuracy of outputting the first control signal and thus improving the reliability of the transposition operation.

[0113] In some embodiments, please refer to Figure 4 , when K≥2, the processing device 100 may further include a second multiplexer 190 .

[0114] The second multiplexer 190 may be connected to all K first multiplexers 130 , and configured to select and output the j-th column element of the k-th matrix to be transposed from the k-th first multiplexer 130 in response to a second indication signal corresponding to the k-th first multiplexer 130 .

[0115] For example, the second multiplexer 190 may include an output terminal and K input terminals connected one-to-one with the K first multiplexers 130. The second multiplexer 190 may select, according to the second indication signal corresponding to the kth first multiplexer 130, the jth column element of the kth matrix to be transposed inputted via the kth input terminal connected to the kth first multiplexer 130 for output.

[0116] In this way, when the j-th column elements of multiple matrices to be transposed all need to be output, the second multiplexer can select the j-th column element of one matrix to be transposed from them for output, thereby reducing the possibility of data confusion caused by the simultaneous output of the j-th column elements of multiple matrices to be transposed, thereby further improving the reliability of the transposition operation.

[0117] In some embodiments, when K≥2, the processing device 100 may further include a fourth counter and a third controller 200 .

[0118] The fourth counter may be connected to all K first multiplexers 130 , and may be configured to send a second flag signal corresponding to the kth matrix to be transposed when the kth group of registers 110 has received M rows of elements of the kth matrix to be transposed.

[0119] The third controller 200 may be connected to both the fourth counter and the second multiplexer 190 , and may be configured to send a second indication signal corresponding to the kth first multiplexer 130 to the second multiplexer 190 in response to a second flag signal corresponding to the kth matrix to be transposed.

[0120] In this way, when the processing device includes multiple groups of registers, it can ensure that the second multiplexer accurately selects the element output from the kth first multiplexer when all elements in the kth matrix to be transposed have been input into the kth group of registers, thereby further improving the reliability of the transposition operation.

[0121] In some embodiments, the fourth counter may be another counter different from the third counter 170 .

[0122] In other embodiments, Figure 4 As shown, the fourth counter and the third counter 170 can be integrally arranged, that is, the two are the same counter.

[0123] For example, the third counter 170 (i.e., the fourth counter) can receive the first control signal from the second controller 180 through the input terminal 1171a to know that the kth group of registers has received the M rows of elements of the kth matrix to be transposed, thereby sending the second flag signal corresponding to the kth matrix to be transposed to the third controller 200.

[0124] The third controller 200 may send a second indication signal corresponding to the kth first multiplexer 130 to the second multiplexer 190 in response to the second flag signal corresponding to the kth matrix to be transposed.

[0125] The second multiplexer 190 may select and output the j-th column element of the k-th matrix to be transposed from the k-th first multiplexer 130 in response to the second indication signal corresponding to the k-th first multiplexer 130 .

[0126] It can be seen that the third controller 200 can control the second multiplexer 190 to select the j-th column element of the k-th matrix to be transposed from the k-th first multiplexer 130 for output according to the instruction of the third counter 170 .

[0127] In the above embodiment, through a counter, when the kth group of registers has received the M row elements of the kth matrix to be transposed, not only can the second signal representing j be sent in sequence to ensure that the kth first multiplexer can sequentially output the N column elements of the kth matrix to be transposed, but also the second flag signal corresponding to the kth matrix to be transposed can be sent to ensure that the second multiplexer can select the N column elements output from the kth first multiplexer for output. In this way, the reliability of the output of the N column elements of the kth matrix to be transposed can be ensured while saving hardware resources to help reduce the size of the processing device, so as to further improve the reliability of the transposition operation.

[0128] In some embodiments, the K group of registers may include an mth group of registers and an nth group of registers. The time when the mth group of registers receives the M row elements of the mth matrix to be transposed at least partially overlaps with the time when the nth group of registers outputs the N column elements of the nth matrix to be transposed, where 1≤m≤K, 1≤n≤K, and m and n are different.

[0129] For example, Figure 4 As shown, when the first group of registers 110 connected to the first first multiplexer 130 has received the M row elements of the first matrix to be transposed, the second multiplexer 190 can select the j-th column element of the first matrix to be transposed from the first first multiplexer 130 for output in response to the second indication signal corresponding to the first first multiplexer 130. In the process of the second multiplexer 190 sequentially outputting the N column elements of the first matrix to be transposed, the second demultiplexer 150 can receive the M row elements of the second matrix to be transposed, and transmit the received M row elements of the second matrix to be transposed to the second group of registers via the second first demultiplexer 120. That is, the time when the first group of registers outputs the N column elements of the first matrix to be transposed can overlap with the time when the second group of registers receives the M row elements of the second matrix to be transposed.

[0130] In this way, any two groups of registers in the K groups of registers can perform transposition operations alternately and continuously, that is, there is no need to wait for all N columns of elements of a matrix to be transposed stored in one group of registers to be output before inputting another matrix to be transposed into another group of registers, thereby further improving the processing efficiency of the transposition operation.

[0131] In some embodiments, the time when the mth group of registers receives the M row elements of the mth matrix to be transposed and the time when the nth group of registers outputs the N column elements of the nth matrix to be transposed can all overlap, thereby further improving the processing efficiency of the transposition operation.

[0132] In some embodiments, the kth matrix to be transposed can be obtained by dividing the original matrix in the neural network algorithm. This division can make the number of rows of the original matrix an integer multiple of the number of rows of the kth matrix to be transposed, and the number of columns of the original matrix an integer multiple of the number of columns of the kth matrix to be transposed. For example, the sizes of the multiple matrices to be transposed obtained after dividing the original matrix can be the same.

[0133] It should be understood that when the size of the original matrix does not meet the integer multiple requirement for division, the original matrix may be padded (eg, filled with 0) to fill the number of rows and / or columns of the original matrix to the required size.

[0134] In some embodiments, the original matrix may be divided according to the number M of registers 111 in the kth group of registers 110 in the processing device 100 and the number N of storage units 112 in each register 111, so that the kth group of registers 110 can support the transposition operation of the kth matrix to be transposed obtained after the division. For example, the size specification of the kth matrix to be transposed can be the maximum specification supported by the kth group of registers 110 through division.

[0135] Figure 5 is a schematic diagram of an original matrix according to some embodiments of the present disclosure.

[0136] like Figure 5 As shown, the original matrix 50 is a 6×8 matrix.

[0137] Assuming that the number of registers 111 in each register group 110 in the processing device 100 is 3, and the number of storage units 112 in each register 111 is 4, the original matrix 50 can be divided to obtain 4 matrices to be transposed. A matrix of size 3×4 in a dotted box is a matrix to be transposed.

[0138] For example, the processing device 100 may include 4 groups of registers. The processing device 100 may sequentially receive and store the 3 row elements of the 1st to 4th matrices to be transposed, and sequentially output the 4 column elements of the 1st to 4th matrices to be transposed, thereby completing the transposition operation on the original matrix 50.

[0139] For another example, the processing device 100 may include two groups of registers. The processing device 100 may first sequentially receive and store the three rows of elements of the first to second matrices to be transposed, and sequentially output the four columns of elements of the first to second matrices to be transposed; then sequentially receive and store the three rows of elements of the third to fourth matrices to be transposed, and sequentially output the four columns of elements of the third to fourth matrices to be transposed, thereby completing the transposition operation on the original matrix 50.

[0140] In this way, for an original matrix of any size that needs to be transposed in a neural network algorithm, the original matrix can be divided into multiple matrices to be transposed that can be supported by the processing device 100 in the above manner to perform a transposition operation, thereby improving the versatility of the processing device 100.

[0141] Figure 6 It is a schematic diagram of the structure of an artificial intelligence chip according to some embodiments of the present disclosure.

[0142] like Figure 6 As shown, the artificial intelligence chip 600 may include a processing device 601 for transposition operation (for example, the processing device 601 may be the processing device 100 of any one of the above-mentioned embodiments).

[0143] In some embodiments, the artificial intelligence chip 600 may further include a first storage device 602. The first storage device 602 may include a first memory 6021.

[0144] The first storage device 602 may be configured to receive the j-th column element of the k-th matrix to be transposed from the processing device 601 , and store the j-th column element of the k-th matrix to be transposed in the first memory 6021 as the j-th row element of the k-th transposed matrix.

[0145] In some embodiments, the first storage device 602 may be a data buffer (Data Buffer, DB). The first memory 6021 may be a random access memory (Random Access Memory, RAM).

[0146] In some embodiments, the first storage device 602 may further include a first address generating device 6022 and a first control register 6023 .

[0147] The first control register 6023 may be configured to send a first drive signal in response to a first configuration signal corresponding to the j-th column element of the k-th matrix to be transposed. The first address generating device 6022 may be configured to generate a first write address for storing the j-th row element of the k-th transposed matrix in response to a first drive signal from the first control register 6023.

[0148] In these embodiments, the first storage device 602 may be configured to write the j-th column element of the k-th matrix to be transposed as the j-th row element of the k-th transposed matrix into the first memory 6021 according to the first write address.

[0149] In some embodiments, the artificial intelligence chip 600 may further include a second storage device 603. The second storage device 603 may include a second memory 6031.

[0150] The second storage device 603 may be configured to read the M row elements of the kth matrix to be transposed from the second memory 6031 row by row, and transmit the M row elements of the kth matrix to be transposed to the processing device 601 row by row.

[0151] In some embodiments, the second storage device 603 may be a data buffer. The second memory 6031 may be a random access memory.

[0152] In some embodiments, the second storage device 603 may further include a second address generating device 6032 and a second control register 6033 .

[0153] The second control register 6033 may be configured to send a first drive signal in response to a first configuration signal corresponding to the i-th row element of the k-th matrix to be transposed. The second address generating device 6032 may be configured to generate a first read address for obtaining the i-th row element of the k-th matrix to be transposed in response to the first drive signal from the second control register 6033.

[0154] In these embodiments, the second storage device 603 may be configured to read the i-th row element of the k-th matrix to be transposed from the second memory 6031 according to the first read address.

[0155] The embodiments of the present disclosure also provide an accelerator, comprising an artificial intelligence chip according to any one of the above embodiments (e.g., artificial intelligence chip 600).

[0156] The embodiment of the present disclosure also provides a method for processing a transposition operation, comprising the following steps.

[0157] First, the i-th register in the k-th group of registers of K groups of registers receives the i-th row elements of the k-th matrix to be transposed, and stores the j-th element in the i-th row elements of the k-th matrix to be transposed in the j-th storage unit of the i-th register in the k-th group of registers.

[0158] Here, the kth group of registers includes M registers, each register includes N storage parts, the kth matrix to be transposed is an M×N matrix, and the N elements in the i-th row of the kth matrix to be transposed are arranged in sequence from 1 to N, N≥2, M≥2, K≥1, 1≤i≤M, 1≤j≤N, 1≤k≤K.

[0159] Then, the M registers in the kth group of registers sequentially output the N column elements of the kth matrix to be transposed in the order from 1 to N or from N to 1.

[0160] Here, the j-th column element of the k-th matrix to be transposed includes the j-th element in the j-th storage unit of each register in the k-th group of registers.

[0161] It should be understood that the processing method for the transposition operation can be performed by the processing device of any of the above embodiments (e.g., the processing device 100). Other embodiments and advantages of the processing method for the transposition operation provided by the embodiment of the present disclosure can refer to the description of the processing device for the transposition operation provided by the embodiment of the present disclosure, which will not be repeated here.

[0162] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the description of the present disclosure, it is fully understood how to implement the technical solutions disclosed herein.

[0163] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A transposition processing device, comprising K groups of registers, the kth group of registers comprising M registers, each register comprising N storage units, N≥2, M≥2, K≥1, 1≤k≤K, wherein: The i-th register in the k-th group of registers is configured to receive the i-th row element of the k-th matrix to be transposed, and store the j-th element in the i-th row element of the k-th matrix to be transposed in the j-th storage unit of the i-th register in the k-th group of registers, the k-th matrix to be transposed is an M×N matrix, and the N elements in the i-th row element of the k-th matrix to be transposed are arranged in sequence from 1 to N, 1≤i≤M, 1≤j≤N; The M registers in the k-th group of registers are configured to sequentially output N column elements of the k-th matrix to be transposed in an order from 1 to N or from N to 1, and the j-th column element of the k-th matrix to be transposed includes the j-th element in the j-th storage unit of each register in the k-th group of registers; Each register includes N output terminals corresponding to the N storage parts of the register, the k-th group of registers includes N groups of output terminals, and the j-th group of output terminals includes the j-th output terminal corresponding to the j-th storage part of each register in the k-th group of registers; The processing device also includes: K first multiplexers, the kth first multiplexer is connected to the N groups of output terminals of the kth group of registers, and is configured to output the jth column element of the kth matrix to be transposed outputted by the jth group of output terminals of the kth group of registers in response to a second signal representing j.

2. The processing device according to claim 1, wherein: Each register includes N input terminals, and the processing device also includes: K first multiplexers, the kth first multiplexer is connected to the N input terminals of each register in the kth group of registers, and is configured to respond to a first signal representing i, to transmit the jth element of the i-th row element of the received k-th matrix to be transposed to the j-th storage unit of the i-th register of the k-th group of registers through the j-th input terminal of the i-th register of the k-th group of registers.

3. The processing device according to claim 2, further comprising: The first counter is connected to the K first demultiplexers and is configured to send a first signal representing i when the processing device receives the i-th row element of the k-th matrix to be transposed.

4. The processing device according to claim 2 or 3, wherein: K≥2, the processing device further includes: The second demultiplexer is connected to the K first demultiplexers and is configured to transmit the i-th row element of the received k-th transposed matrix to the k-th first demultiplexer in response to a first indication signal corresponding to the k-th first demultiplexer.

5. The processing device according to claim 4, further comprising: a second counter connected to the K first demultiplexers and configured to send a first flag signal corresponding to the kth matrix to be transposed when the second demultiplexer receives the i-th row element of the kth matrix to be transposed; The first controller is connected to the second counter and the second demultiplexer, and is configured to send a first indication signal corresponding to the kth first demultiplexer to the second demultiplexer in response to a first flag signal corresponding to the kth matrix to be transposed.

6. The processing device according to claim 1, further comprising: The third counter is connected to the K first multiplexers and is configured to output a second signal representing j in sequence from 1 to N or from N to 1 when the kth group of registers has received M rows of elements of the kth matrix to be transposed.

7. The processing device according to claim 6, further comprising: A second controller is configured to output a first control signal when the kth group of registers has received M rows of elements of the kth matrix to be transposed; The third counter is also connected to the second controller and is configured to output a second signal representing j in sequence from 1 to N or from N to 1 in response to the first control signal.

8. The processing device according to claim 7, wherein: The second controller is further configured to output a second control signal when the third counter outputs a second signal indicating N in a sequence from 1 to N or outputs a second signal indicating 1 in a sequence from N to 1; The third counter is further configured to stop outputting the second signal representing j in response to the second control signal.

9. The processing device according to claim 7 or 8, wherein: Each register includes N input terminals, and the processing device also includes: K first demultiplexers, the kth first demultiplexer is connected to the N input terminals of each register in the kth group of registers, and is configured to transmit the jth element of the i-th row element of the kth matrix to be transposed received to the jth storage part of the i-th register of the kth group of registers through the j-th input terminal of the i-th group of input terminals of the kth group of registers in response to the first signal representing i; A first counter connected to each of the K first demultiplexers and configured to send a first signal representing i when the processing device receives an i-th row element of the k-th matrix to be transposed; The second controller is connected to the first counter and is configured to output the first control signal in response to a first signal representing M from the first counter.

10. The processing device according to any one of claims 1 to 3 and 6 to 8, wherein: K≥2, the processing device further includes: The second multiplexer is connected to the K first multiplexers and is configured to select and output the j-th column element of the k-th matrix to be transposed from the k-th first multiplexer in response to a second indication signal corresponding to the k-th first multiplexer.

11. The processing device according to claim 10, further comprising: a fourth counter connected to the K first multiplexers and configured to send a second flag signal corresponding to the kth matrix to be transposed when the kth group of registers has received the M rows of elements of the kth matrix to be transposed; The third controller is connected to the fourth counter and the second multiplexer, and is configured to send a second indication signal corresponding to the kth first multiplexer to the second multiplexer in response to a second flag signal corresponding to the kth matrix to be transposed.

12. The processing device according to any one of claims 1 to 3 and 6 to 8, wherein: The K group of registers includes an mth group of registers and an nth group of registers, the time when the mth group of registers receives the M row elements of the mth matrix to be transposed and the time when the nth group of registers outputs the N column elements of the nth matrix to be transposed at least partially overlap, 1≤m≤K, 1≤n≤K, m and n are different.

13. The processing device according to any one of claims 1 to 3 and 6 to 8, wherein: The kth matrix to be transposed is obtained by dividing the original matrix in the neural network algorithm, and the division makes the number of rows of the original matrix an integer multiple of the number of rows of the kth matrix to be transposed, and the number of columns of the original matrix is ​​an integer multiple of the number of columns of the kth matrix to be transposed.

14. An artificial intelligence chip, comprising: The processing device according to any one of claims 1 to 13.

15. The chip according to claim 14, further comprising: The first storage device is configured to receive the j-th column element of the k-th matrix to be transposed from the processing device, and store the j-th column element of the k-th matrix to be transposed as the j-th row element of the k-th transposed matrix in the first memory of the first storage device.

16. The chip according to claim 14, further comprising: The second storage device is configured to read the M row elements of the kth matrix to be transposed row by row from the second memory of the second storage device, and transmit the M row elements of the kth matrix to be transposed row by row to the processing device.

17. An accelerator, comprising: A chip as described in any one of claims 14 to 16.

18. A method for processing a transposition operation, comprising: The i-th register in the k-th group of registers of the K-th group of registers receives the i-th row element of the k-th matrix to be transposed, and stores the j-th element in the i-th row element of the k-th matrix to be transposed in the j-th storage section of the i-th register in the k-th group of registers, wherein the k-th group of registers includes M registers, each register includes N storage sections and N output terminals corresponding to the N storage sections of the register one by one, the k-th matrix to be transposed is an M×N matrix, and the N elements in the i-th row element of the k-th matrix to be transposed are arranged in sequence from 1 to N, N≥2, M≥2, K≥1, 1≤i≤M, 1≤j≤N, 1≤k≤K; The M registers in the kth group of registers sequentially output N column elements of the kth matrix to be transposed in order from 1 to N or from N to 1, wherein the jth column element of the kth matrix to be transposed includes the jth element in the jth storage section of each register in the kth group of registers, the kth group of registers includes N groups of output terminals, and the jth group of output terminals includes the jth output terminal corresponding to the jth storage section of each register in the kth group of registers; The kth first multiplexer among the K first multiplexers outputs the j-th column element of the k-th matrix to be transposed outputted from the j-th group output terminal of the k-th group of registers in response to the second signal representing j, and the k-th first multiplexer is connected to all N groups of output terminals of the k-th group of registers.

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