Power semiconductor device capable of reducing contact resistance and preparation method thereof

Abstract

The present invention relates to a power semiconductor device and a preparation method capable of reducing contact resistance. It comprises: an active region, comprising a plurality of cell grooves, wherein a channel source region body is arranged at least on one side of the cell groove, the channel source region body comprising a second conductive type well region and a first conductive type source region adapted to be connected to the second conductive type well region; the first conductive type source region extends into an electrode metal contact hole of an insulating dielectric layer, the first conductive type source region is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole, and the first electrode metal of the device is also electrically connected to the second conductive type well region of the channel region; an insulating dielectric layer is supported on a semiconductor substrate, and the insulating dielectric layer covers the notch of the cell groove, so as to use the insulating dielectric layer to separate the cell groove from the first electrode metal of the device. The present invention can effectively reduce contact resistance and reduce conduction loss of power semiconductor devices.

Description

Technical Field

[0001] The invention relates to a power semiconductor device and a preparation method thereof, in particular to a power semiconductor device and a preparation method thereof capable of reducing contact resistance. Background Art

[0002] SGT (Shield Gate Trench) power devices are a new type of power semiconductor devices, which have the advantages of low conduction loss and low switching loss compared with traditional power semiconductor devices. SGT power devices can include SGT MOSFET devices and SGT IGBT (Insulated Gate Bipolar Transistor) devices. Among them, SGTMOSFET (Metal-Oxide- Semiconductor Field-Effect Transistor) devices are widely used as switching devices and can achieve excellent power control effects.

[0003] The cell of an SGT power device generally consists of a shield gate and a control gate. When the SGT power device is turned on, the drain current follows the longitudinal sidewalls of the SGT trench to form an inversion layer channel on the surface of the body region. When the source is positively biased, electrons are transferred from the source region to the drain region along the inversion layer channel. After passing through the channel from the source region, the electrons enter the epitaxial region at the bottom of the trench gate and then expand across the width of the entire active region.

[0004] Although the SGT power device has lower conduction loss, the contact area between the source region and the metal is small, resulting in a large contact resistance, making it impossible to further reduce the conduction loss of the SGT power device. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a power semiconductor device and a preparation method capable of reducing contact resistance, which can effectively reduce contact resistance and reduce conduction loss of the power semiconductor device.

[0006] According to the technical solution provided by the present invention, a power semiconductor device capable of reducing contact resistance comprises:

[0007] A semiconductor substrate having a first conductivity type;

[0008] The active region is distributed in the central area of ​​the semiconductor substrate and includes a plurality of unit cell trenches, wherein a channel source region body is provided at least on one side of the unit cell trench, and the channel source region body includes a second conductivity type well region for forming a channel region and a first conductivity type source region adaptively connected to the second conductivity type well region;

[0009] The first conductive type source region extends into the electrode metal contact hole of the insulating dielectric layer, the first conductive type source region is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole, and the first electrode metal of the device is also electrically connected to the second conductive type well region;

[0010] The insulating dielectric layer is supported on the semiconductor substrate, and the insulating dielectric layer covers the notch of the cell trench, so as to separate the cell trench from the first electrode metal of the device by using the insulating dielectric layer.

[0011] In the cross section of the power semiconductor device, the first conductive type source region is located above the second conductive type well region, and a plurality of second conductive type source contact regions are arranged in the first conductive type source region, wherein:

[0012] The junction depth of the second conductivity type source contact region is not less than the junction depth of the first conductivity type source region, so that the second conductivity type source contact region is in contact with the second conductivity type well region;

[0013] When the first electrode metal of the device is in ohmic contact with the first conductivity type source region, the first electrode metal of the device is also in ohmic contact with the second conductivity type source contact region, and the first electrode metal of the device is electrically connected to the contacted second conductivity type well region through the second conductivity type source contact region.

[0014] The insulating dielectric layer includes an insulating first dielectric layer and an insulating second dielectric layer located on the insulating first dielectric layer, wherein:

[0015] The insulating first dielectric layer is supported on the semiconductor substrate and corresponds to the notch of the cell trench, and the thickness of the insulating second dielectric layer is greater than the thickness of the insulating first dielectric layer;

[0016] The electrode metal contact hole penetrates the insulating second dielectric layer, the first conductive type source region passes through the insulating first dielectric layer and then extends into the electrode metal contact hole, and the first conductive type source region is vertically distributed in the electrode metal contact hole.

[0017] In the active region, the channel source region body between any two adjacent cell trenches is configured as a fin structure, wherein:

[0018] When the channel source region body is configured as a fin structure, only one well region of the second conductivity type and one source region of the first conductivity type are arranged between two adjacent cell trenches, and the well region of the second conductivity type and the source region of the first conductivity type are in contact with the outer side walls of the cell trenches on both sides at the same time;

[0019] When the power semiconductor device is forward-conducting, a full inversion conduction channel is formed between two cell trenches based on the fin structure, and the width of the formed full inversion conduction channel does not exceed 100 nm.

[0020] Any cell groove includes a cell wide groove and a cell narrow groove connected to the cell wide groove, wherein the width of the cell wide groove is greater than the groove width of the cell narrow groove, and the groove bottom of the cell narrow groove is located below the corresponding groove bottom of the cell wide groove;

[0021] For any two adjacent cell grooves, the cell-width grooves of the two cell grooves are in direct correspondence, and the fin structure is in contact with the outer sidewalls of the two cell-width grooves;

[0022] When the power semiconductor device is forward-conducting, a full inversion conduction channel is formed between two cell-wide trenches based on the fin structure.

[0023] An SGT cell structure is set in each cell groove, where:

[0024] The SGT cell structure includes a control gate located in a wide cell trench and a shielding gate located in a narrow cell trench, wherein:

[0025] The width of the control grid is greater than the width of the shielding grid, and the control grid and the shielding grid are insulated and isolated from each other;

[0026] The control gate is insulated and isolated from the sidewall of the wide trench of the cell where it is located by a gate oxide layer;

[0027] The shielding gate is insulated and isolated from the sidewalls and bottom wall of the narrow trench of the unit cell where it is located by a field oxide layer, and the field oxide layer also covers the bottom wall and corresponding sidewalls of the wide trench of the unit cell above;

[0028] The thickness of the field oxide layer is greater than the thickness of the gate oxide layer;

[0029] The shielding gate is electrically connected to the first electrode metal of the device above the semiconductor substrate, the control gate is electrically connected to the second electrode metal of the device above the semiconductor substrate, and the first electrode metal of the device is isolated from the second electrode metal of the second device.

[0030] In the active area, a first conductive type enhancement layer is also included, wherein:

[0031] The first conductive type enhancement layer at least crosses the active area in the semiconductor substrate.

[0032] The bottom surface of the first conductive type enhancement layer is not lower than the bottom of the cell-wide trench, and the first conductive type enhancement layer is in contact with the gate oxide layer in the cell-wide trench.

[0033] The semiconductor substrate comprises a substrate and an epitaxial layer located on the substrate, wherein:

[0034] The epitaxial layer is adjacent to the substrate, and the cell trench is prepared in the epitaxial layer;

[0035] The epitaxial layer includes at least one epitaxial doping layer, wherein:

[0036] When the epitaxial layer includes multiple epitaxial doped layers, the bottom of the cell trench is located in the epitaxial doped layer adjacent to the substrate.

[0037] A method for preparing a power semiconductor device capable of reducing contact resistance is used to prepare the power semiconductor device described above, wherein the preparation method comprises:

[0038] A semiconductor substrate of a first conductivity type is provided, and a front cell process is performed on the front side of the semiconductor substrate to prepare an active area distributed in the central area of ​​the semiconductor substrate after the front cell process, wherein:

[0039] The active region includes a plurality of unit cell trenches, wherein a channel source region body is provided at least on one side of the unit cell trench, and the channel source region body includes a second conductive type well region and a first conductive type source region adaptively connected to the second conductive type well region;

[0040] The first conductive type source region extends into the electrode metal contact hole of the insulating dielectric layer, the first conductive type source region is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole, and the first electrode metal of the device is also electrically connected to the second conductive type well region in the channel region;

[0041] The insulating dielectric layer is supported on the semiconductor substrate, and the insulating dielectric layer covers the notch of the cell groove, so that the cell groove and the insulating dielectric layer are insulated and spaced by the insulating dielectric layer.

[0042] When performing front cell processing on a semiconductor substrate, it includes:

[0043] Performing trench etching on the front surface of the semiconductor substrate to form a plurality of cell-wide trenches in the semiconductor substrate;

[0044] Performing trench etching on the bottom of the cell wide trench to prepare a plurality of cell narrow trenches in the semiconductor substrate, wherein a cell trench is formed based on a cell narrow trench and a cell wide trench corresponding to the cell narrow trench, and for any cell trench, the notch of the cell narrow trench corresponds to the bottom of the cell wide trench, and the cell narrow trench is connected to the cell wide trench;

[0045] Preparing a cell groove oxide layer in the cell groove, wherein the cell groove oxide layer covers the corresponding inner walls of the cell wide groove and the cell narrow groove;

[0046] Filling a shielding grid in the above-mentioned cell narrow groove, wherein the shielding grid is insulated and isolated from the inner wall of the cell narrow groove by the cell groove oxide layer in the cell narrow groove;

[0047] An isolation dielectric body is prepared in the cell trench, and the corresponding cell trench oxide layer in the cell wide trench is removed to obtain a field oxide layer located in the cell narrow trench, wherein the isolation dielectric body is pressed on the shielding grid, and the field oxide layer also covers the bottom wall of the cell wide trench and the side wall adjacent to the bottom wall;

[0048] Prepare a gate oxide layer, wherein the gate oxide layer at least covers the sidewalls of the cell wide trench;

[0049] Filling a control gate in the cell-wide trench, wherein the control gate is insulated and isolated from the shielding gate by an isolation dielectric, and is insulated and isolated from the sidewall of the cell-wide trench by a gate oxide substrate, and the thickness of the control gate is less than the depth of the cell-wide trench;

[0050] Processing the gate oxide base layer to obtain a gate oxide layer corresponding to the control gate;

[0051] Preparing an insulating first dielectric layer in the cell-wide trench, wherein the insulating first dielectric layer covers the control gate in the cell-wide trench and the insulating first dielectric layer is below the notch of the cell-wide trench;

[0052] A channel source region body is prepared outside the cell-wide trench, wherein when the channel source region body is a fin structure, the fin structure is at least distributed between adjacent cell-wide trenches and is adaptively connected to adjacent cell-wide trenches on both sides, the fin structure includes a second conductivity type well region and a first conductivity type source region adaptively connected to the second conductivity type well region, and an end of the first conductivity type source region is located above the insulating first dielectric layer;

[0053] Preparing an insulating second dielectric layer, and patterning the insulating second dielectric layer to obtain at least a plurality of electrode metal contact holes corresponding to the first conductive type source regions, wherein the electrode metal contact holes penetrate the insulating second dielectric layer, and the first conductive type source regions extend into the corresponding electrode metal contact holes;

[0054] A front electrode metal is prepared on the front side of the semiconductor substrate, wherein the prepared metal electrode includes a first device electrode metal and a second device electrode metal,

[0055] The first electrode metal of the device is filled in the electrode metal contact hole and is in ohmic contact with the first conductive type source region, and is electrically connected to the shielding gate in each cell narrow trench and the corresponding second conductive type well region in the active region;

[0056] The second electrode metal of the device is electrically connected to the control gate, and the second electrode metal of the device is insulated and isolated from the first electrode metal of the device.

[0057] The advantages of the present invention are as follows: the first conductive type source region of the channel source region body extends into the electrode metal contact hole of the insulating dielectric layer, and the first conductive type source region is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole. Thus, the first electrode metal of the device can simultaneously contact the upper end surface and the corresponding side surface of the first conductive type source region entering the electrode metal contact hole, thereby increasing the contact area between the first electrode metal of the device and the first conductive type source region, effectively reducing the contact resistance, and reducing the conduction loss of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a cross-sectional view of a power semiconductor device according to a first embodiment of the present invention.

[0059] Figure 2 It is a cross-sectional view of a power semiconductor device according to a second embodiment of the present invention.

[0060] Figure 3 For the present invention Figure 1~Figure 2 A top view of a power semiconductor device in an embodiment.

[0061] Figure 4 to Figure 16 For Figure 1 A cross-sectional view of a specific manufacturing process step of an embodiment of a medium-power semiconductor device, wherein:

[0062] Figure 4 A cross-sectional view of an embodiment of a semiconductor substrate of the present invention.

[0063] Figure 5 It is a cross-sectional view of an embodiment of the present invention after forming a cell wide groove.

[0064] Figure 6 It is a cross-sectional view of an embodiment of the present invention after forming a cell narrow groove.

[0065] Figure 7 This is a cross-sectional view of an embodiment of the present invention after the cell dog has wiped the oxide layer.

[0066] Figure 8 A cross-sectional view of an embodiment of the present invention after the shielding grid is prepared.

[0067] Fig. 9 This is a cross-sectional view of an embodiment of the present invention after the isolation dielectric body is prepared.

[0068] Fig.10 This is a cross-sectional view of an embodiment of the present invention after the gate oxide base layer is prepared.

[0069] Fig.11 A cross-sectional view of an embodiment of the present invention after the control gate is prepared.

[0070] Fig.12This is a cross-sectional view of an embodiment of the present invention after the insulating first dielectric layer is prepared.

[0071] Fig.13 This is a cross-sectional view of an embodiment of the present invention after the N+ source region is prepared.

[0072] Fig.14 This is a cross-sectional view of an embodiment of the present invention after the insulating second dielectric layer is prepared.

[0073] Fig.15 It is a cross-sectional view of an embodiment of the present invention after the insulating second dielectric layer is patterned.

[0074] Fig.16 This is a cross-sectional view of an embodiment of the present invention after the drain electrode metal is prepared.

[0075] Explanation of the accompanying drawings: 1-substrate, 2-epitaxial layer, 3-unit cell narrow trench, 4-shielding gate, 5-field oxide layer, 6-N+ enhancement layer, 7-isolation dielectric body, 8-P-type well region, 9-N+ source region, 10-insulating first dielectric layer, 11-insulating second dielectric layer, 12-electrode metal contact hole, 13-gate oxide layer, 14-drain electrode metal, 15-epitaxial first doped layer, 16-epitaxial second doped layer, 17-epitaxial third doped layer, 18-control gate, 19-P+ source contact region, 20-epitaxial base layer, 21-unit cell wide trench, 22-unit cell trench sidewall, 23-trench field oxide layer, 24-shielding gate filling hole, 25-gate oxide base layer. DETAILED DESCRIPTION

[0076] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0077] In order to effectively reduce the contact resistance and the conduction loss of the power semiconductor device, taking the first conductivity type as N type as an example, the present invention provides a power semiconductor device capable of reducing the contact resistance. Specifically, the power semiconductor device includes:

[0078] A semiconductor substrate having an N conductivity type;

[0079] The active region is distributed in the central area of ​​the semiconductor substrate, and includes a plurality of unit cell trenches, wherein a channel source region body is provided at least on one side of the unit cell trench, and the channel source region body includes a P-type well region 8 for forming a channel region and an N+ source region 9 adapted to be connected to the P-type well region 8;

[0080] The N+ source region 9 extends into the electrode metal contact hole 12 of the insulating dielectric layer, and the N+ source region 9 is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole 12, and the first electrode metal of the device is also electrically connected to the P-type well region 8;

[0081] The insulating dielectric layer is supported on the semiconductor substrate, and the insulating dielectric layer covers the notch of the cell trench, so as to separate the cell trench from the first electrode metal of the device by using the insulating dielectric layer.

[0082] Specifically, the power semiconductor device may be the MOSFET device, IGBT device or other types of power semiconductor devices mentioned above. The type of the power semiconductor device may be selected and determined according to the actual application scenario, etc. Figure 1~Figure 2 as well as Fig.16 1 shows an embodiment in which the power semiconductor device is a MOSFET device. In the figure, a drain electrode metal 14 is provided on the back of the semiconductor substrate. In this case, the drain electrode metal 14 can form the drain electrode of the MOSFET device. When the power semiconductor device is of other types, the corresponding structure can be determined according to the type of shielded gate power semiconductor device. For example, for an IGBT device, Figure 1~Figure 2 as well as Fig.16 The drain electrode metal 14 is replaced with a corresponding collector structure. At this time, the collector structure can be used to form the collector of the IGBT device. The form of the collector structure can be selected according to needs, based on the collector required for the IGBT device. Therefore, when the power semiconductor device is a MOSFET device or other type of power device other than the IGBT device, the specific situation of the power semiconductor device can be determined accordingly, and examples will not be given one by one here.

[0083] Power semiconductor devices are generally prepared on a semiconductor substrate. The semiconductor substrate can be made of existing commonly used semiconductor materials, such as silicon, silicon carbide and other materials. The material type of the semiconductor substrate can be selected according to needs. The conductivity type of the semiconductor substrate can be N-type. Of course, the conductivity type of the semiconductor substrate can also be P-type. The specific selection can be based on actual needs. In the embodiment of the present invention, the conductivity type of the semiconductor substrate is N-type as an example for specific description.

[0084] Generally, an active area is prepared in the central area of ​​a semiconductor substrate. The active area is also the functional area of ​​a power semiconductor device. The active area includes a number of cell grooves. Cells of the power semiconductor device can be formed by using the cell grooves in the active area. The cells in the active area are formed by using the cell grooves, and the functions of the cells are consistent with the existing ones. The cell grooves in the active area generally adopt the same form. In order to form a channel area, in one embodiment of the present invention, it is generally necessary to set a channel source region body on at least one side of the cell groove. For example, for a cell groove located at an edge position, the channel source region body can be set only on one side of the cell groove. Under normal circumstances, it is generally necessary to set a channel source region body on both sides of the cell groove. Specifically, the cell groove at the edge position may specifically include a cell groove adjacent to the terminal protection area. At this time, the channel source region body can be set only on the side of the cell groove away from the terminal protection area. It can be seen that the distribution of the channel source region body on the outside of the cell groove may be related to the position of the cell groove and the need to form a channel area, and examples will not be given one by one here.

[0085] For a channel source region body, it can generally include at least a P-type well region 8 and an N+ source region 9 adapted to be connected to the P-type well region 8. The P-type well region 8 and the N+ source region 9 should be in contact with the outer side wall of the corresponding cell trench. In order to reduce the contact resistance, in one embodiment of the present invention, the N+ source region 9 is extended into the electrode metal contact hole 12, and the electrode metal contact hole 12 penetrates the insulating dielectric layer. When the first electrode metal of the device is filled in the electrode metal contact hole 12, the first electrode metal of the device can not only make ohmic contact with the upper end surface of the N+ source region 9, but also make ohmic contact with the side surface of the N+ source region 9. It can be seen that the ohmic contact method between the first electrode metal of the device and the N+ source region 9 of the present invention can increase the contact area between the first electrode metal of the device and the N+ source region 9 compared with the prior art, thereby reducing the contact resistance.

[0086] In the above description, the upper end surface of the N+ source region 9 specifically refers to the upper surface of the N+ source region 9 entering the electrode metal contact hole 12; the side surface of the N+ source region 9 specifically refers to the side surfaces on both sides of the upper end surface of the N+ source region 9. For the upper end surface and side surfaces of the N+ source region 9, please refer to Figure 1 , Figure 2 and Fig.16 Further, it can be seen from the above description that the reduction of contact resistance of the present invention specifically refers to reducing the contact resistance between the first electrode metal of the device and the N+ source region 9. When the contact resistance is reduced, the on-resistance of the power semiconductor device can be reduced, thereby reducing the conduction loss of the power semiconductor device.

[0087] In addition, the first electrode metal of the device should generally be electrically connected to the P-type well region 8. The first electrode metal of the device can be used to form the front first electrode of the power semiconductor device. The situation of the front first electrode is related to the type of the power semiconductor device, etc. For example, when the power semiconductor device is a MOSFET device, the front first electrode is the source electrode of the MOSFET device. When the power tube semiconductor device is an IGBT device, the front first electrode is the emitter of the MOSFET device. When the power semiconductor device is of other types, the category of the front first electrode can be determined accordingly, and they are not listed one by one here.

[0088] In specific implementation, the insulating dielectric layer is supported on the semiconductor substrate, and the number of electrode metal contact holes 12 in the insulating dielectric layer should be no less than the number of channel source region bodies in the active region. Generally, the number of electrode metal contact holes 12 corresponds to the channel source region bodies one by one. At this time, one electrode metal contact hole 12 is used to correspond to one N+ source region 9, so that the first electrode metal of the device can be in ohmic contact with the N+ source region 9. The electrode metal contact hole 12 needs to pass through the insulating dielectric layer, and the insulating dielectric layer generally covers the notch of the cell trench. The insulating dielectric layer can be used to realize the spacing between the cell trench and the first electrode metal of the device. The situation of the insulating dielectric layer will be illustrated below.

[0089] In one embodiment of the present invention, in a cross section of the power semiconductor device, the N+ source region 9 is located above the P-type well region 8, and a plurality of P+ source contact regions 19 are arranged in the N+ source region 9, wherein:

[0090] The junction depth of the P+ source contact region 19 is not less than the junction depth of the N+ source region 9, so that the P+ source contact region 19 is in contact with the P-type well region 8;

[0091] When the first electrode metal of the device is in ohmic contact with the N+ source region 9 , the first electrode metal of the device is also in ohmic contact with the P+ source contact region 19 , and the first electrode metal of the device is electrically connected to the contacted P-type well region 8 through the P+ source contact region 19 .

[0092] Figure 1 , Figure 2 and Fig.16 1 is a cross-sectional view of an embodiment of a power semiconductor device, in which an N+ source region 9 is located above a P-type well region 8, and an embodiment is shown in which the N+ source region 9 is in contact with the P-type well region 8. As can be seen from the above description, the P-type well region 8 needs to be electrically connected to the first electrode metal of the device. In order to achieve electrical connection between the P-type well region 8 and the first electrode metal of the device, in an embodiment of the present invention, a plurality of P+ source contact regions 19 can be provided in the N+ source region 9. Figure 3FIG. 1 shows an embodiment of setting a P+ source contact region 19 in each N+ source region 9. In the figure, two P+ source contact regions 19 are distributed along the length direction of the N+ source region 9. The length direction of the N+ source region 9 should be consistent with the length direction of the cell trench. Therefore, Figure 1~Figure 3 The cell grooves in the are long strips; it is understandable that Figure 3 The top view mainly shows the relative position relationship between the insulating second dielectric layer 11, the N+ source region 9 and the P+ source contact region 19, and the structure of the first electrode metal of the device is not shown in the figure.

[0093] In specific implementation, the junction depth of the P+ source contact region 19 is not less than the junction depth of the N+ source region 9, so that the P+ source contact region 19 can contact the P-type well region 8 below. Preferably, the junction depth of the P+ source contact region 19 is greater than the junction depth of the N+ source region 9, so as to improve the reliability of the contact between the P+ source contact region 19 and the P-type well region 8. After the N+ source region 9 is prepared, the P+ source contact region 19 can be prepared in the N+ source region 9 by using ion implantation and other processes. Of course, the P+ source contact region 19 can also be prepared by other processes. The specific preparation process conditions and process can be selected according to needs, so as to prepare the P+ source contact region 19 and make the P+ source contact region 19 contact the P-type well region 8.

[0094] Specifically, when the first electrode metal of the device is in ohmic contact with the N+ source region 9, the first electrode metal of the device is also in ohmic contact with the P+ source contact region 19, and the first electrode metal of the device is electrically connected to the contacted P-type well region 8 through the P+ source contact region 19; therefore, after preparing the P+ source contact region 19, the contact hole process for the N+ source region 9 can be omitted, reducing the process cost, and ensuring the electrical connection between the first electrode metal of the device and the P-type well region 8.

[0095] In one embodiment of the present invention, the insulating dielectric layer includes an insulating first dielectric layer 10 and an insulating second dielectric layer 11 located on the insulating first dielectric layer 10, wherein:

[0096] The insulating first dielectric layer 10 is supported on the semiconductor substrate and corresponds to the notch of the cell trench, and the thickness of the insulating second dielectric layer 11 is greater than the thickness of the insulating first dielectric layer 10;

[0097] The electrode metal contact hole 12 penetrates the insulating second dielectric layer 11 , and the N+ source region 9 extends into the electrode metal contact hole 12 after passing through the insulating first dielectric layer 10 , and the N+ source region 9 is vertically distributed in the electrode metal contact hole 12 .

[0098] Figure 1 , Figure 2 and Fig.16An embodiment of the insulating dielectric layer is shown in FIG. 1 , in which the insulating dielectric layer includes an insulating first dielectric layer 10 and a second insulating dielectric layer 11, wherein the insulating first dielectric layer 10 is supported on the semiconductor substrate and can correspond to the notch of the cell trench, and the thickness of the insulating first dielectric layer 10 is generally less than the thickness of the insulating second dielectric layer 11. When the insulating dielectric layer includes the insulating first dielectric layer 10 and the insulating second dielectric layer 11, the electrode metal contact hole 12 passes through the insulating second dielectric layer 11, that is, the bottom of the electrode metal contact hole 12 is the insulating first dielectric layer 10, and the N+ source region 9 passes through the insulating first dielectric layer 10 and extends into the electrode metal contact hole 12.

[0099] In the cross section of the power semiconductor device, the N+ source region 9 is vertically distributed in the electrode metal contact hole 12. When the N+ source region 9 is vertically distributed, the N+ source region 9 is perpendicular to the plane where the first insulating dielectric layer 10 is located, and the height of the N+ source region 9 extending into the electrode metal contact hole 12 should be less than the depth of the electrode metal contact hole 12. Figure 1 , Figure 2 and Fig.16 As shown in the figure, after extending into the electrode metal contact hole 12, the surface of the N+ source region 9 corresponding to the inner wall of the electrode metal contact hole 12 forms the side of the N+ source region 9, and the surface of the N+ source region 9 away from the insulating first dielectric layer 10 forms the upper end surface of the N+ source region 9.

[0100] In one embodiment of the present invention, in the active region, the channel source region body between any two adjacent cell trenches is configured as a fin structure, wherein:

[0101] When the channel source region body is configured as a fin structure, only one P-type well region 8 and one N+ source region 9 are provided between two adjacent cell trenches, and the P-type well region 8 and the N+ source region 9 are in contact with the outer side walls of the cell trenches on both sides at the same time;

[0102] When the power semiconductor device is forward-conducting, a full inversion conduction channel is formed between two cell trenches based on the fin structure, and the width of the formed full inversion conduction channel does not exceed 100 nm.

[0103] Specifically, for any two adjacent cell trenches, the channel source region body between the cell trenches of the two cell trenches is configured as a fin structure, so that when the power semiconductor device is forward-conducted, a fully inverted conduction channel can be formed between the two cell trenches. It can be understood that when the channel region between the two cell trenches forms a fully inverted conduction channel, the channel width can be increased and the channel resistance can be reduced. At the same time, based on the quantum effect of the fin structure, the conduction channel can be deviated from the interface between the semiconductor substrate and the dielectric, reducing the scattering effect and interface state effect of carriers at the interface between the semiconductor substrate and the dielectric, thereby further reducing the channel resistance. The situation of the dielectric interface will be described in detail below.

[0104] Specifically, when a fully inverted conduction channel is formed between two cell trenches based on a fin structure, the width of the fully inverted conduction channel does not exceed 100 nm, and thus, the distance between two adjacent cell trenches should be set to not exceed 100 nm, which can meet the requirement of forming a fully inverted conduction channel based on a fin structure. It can be seen that when the channel source region body is configured as a fin structure, the channel source region body should be distributed between two adjacent cell trenches.

[0105] Figure 1 , Figure 2 and Fig.16 , and , show an embodiment of configuring the channel source region body as a fin structure. In the figure, each fin structure includes a P-type well region 8 and an N+ source region 9, and the P-type well region 8 and the N+ source region 9 are in contact with the outer side walls of the cell trenches on both sides. At this time, on the cross section of the power semiconductor device, the corresponding widths of the P-type well region 8 and the N+ source region 9 do not exceed 100nm. It can be understood that when the channel source region body is configured as a fin structure, a P+ source contact region 19 can still be set in the fin structure, wherein the P+ source contact region 19 is set in the N+ source region 9.

[0106] In one embodiment of the present invention, any cell groove includes a cell wide groove 21 and a cell narrow groove 3 connected to the cell wide groove 21, wherein the width of the cell wide groove 21 is greater than the groove width of the cell narrow groove 3, and the groove bottom of the cell narrow groove 3 is located below the corresponding groove bottom of the cell wide groove 21;

[0107] For any two adjacent cell grooves, the cell-wide grooves 21 of the two cell grooves are exactly corresponding, and the fin structure is in contact with the outer sidewalls of the two cell-wide grooves 21;

[0108] When the power semiconductor device is forward-conducting, a full inversion conduction channel is formed between two cell-wide trenches 21 based on the fin structure.

[0109] Figure 1 , Figure 2 and Fig.16An embodiment of a cell groove is shown in FIG. 1 . In the figure, each cell groove includes a cell wide groove 21 and a cell narrow groove 3 . On the cross section of the power semiconductor device, the width of the cell wide groove 21 is greater than the width of the cell narrow groove 3, and the cell wide groove 21 is connected to the cell narrow groove 3. Specifically, the notch of the cell narrow groove 3 corresponds to the bottom of the cell wide groove 21, and the bottom of the cell narrow groove 3 is located directly below the cell wide groove 21, that is, the bottom of the cell narrow groove 3 points to the direction of the notch of the cell narrow groove 3, which is consistent with the direction in which the bottom of the cell wide groove 21 points to the notch of the cell wide groove 21. In addition, the cell wide groove 21 and the corresponding connected cell narrow groove 3 are coaxially distributed; therefore, the bottom of the cell narrow groove 3 is the bottom of the entire cell groove, that is, the depth of the cell groove is the sum of the depth of the cell wide groove 21 and the depth of the cell narrow groove 3.

[0110] In the active area, for any two adjacent cell grooves, the cell wide grooves 21 of the two cell grooves are exactly corresponding, wherein the two cell wide grooves 21 are exactly corresponding, specifically referring to that the notches and the groove bottoms of the two cell wide grooves 21 are respectively aligned, at this time, the notches and the groove bottoms of the two cell narrow grooves 3 are also respectively aligned; at the same time, the cell wide grooves 21 of the two cell grooves are correspondingly adjacent, and the distance between the two cell wide grooves 21 is smaller than the distance between the two cell narrow grooves 3.

[0111] In one embodiment of the present invention, for any two adjacent cell grooves, a fin structure is set between the cell width grooves 21 of the two cell grooves, so that when the shielded gate power semiconductor device is forward-conducted, a fully inverted conduction channel can be formed between the two cell width grooves 21, and the fully inverted conduction channel, that is, the area between the two cell width grooves 21 can form a conductive channel, and the situation of forming a fully inverted conduction channel is consistent with the existing. It can be seen from the above description that when a fully inverted conduction channel is formed between the two cell width grooves 21, the channel width can be increased and the channel resistance can be reduced. In order to form a fin structure, for any two adjacent cell grooves, the distance between the corresponding cell width grooves 21 of the two cell grooves can be set to not more than 100nm, which can meet the requirements of forming a fully inverted conduction channel based on the fin structure.

[0112] In addition, the cell narrow groove 3 increases the groove depth of the cell groove, plays the role of a field plate, and thus can improve the withstand voltage of each cell groove. At this time, when the drain-source breakdown voltage remains unchanged, the cell size can be further reduced, and the characteristic resistance of the entire shielded gate power semiconductor device can be reduced. It can be seen that the conduction loss of the shielded gate power semiconductor device can be reduced.

[0113] When the distance between the cell wide grooves 21 is configured to be no more than 100nm and a fin structure is formed, in order to improve the withstand voltage of the cell grooves, in one embodiment of the present invention, the distance between the cell wide grooves 21 is configured to be no more than 100nm and a fin structure is formed, in order to improve the withstand voltage of the cell grooves, in one embodiment of the present invention, the ratio of the groove depth of the cell wide groove 21 to the groove depth of the cell narrow groove 3 can be less than 1:1.5, such as the ratio of the groove depth of the cell wide groove 21 to the groove depth of the cell narrow groove 3 can be 1:7~1:3, and the groove depth ratio between the cell wide groove 21 and the cell narrow groove 3 is based on the balance between satisfying the process conditions and the withstand voltage of the cell grooves. Specifically, the depth of the cell wide groove 21 refers to the distance between the groove opening of the cell wide groove 21 and the bottom of the cell wide groove 21. The depth of the cell narrow groove 3 can refer to the description of the depth of the cell wide groove 21, which will not be described in detail here.

[0114] In addition, the ratio of the width of the cell wide groove 21 to the width of the cell narrow groove 3 can be greater than 2:1. It should be noted that when the width of the cell narrow groove 3 is small, it is beneficial to reduce the drift region resistance of the shielded gate semiconductor device; but if the width of the cell narrow groove 3 is too narrow, the resistance of the shielding gate 4 in the cell narrow groove 3 will increase, thereby affecting the local field plate effect of the shielded gate semiconductor device, resulting in unstable local breakdown voltage, wherein the local field plate specifically refers to the area between the shielding gate metal contacts of the shielding gate 4. Specifically, in order to lead out the shielding gate 4, on the top-view plane of the shielding gate power semiconductor device, for each shielding gate 4, a shielding gate metal contact is set at both ends of the shielding gate 4. From the above description, it can be seen that the shielding gate contact metal is the above-mentioned device first electrode metal. Therefore, the ratio of the width of the cell-wide groove 21 to the width of the cell-narrow groove 3 can be selected according to actual needs, so as to achieve a balance between the process and the cell-wide groove withstand voltage. For example, the ratio of the width of the cell-wide groove 21 to the width of the cell-narrow groove 3 can be 3:1. It can be understood that the ratio of the groove width ratio is also related to the withstand voltage level of the shielded gate power semiconductor device. Specifically, the width of the cell-wide groove 21 and the cell-narrow groove 3 refers to Figure 1~Figure 2 as well as Fig.16 The width of a shielded gate power semiconductor device in a cross-sectional view.

[0115] In one embodiment of the present invention, an SGT cell structure is provided in each cell groove, wherein:

[0116] The SGT cell structure includes a control gate 18 located in a cell wide trench 21 and a shielding gate 4 located in a cell narrow trench 3, wherein:

[0117] The width of the control grid 18 is greater than the width of the shield grid 4, and the control grid 18 and the shield grid 4 are insulated and isolated from each other;

[0118] The control gate 18 is insulated and isolated from the sidewall of the cell wide trench 21 by the gate oxide layer 13;

[0119] The shield gate 4 is insulated and isolated from the sidewalls and bottom wall of the cell narrow trench 3 by the field oxide layer 5, and the field oxide layer 5 also covers the bottom wall and corresponding sidewalls of the upper cell wide trench 21;

[0120] The thickness of the field oxide layer 5 is greater than the thickness of the gate oxide layer 13;

[0121] The shield gate 4 is electrically connected to the first electrode metal of the device above the semiconductor substrate, the control gate 18 is electrically connected to the second electrode metal of the device above the semiconductor substrate, and the first electrode metal of the device is isolated from the second electrode metal of the second device.

[0122] It can be understood that when each cell groove is provided with an SGT cell structure, the power semiconductor device can form an SGT power semiconductor device. For the SGT power semiconductor device, the SGT cell structure should include a control gate 18 and a shielding gate 4. When a cell groove includes a cell wide groove 21 and a cell narrow groove 3, the SGT cell structure is distributed in the cell wide groove 21 and the cell narrow groove 3. The form of the SGT cell structure and the form distributed in the cell wide groove 21 and the cell narrow groove 3 can be referred to the following description.

[0123] In one embodiment of the present invention, the control gate 18 is filled in the cell wide trench 21, and the shielding gate 4 is filled in the cell narrow trench 3. Figure 1 , Figure 2 and Fig.16 As shown, the width of the control gate 18 is greater than the width of the shielding gate 4. The control gate 18 is isolated from the shielding gate 4 by the isolation dielectric body 7. The main body of the isolation dielectric body 7 is located in the cell narrow groove 3, and is mainly located in the notch area of ​​the cell narrow groove 3. Generally, the control gate 18 and the shielding gate 4 can both be made of conductive polysilicon, and of course, other commonly used conductive materials can also be used. The materials of the control gate 18 and the shielding gate 4 can be selected according to needs, and the material of the isolation dielectric body 7 is generally silicon dioxide or silicon nitride, etc., which can achieve insulation isolation.

[0124] As can be seen from the above description, the cell trench is separated from the first electrode metal of the device by an insulating dielectric layer, specifically, the first electrode metal of the device is separated from at least the control gate 18. In specific implementation, a gate oxide layer 13 is provided on the side wall of the cell wide groove 21, and the gate oxide layer 13 is generally a silicon dioxide layer. The control gate 18 is in contact with the gate oxide layer 13, so that the control gate 18 can be insulated and isolated from the side wall of the cell wide groove 21 through the gate oxide layer 13. Generally, the gate oxide layer 13 extends from the notch of the cell wide groove 21 to the bottom of the cell wide groove 21, but the height of the gate oxide layer 13 is less than the groove depth of the cell wide groove 21, so that the bottom area of ​​the cell wide groove 21 can be covered by the field oxide layer 5. Specifically, the above-mentioned dielectric interface is the contact interface between the gate oxide layer 13 and the P-type well region 8.

[0125] A field oxide layer 5 is provided in the cell narrow groove 3, and the field oxide layer 5 covers the inner wall of the cell narrow groove 3, that is, the field oxide layer 5 covers the side wall and the bottom wall of the cell narrow groove 3. In order to protect the bottom of the cell wide groove 21, it can be known from the above description that the field oxide layer 5 will at least cover the bottom of the cell wide groove 21. The protection of the bottom area of ​​the cell wide groove 21 by the field oxide layer 5 can prevent the shielded gate power semiconductor device from being concentrated at the bottom of the cell wide groove 21 when the electric field is reversely turned off, thereby achieving the purpose of further improving the withstand voltage of the cell groove.

[0126] In addition, in the cell-wide groove 21, the field oxide layer 5 also covers the sidewalls of the cell-wide groove 21 adjacent to the bottom of the groove, and the field oxide layer 5 entering the cell-wide groove 21 contacts the gate oxide layer 13, so that the sidewalls and bottom walls of the cell-wide groove 21 are covered with an oxide layer. In one embodiment of the present invention, the thickness of the field oxide layer 5 is greater than the thickness of the gate oxide layer 13, and the corresponding thicknesses of the field oxide layer 5 and the gate oxide layer 13 can be selected as needed to meet the working and withstand voltage requirements of the shielded gate power semiconductor device.

[0127] In order to form a shielding gate structure, in one embodiment of the present invention, the shielding gate 4 is electrically connected to the first electrode metal of the device, the control gate 18 is electrically connected to the second electrode metal of the device, and the first electrode metal of the device and the second electrode metal of the device are isolated from each other. It should be noted that the first electrode metal of the device and the second electrode metal of the device are not Figure 1~Figure 2 as well as Fig.16 As shown in the figure, the specific connection and matching mode between the first electrode metal of the device and the shielding gate 4, and the control gate 18 and the second electrode metal of the device can be consistent with the existing one.

[0128] In specific implementation, the first electrode metal of the device can be used to form the front first electrode of the shielded gate power semiconductor device, and the second electrode metal of the device can be used to form the front second electrode of the shielded gate power semiconductor device. The types of the front first electrode and the front second electrode are related to the type of the shielded gate power semiconductor device. For the case of the front first electrode, refer to the corresponding description above; for the front second electrode, when the power semiconductor device is an SGT MOSFET device, the front second electrode is the gate electrode of the SGT MOSFET device, and when the power semiconductor device is an SGT IGBT device, the front second electrode is the gate of the SGT IGBT device. When the power semiconductor device is of other types, the electrode types of the front first electrode and the front second electrode can be determined according to the type of the power semiconductor device, and they will not be listed one by one here.

[0129] In specific implementation, the P-type well region 8 generally crosses the active region, that is, the P-type well region 8 is distributed throughout the active region. Figure 1~Figure 2 and Fig.16 In the figure, the bottom of the P-type well region 8 is located above the bottom of the control gate 18. The bottom of the P-type well region 8 and the bottom of the control gate 18 specifically refer to the surface of the P-type well region 8 and the control gate 18 adjacent to the bottom of the cell narrow trench 3. The N+ source region 19 is located above the P-type well region 8, and the N+ source region 19 and the P-type well region 8 are in contact with the outer side walls of the cell wide trench 21 on both sides, that is, the N+ source region 19 and the P-type well region 8 are in contact with the corresponding gate oxide layer 13 in the cell wide trench 21.

[0130] In one embodiment of the present invention, the semiconductor substrate comprises a substrate 1 and an epitaxial layer 2 located on the substrate 1, wherein:

[0131] The epitaxial layer 2 is adjacent to the substrate 1, and the cell trench is prepared in the epitaxial layer 2;

[0132] The epitaxial layer 2 includes at least one epitaxial doping layer, wherein:

[0133] When the epitaxial layer 2 includes multiple epitaxial doped layers, the bottom of the cell trench is located in the epitaxial doped layer adjacent to the substrate 1 .

[0134] Generally, the semiconductor substrate in the power semiconductor device may include a substrate 1 and an epitaxial layer 2. The epitaxial layer 2 is located on the substrate 1. The corresponding conductivity types of the substrate 1 and the epitaxial layer 2 are consistent with the conductivity type of the semiconductor substrate, that is, both are N conductivity types. The doping concentration of the substrate 1 is generally greater than the doping concentration of the epitaxial layer 2, but the thickness of the epitaxial layer 2 is greater than the thickness of the substrate 1, and the thickness is the dimension of the substrate 1 pointing to the epitaxial layer 2. The epitaxial layer 2 is adjacent to the substrate 1, and the cell trench is generally prepared in the epitaxial layer 2.

[0135] In one embodiment of the present invention, the epitaxial layer 2 includes at least one epitaxial doped layer, and the number of epitaxial doped layers can be selected according to needs, such as Figure 1 , an embodiment in which the epitaxial layer 2 includes an epitaxial doping layer is shown. In this case, the doping concentrations of all regions in the epitaxial layer 2 are consistent. Figure 2 An embodiment in which the epitaxial layer 2 has three epitaxial doping layers is shown. Figure 2 In the embodiment, the two epitaxial doped layers are respectively a first epitaxial doped layer 15, a second epitaxial doped layer 16 and a third epitaxial doped layer 17, wherein the substrate 1, the first epitaxial doped layer 15, the second epitaxial doped layer 16 and the third epitaxial doped layer 17 are arranged in sequence.

[0136] In a specific implementation, when there are more than two epitaxial doping layers in the epitaxial layer 2, the multiple epitaxial doping layers can form at least three doping distribution areas, wherein the three doping distribution areas include a first doping distribution area, a second doping distribution area and a third doping distribution area, wherein the first doping distribution area, the second doping distribution area and the third doping distribution area are sequentially distributed along the direction in which the epitaxial layer 2 is executed by the substrate 1, therefore, the first doping distribution area is adjacent to the substrate 1, the second doping distribution area is adjacent to the first doping distribution area and the third doping distribution area, the doping concentration of the second doping distribution area is greater than the doping concentration of the first doping distribution area and the doping concentration of the third doping area, the junction of the second doping distribution area and the first doping area is located above the bottom of the shielding gate 4, the bottom of the shielding gate 4 is the end of the shielding gate adjacent to the bottom of the cell narrow trench 3; the bottom of the cell narrow trench 3 is located in the first doping distribution area.

[0137] It should be noted that the first doping distribution region, the second epitaxial doping distribution region, and the third epitaxial doping distribution region may all include at least one epitaxial doping layer. Optionally, the first doping distribution region and the third epitaxial doping distribution region only include one epitaxial doping region, and the second epitaxial doping distribution region may include one or more epitaxial doping layers. The number of epitaxial doping layers in the first doping distribution region, the second epitaxial doping distribution region, and the third epitaxial doping distribution region can be selected according to needs.

[0138] Figure 2 2 shows an embodiment in which the epitaxial layer 2 includes three epitaxial doping layers. In the figure, the three epitaxial doping layers are respectively a first epitaxial doping layer 15, a second epitaxial doping layer 16 and a third epitaxial doping layer 17, wherein the substrate 1, the first epitaxial doping layer 15, the second epitaxial doping layer 16 and the third epitaxial doping layer 17 are arranged in sequence.

[0139] Figure 2In the embodiment, when the epitaxial layer 2 includes the first epitaxial doping layer 15, the second epitaxial doping layer 16 and the third epitaxial doping layer 17, the first epitaxial doping region 3 can form a first doping distribution region, the second epitaxial doping layer 16 can form a second doping distribution region, and the third epitaxial doping layer 17 can form a third doping region, that is, Figure 2 An embodiment is shown in which the first doping distribution region, the second epitaxial doping distribution region, and the third epitaxial doping distribution region can all include an epitaxial doping layer.

[0140] Depend on Figure 2 As can be seen from the above description, the doping concentration of the second epitaxial doping layer 16 is greater than the corresponding doping concentrations of the first epitaxial doping layer 15 and the third epitaxial doping layer 17. The top surface of the third epitaxial doping layer 17 can form the top surface of the epitaxial layer 2, and the bottom surface of the third epitaxial doping layer 17 is located below the isolation dielectric layer 7. The bottom surface of the third epitaxial doping layer 17 is also the side surface of the third epitaxial doping layer 17 adjacent to the substrate 1.

[0141] In one embodiment of the present invention, by setting up a multi-layer epitaxial doping layer, the doping concentration distribution in the epitaxial layer 2 can be adjusted. Based on the doping concentration distribution of the epitaxial doping layer in the epitaxial layer 2, the withstand voltage of the active region can be improved while the drift resistance in the epitaxial layer 2 can be improved, thereby reducing the conduction loss of the shielded gate power semiconductor device.

[0142] Figure 1~Figure 2 In the embodiment, the bottom of the cell narrow groove 3 is located in the epitaxial layer 2, wherein: Figure 1 and Figure 2 In the embodiment, the bottom of the cell narrow groove 3 is located in the first epitaxial doping layer 15. When the epitaxial layer 2 uses other numbers of epitaxial doping layers, the distribution of the epitaxial doping layers and the corresponding relationship between the cell grooves can refer to the above description, and no further examples are given here.

[0143] In one embodiment of the present invention, an N+ enhancement layer 6 is further included in the active region, wherein:

[0144] The N+ enhancement layer 6 at least crosses the active area in the semiconductor substrate.

[0145] The bottom surface of the N+ enhancement layer 6 is not lower than the bottom of the cell-wide trench 21 , and the N+ enhancement layer 6 is in contact with the gate oxide layer 13 in the cell-wide trench 21 .

[0146] Figure 1~Figure 2 and Fig.16, an embodiment of providing an N+ enhancement layer 6 in the active region is shown, wherein the N+ enhancement layer 6 at least crosses the active region, that is, the N+ enhancement layer 6 can be distributed in the entire active region, and the doping concentration of the N+ enhancement layer 6 is greater than the doping concentration of the epitaxial layer 2. For example, when the epitaxial layer 2 adopts multiple epitaxial doping layers, the doping concentration of the N+ enhancement layer 6 is greater than the doping concentration of the adjacent epitaxial doping layer. Specifically: Figure 1 In the embodiment, the epitaxial layer 2 includes only one epitaxial doped layer, and in this case, the doping concentration of the N+ enhancement layer 6 is greater than the doping concentration of the epitaxial doped layer; Figure 2 In the embodiment, when the epitaxial layer 2 includes the first epitaxial doping layer 15 , the second epitaxial doping layer 16 and the third epitaxial doping layer 17 , the doping concentration of the N+ enhancement layer 6 is greater than the doping concentration of the third epitaxial doping layer 17 .

[0147] In a specific implementation, the N+ enhancement layer 6 is located above the epitaxial layer 2 and is adjacent to the corresponding epitaxial doping layer in the epitaxial layer 2. Figure 1 In the embodiment, the N+ enhancement layer 6 is in contact with the only epitaxial doped layer. Figure 2 In the embodiment, the N+ enhancement layer 6 contacts the third epitaxial doping layer 17. When the epitaxial layer 2 includes other number of epitaxial doping layers, the contact between the N+ enhancement layer 6 and the epitaxial layer 2 can refer to the description herein.

[0148] In addition, the bottom surface of the N+ enhancement layer 6 is not lower than the bottom of the cell-wide groove 21, the top surface of the N+ enhancement layer 6 is in contact with the P-type well region 8 above, and the top surface of the N+ enhancement layer 6 is in contact with the gate oxide layer 13 in the cell-wide groove 21. At this time, the N+ enhancement layer 6 can be used to reduce the JFET effect, thereby achieving the purpose of adjusting the electric field size of the active area and shielding the on-resistance of the gate power semiconductor device.

[0149] For the above-mentioned power semiconductor device, the present invention provides a method for preparing a power semiconductor device capable of reducing contact resistance, which is used to prepare the above-mentioned power semiconductor device, wherein the preparation method comprises:

[0150] A semiconductor substrate of N conductivity type is provided, and a front cell process is performed on the front surface of the semiconductor substrate to prepare an active area distributed in the central area of ​​the semiconductor substrate after the front cell process, wherein:

[0151] The active region includes a plurality of unit cell trenches, wherein a channel source region body is provided at least on one side of the unit cell trench, and the channel source region body region includes a P-type well region 8 for forming a channel region and an N+ source region 9 adaptively connected to the P-type well region 8;

[0152] The N+ source region 9 extends into the electrode metal contact hole 12 of the insulating dielectric layer, and the N+ source region 9 is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole 12, and the first electrode metal of the device is also electrically connected to the P-type well region 8 forming the channel region;

[0153] The insulating dielectric layer is supported on the semiconductor substrate, and the insulating dielectric layer covers the notch of the cell trench, so as to separate the cell trench from the first electrode metal of the device by using the insulating dielectric layer.

[0154] Specifically, the situation of the semiconductor substrate can refer to the above description, and the active area can be prepared by performing a front cell process on the semiconductor substrate. The situation of preparing the active area and the cell trenches in the active area can refer to the above description.

[0155] When the channel source region body is a fin structure, in one embodiment of the present invention, when performing front cell processing on the semiconductor substrate, the process includes:

[0156] Performing trench etching on the front surface of the semiconductor substrate to form a plurality of cell-wide trenches 21 in the semiconductor substrate;

[0157] Performing trench etching on the bottom of the cell wide trench 21 to prepare a plurality of cell narrow trenches 3 in the semiconductor substrate, wherein a cell trench is formed based on a cell narrow trench 3 and a cell wide trench 21 corresponding to the cell narrow trench 3, and for any cell trench, the notch of the cell narrow trench 3 corresponds to the bottom of the cell wide trench 21, and the cell narrow trench 3 is connected to the cell wide trench 21;

[0158] A cell groove oxide layer 23 is prepared in the cell groove, wherein the cell groove oxide layer 23 covers the corresponding inner walls of the cell wide groove 21 and the cell narrow groove 3;

[0159] Filling a shielding grid 4 in the above-mentioned cell narrow groove 3, wherein the shielding grid 4 is insulated and isolated from the inner wall of the cell narrow groove 3 by the cell groove oxide layer 23 in the cell narrow groove 3;

[0160] An isolation dielectric body 7 is prepared in the above-mentioned cell groove, and the corresponding cell groove oxide layer 23 in the cell wide groove 21 is removed to obtain a field oxide layer 5 located in the cell narrow groove 3, wherein the isolation dielectric body 7 is pressed on the shielding grid 4, and the field oxide layer 5 also covers the bottom wall of the cell wide groove 21 and the side wall adjacent to the bottom wall;

[0161] Prepare a gate oxide base layer 25, wherein the gate oxide base layer 25 at least covers the sidewalls of the cell width trench 21;

[0162] Filling the control gate 18 in the cell-wide trench 21, wherein the control gate 18 is insulated and isolated from the shielding gate 4 by the isolation dielectric 7, and is insulated and isolated from the sidewall of the cell-wide trench 21 by the gate oxide base layer 25, and the thickness of the control gate 18 is less than the depth of the cell-wide trench 21;

[0163] The gate oxide layer 25 is processed to obtain a gate oxide layer 13 corresponding to the control gate 18;

[0164] An insulating first dielectric layer 10 is prepared in the cell-wide trench 21, wherein the insulating first dielectric layer 10 covers the control gate 18 in the cell-wide trench 21, and the insulating first dielectric layer 10 is below the notch of the cell-wide trench 21;

[0165] A channel source region body is prepared on at least one side of the cell-wide trench 21, wherein when the channel source region body is a fin structure, the fin structure is at least distributed between adjacent cell-wide trenches 21 and is adaptively connected to adjacent cell-wide trenches 21 on both sides, and the fin structure includes a P-type well region 8 and an N+ source region 9 adaptively connected to the P-type well region 8, and an end of the N+ source region 9 is located above the insulating first dielectric layer 10;

[0166] Prepare an insulating second dielectric layer 11, and pattern the insulating second dielectric layer 11 to obtain at least a plurality of electrode metal contact holes 12 corresponding to the N+ source region 9, wherein the electrode metal contact holes 12 penetrate the insulating second dielectric layer 11, and the N+ source region 9 extends into the corresponding electrode metal contact holes 12;

[0167] A front electrode metal is prepared on the front side of the semiconductor substrate, wherein the prepared metal electrode includes a first device electrode metal and a second device electrode metal,

[0168] The first electrode metal of the device is filled in the electrode metal contact hole 12 and is in ohmic contact with the N+ source region 9, and is electrically connected to the shield gate 4 in each cell narrow trench 3 and the corresponding P-type well region 8 in the active region;

[0169] The second electrode metal of the device is electrically connected to the control gate 18 , and the second electrode metal of the device is insulated and isolated from the first electrode metal of the device.

[0170] Figure 4 to Figure 16 An embodiment of the preparation process of the present invention is shown, wherein: Figure 4~Figure 15 FIG. 2 shows an embodiment in which the channel source region body is a fin structure when performing the front cell process. Fig.16 An embodiment of preparing a back electrode structure is shown in the figure, and the preparation process of the present invention is specifically described below with reference to the figure.

[0171] Figure 4An embodiment of providing a semiconductor substrate is shown in FIG. 1 . In the figure, the semiconductor substrate includes a substrate 1 and an epitaxial base layer 20 located on the substrate 1. It can be understood that the epitaxial layer 2 mentioned above can be formed based on the epitaxial base layer 20. Figure 4 The semiconductor substrate in the embodiment of the present invention can use the surface of the epitaxial base layer 20 to form the front side of the semiconductor substrate, and use the surface of the substrate 1 to form the back side of the semiconductor substrate, wherein the front side and the back side of the semiconductor substrate are two corresponding surfaces of the semiconductor substrate.

[0172] Figure 5 FIG. 2 shows an embodiment after trench etching is performed on the front side of the semiconductor substrate. After the trench etching is performed, all the cell-width trenches 21 in the active area can be prepared at the same time. Figure 5 , an embodiment of preparing two cell-wide grooves 21 is shown. In the figure, the cell-wide grooves 21 extend vertically downward from the surface of the epitaxial substrate 20, and the notches of the cell-wide grooves 21 are located on the surface of the epitaxial substrate 20. In addition, adjacent cell-wide grooves 21 are separated by cell-wide groove sidewalls 22. It can be understood that the cell-wide groove sidewalls 22 are areas that have not been subjected to trench etching; the method and process of the trench etching process can be consistent with the existing ones, so as to be able to etch and form the cell-wide grooves 21 and the terminal wide grooves 27.

[0173] Figure 6 An embodiment of forming a cell narrow groove 3 by groove etching is shown in FIG. Specifically, in order to form a cell narrow groove 3, the groove bottom of the cell wide groove 21 needs to be groove etched to form a cell narrow groove 3 after the groove etching. It can be seen that the cell narrow groove 3 extends vertically downward from the groove bottom of the cell wide groove 21, and the groove bottom of the cell narrow groove 3 is located below the groove bottom of the cell wide groove 21. The groove width of the cell narrow groove 3 is smaller than the groove width of the cell wide groove 21. The notch of the cell narrow groove 3 corresponds to the groove bottom of the cell wide groove 21, and the cell narrow groove 3 is connected to the cell wide groove 21. Specifically, a cell groove is formed by using a cell wide groove 21 and a cell narrow groove 3 connected to the cell wide groove 21.

[0174] After the cell groove is prepared, the cell groove oxide layer 23 can be prepared in the cell groove by using the commonly used technical means in the technical field, such as Figure 7 As shown in the figure, the cell groove oxide layer 23 covers the corresponding inner walls of the cell wide groove 21 and the cell narrow groove 3; in specific implementation, the cell groove oxide layer 23 can be a silicon dioxide layer, which can be prepared by a thermal oxidation process or a deposition process. After the cell groove oxide layer 23 is prepared, a shielding gate filling hole 24 needs to be formed in the cell narrow groove 3. Of course, the shielding gate filling hole 24 is connected to the cell wide groove 21. Figure 7 In the embodiment, the cell trench oxide layer 23 also covers the cell trench sidewalls 22 .

[0175] The shielding grid 4 is filled in the cell narrow groove 3 by using the shielding grid filling hole 24. The shielding grid 4 can be directly filled in the cell narrow groove 3 by using the commonly used technical means in the technical field. It can be seen from the above description that the shielding grid 4 can be conductive polysilicon or other commonly used conductive materials. The height of the shielding grid 4 is generally smaller than the groove depth of the cell narrow groove 3, that is, when the shielding grid 4 is filled in the cell narrow groove 3, the upper end of the shielding grid 4 is located below the notch of the cell narrow groove 3. The shielding grid 4 is insulated and isolated from the inner wall of the cell narrow groove 3 by the cell groove oxide layer 33. It should be noted that the inner wall of the cell narrow groove 3 specifically includes the side wall and the bottom wall of the cell narrow groove 3. The inner wall of the present invention generally refers to the same meaning, and the specifics can all be referred to here.

[0176] In order to form the above-mentioned SGT cell structure, it is necessary to prepare an isolation dielectric body 7 in the cell groove, and remove the corresponding cell groove oxide layer 23 in the cell wide groove 21. In specific implementation, the isolation dielectric body 7 can be prepared in the cell groove, and then the corresponding cell groove oxide layer 23 in the cell wide groove 21 can be removed. Fig. 9 As shown in the figure, when the corresponding cell trench oxide layer 23 in the cell wide trench 21 is removed, the cell trench oxide layer 23 on the cell trench sidewall 22 is removed at the same time.

[0177] It should be noted that when the cell trench oxide layer 23 in the cell wide groove 21 is removed, the cell trench oxide layer 33 in the cell narrow groove 3 is retained. At this time, a field oxide layer 5 can be formed based on the cell trench oxide layer 23 retained in the cell narrow groove 3. From the above description, it can be seen that in order to protect the bottom of the cell wide groove 21, the field oxide layer 5 also covers the bottom wall of the cell wide groove 21 and the side wall adjacent to the bottom wall. The isolation dielectric body 7 is pressed on the shielding grid 4, such as Fig. 9 As shown, the isolation dielectric body 7 can be made of materials such as silicon dioxide or silicon carbide, and can be prepared by a process commonly used in the technical field. The isolation dielectric body 7 is in contact with the shielding gate 4 and the field oxide layer 5 .

[0178] In a specific implementation, the isolation dielectric material may be first filled in the cell wide groove 21, wherein the isolation dielectric material may fill the cell wide groove 21. At this time, the isolation dielectric material may also enter the cell narrow groove 3 and cover the shielding gate 4. Thereafter, the isolation dielectric material in part of the cell wide groove 21 and the cell groove oxide layer 23 may be removed. After the isolation dielectric material is removed, an isolation dielectric body 7 may be obtained. After the cell groove oxide layer 23 is removed, the side wall of the cell wide groove 21 may not be covered by the oxide layer, and the cell groove side wall 22 may not be covered by the cell groove oxide layer 23.

[0179] In specific implementation, commonly used technical means in the technical field can be used to remove the corresponding cell trench oxide layer 23 in the cell wide trench 21 and retain the corresponding cell trench oxide layer 33 in the cell narrow trench 3.

[0180] After the cell trench oxide layer 23 of the cell wide trench 21 is removed, a gate oxide layer 25 can be prepared on the sidewall of the cell wide trench 21 by a process commonly used in the technical field. For example, the gate oxide layer 25 can be prepared by thermal oxidation. The gate oxide layer 25 covers the sidewall of the cell wide trench 21. Fig.10 As shown, the thickness of the gate oxide layer 25 is generally smaller than the thickness of the field oxide layer 5 , and the gate oxide layer 25 is in contact with the field oxide layer 5 in the cell wide trench 21 ; in addition, the gate oxide layer 25 also covers the cell trench sidewall 22 .

[0181] The control gate 18 is filled in the cell-wide trench 21, wherein the thickness of the control gate 18 is less than the depth of the cell-wide trench 21. Fig.11 As shown, it can be known from the above description that the control gate 18 can be conductive polysilicon or other commonly used conductive materials. When the control gate 18 is filled in the cell wide groove 21, the control gate 18 is insulated and isolated from the shielding gate 4 by the isolation dielectric body 7, and is insulated and isolated from the side wall of the cell wide groove 21 by the gate oxide base layer 25, and is insulated and isolated from the bottom wall of the cell wide groove 21 by the field oxide layer 5 in the cell wide groove 21.

[0182] After the cell-wide trench 21 is filled with the control gate 18, an insulating first dielectric layer 10 is prepared in the cell-wide trench 21. When the first insulating dielectric layer 10 is prepared, the gate oxide base layer 25 above the control gate 18 needs to be removed to prepare a gate oxide layer 13 corresponding to the control gate 18. Fig.12 As shown in the figure, the insulating first dielectric layer 10 covers the control gate 18 in the cell-wide trench 21, and the insulating first dielectric layer 10 is below the notch of the cell-wide trench 21, that is, the sum of the thickness of the control gate 18 and the thickness of the insulating first dielectric layer 10 is less than the depth of the cell-wide trench 21. When a portion of the gate oxide layer 25 is removed, the gate oxide layer 25 on the cell trench sidewall 22 is also removed, and the method for removing the gate oxide layer 25 can be consistent with the existing method.

[0183] After preparing the insulating first insulating dielectric layer 10, a channel source region body can be prepared on at least one side of the cell width trench 21, and the channel source region body can be configured as a fin structure. When preparing the fin structure, an N+ enhancement layer 6 can be prepared. The specific preparation process is illustrated by example.

[0184] As can be seen from the above description, an N+ enhancement layer 6 can be prepared at least in the active area. In order to prepare the N+ enhancement layer 6, an N+ enhancement region can be formed on the upper part of the epitaxial base layer 20 by ion implantation. The doping concentration of the N+ enhancement region is greater than the doping concentration of the epitaxial base layer 20. The N+ enhancement region extends vertically downward from the surface of the epitaxial base layer 20. The N+ enhancement region vertically extends to the top of the cell width trench 21 and is located below the bottom of the gate oxide layer 13. In addition, after the N+ enhancement region is prepared, the epitaxial layer 2 can be formed in the area below the N+ enhancement region in the epitaxial base layer 20.

[0185] It can be understood that, in the active area, the N+ enhancement region is distributed in the area where the cell trench sidewall 22 is located. After the N+ enhancement region is prepared, the P-type well region 8 and the N+ source region 9 can be prepared by ion implantation, wherein the area where the P-type well region 8 is located is consistent with the N+ enhancement region, that is, distributed in the cell trench sidewall 22. Therefore, after the P-type well region 8 is prepared, the N+ enhancement layer 6 can be formed, as shown in FIG. Fig.13 As shown in the figure, the P-type well region 8 is distributed in the active area, the bottom surface of the P-type well region 8 is in contact with the N+ enhancement layer 6, the P-type well region 8 is in contact with the corresponding side walls of the cell width trench 21, and the bottom surface of the P-type well region 8 is located above the bottom surface of the control gate 18.

[0186] It can be seen from the above description that a fin structure can be formed based on the N+ source region 9 and the P-type well region 8. The fin structure is distributed at least on one outer side of the cell-wide groove 21. When a fully inverted conduction channel is formed, the fully inverted conduction channel needs to be located between two adjacent cell-wide grooves 21. Therefore, in order to form a fully inverted conduction channel, the width of the cell-wide groove sidewall 22 should not exceed 100nm. Specifically, the N+ source region 9 protrudes from the notch of the cell-wide groove 21, and the width of the N+ source region 9 is consistent with the width of the cell-wide groove sidewall 22.

[0187] Fig.13 In the figure, the end of the N+ source region 9 is located above the insulating first dielectric layer 10, and the junction of the N+ source region 9 and the P-type well region 8 is located below the insulating first dielectric layer 10. The above of the insulating first dielectric layer 10 is the direction of the insulating first dielectric layer 10 away from the substrate 1, and the below of the insulating first dielectric layer 10 is the direction of the insulating first dielectric layer 10 close to the substrate 1.

[0188] It should be noted that the thickness of the insulating first dielectric layer 10 is generally thin, such as less than 100 nm. Therefore, the thickness of the insulating first dielectric layer 10 does not meet the requirements of insulation isolation. After the N+ source region 9 is prepared, the insulating second dielectric layer 11 can be prepared. The insulating second dielectric layer 11 covers the insulating first dielectric layer 10 and the N+ source region 9, and generally the active region can be fully covered. Fig.14As shown in the figure, the N+ source region 9 extends into the insulating second dielectric layer 11. The thickness of the insulating second dielectric layer 11 may generally be not less than 400 nm. In addition, the insulating second dielectric layer 11 may be made of a material having a different etching selectivity from the insulating first dielectric layer 10, so that when the insulating second dielectric layer 11 is etched to form the electrode metal contact hole 12, the insulating first dielectric layer 10 may be used to protect the control gate 18 and the gate oxide layer 13.

[0189] Depend on Fig.14 As can be seen from the above description, the insulating second dielectric layer 11 can cover the N+ source region 9. In order to facilitate ohmic contact with the first electrode metal of the device, the insulating second dielectric layer 11 needs to be etched. The insulating second dielectric layer 11 can be etched by using existing commonly used technical means to obtain an electrode metal contact hole 12 exposing the N+ source region 9 after etching. The electrode metal contact hole 12 penetrates the insulating second dielectric layer 11. Since the etching selectivity of the insulating first dielectric layer 10 is different from the etching selectivity of the insulating second dielectric layer 11, the etching is stopped after the electrode metal contact hole 12 penetrating the insulating second dielectric layer 11 is obtained. Fig.15 As shown in the figure, at the interface of the power semiconductor device, the interface of the insulating second dielectric layer 11 above each insulating first dielectric layer 10 is a trapezoidal shape that is wide at the top and narrow at the bottom. At this time, the N+ source region 9 will extend into the electrode metal contact hole 12.

[0190] After the N+ source region 9 is prepared, P-type impurity ion implantation can be performed to prepare the P+ source contact region 19. The situation of the P+ source contact region 19 can refer to the above description; of course, P-type impurity ion implantation can also be performed after the electrode metal contact hole 12 is prepared. The specific preparation order can be selected according to needs, so as to prepare the P+ source contact region 19.

[0191] After the above process, a front electrode metal can be prepared on the front side of the semiconductor substrate, wherein the prepared metal electrode includes a first electrode metal of the device and a second electrode metal of the device. Specifically, the first electrode metal of the device is filled in the electrode metal contact hole 12, and is in ohmic contact with the N+ source region 9, and is electrically connected to the shielding gate 4 in each cell narrow trench 3 and the corresponding P-type well region 8 in the active region; the second electrode metal of the device is electrically connected to the control gate 18, and the second electrode metal of the device is insulated and isolated from the first electrode metal of the device.

[0192] In the specific implementation, the commonly used technical means in this technical field can be used to prepare the first electrode metal of the device and the second electrode metal of the device. The first electrode metal of the device and the second electrode metal of the device are used to form the first electrode on the front side of the device and the second electrode on the front side of the device. Please refer to the above description and will not be repeated here.

[0193] From the above description, it can be seen that the front cell process is completed, and then the back electrode process can be carried out. Fig.16 An embodiment of a back electrode structure prepared by a back electrode process is shown in FIG. In the figure, the back electrode structure includes a drain electrode metal 14, which covers the substrate 1 and is in ohmic contact with the substrate 1. As can be seen from the above description, the drain electrode metal 1 can be used to form a drain electrode of a power semiconductor device. When the shielded gate power semiconductor device is a power semiconductor device of other types, the corresponding back electrode structure can be prepared by the corresponding back electrode process, which will not be listed here one by one.

[0194] In addition, by Figure 5~Figure 16 It can be seen from the manufacturing process shown that the power semiconductor device shown based on the manufacturing process is Figure 1 The power semiconductor device shown in the figure is an embodiment in which there is only one epitaxial doped layer in the epitaxial layer 2. It can be understood that when there are multiple epitaxial doped layers in the epitaxial layer 2, the same front cell process and the preparation process of the back electrode structure can be used, that is, by providing the epitaxial base layer 20 of different semiconductor substrates, it can be achieved. Figure 2 The preparation of the corresponding shielded gate power semiconductor device will not be described in detail here.

Claims

1. A power semiconductor device capable of reducing contact resistance, characterized in that: The power semiconductor device comprises: A semiconductor substrate having a first conductivity type; The active region is distributed in the central area of ​​the semiconductor substrate and includes a plurality of unit cell trenches, wherein a channel source region body is provided at least on one side of the unit cell trench, and the channel source region body includes a second conductivity type well region for forming a channel region and a first conductivity type source region adaptively connected to the second conductivity type well region; The first conductive type source region extends into the electrode metal contact hole of the insulating dielectric layer, the first conductive type source region is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole, and the first electrode metal of the device is also electrically connected to the second conductive type well region, wherein when the first electrode metal of the device is filled in the electrode metal contact hole, the first electrode metal of the device is in ohmic contact with the upper end surface of the first conductive type source region and is also in ohmic contact with the side surface of the first conductive type source region; The insulating dielectric layer is supported on the semiconductor substrate, and the insulating dielectric layer covers the notch of the cell groove, so as to separate the cell groove from the first electrode metal of the device by the insulating dielectric layer; In the cross section of the power semiconductor device, the first conductive type source region is located above the second conductive type well region, and a plurality of second conductive type source contact regions are arranged in the first conductive type source region, wherein: The junction depth of the second conductivity type source contact region is not less than the junction depth of the first conductivity type source region, so that the second conductivity type source contact region is in contact with the second conductivity type well region; When the first electrode metal of the device is in ohmic contact with the first conductivity type source region, the first electrode metal of the device is also in ohmic contact with the second conductivity type source contact region, and the first electrode metal of the device is electrically connected to the contacted second conductivity type well region through the second conductivity type source contact region.

2. The power semiconductor device capable of reducing contact resistance according to claim 1, characterized in that: The insulating dielectric layer includes an insulating first dielectric layer and an insulating second dielectric layer located on the insulating first dielectric layer, wherein: The insulating first dielectric layer is supported on the semiconductor substrate and corresponds to the notch of the cell trench, and the thickness of the insulating second dielectric layer is greater than the thickness of the insulating first dielectric layer; The electrode metal contact hole penetrates the insulating second dielectric layer, the first conductive type source region passes through the insulating first dielectric layer and then extends into the electrode metal contact hole, and the first conductive type source region is vertically distributed in the electrode metal contact hole.

3. The power semiconductor device capable of reducing contact resistance according to any one of claims 1 to 2, characterized in that: In the active area, the channel source region body between any two adjacent cell trenches is configured as a fin structure, where: When the channel source region body is configured as a fin structure, only one well region of the second conductivity type and one source region of the first conductivity type are arranged between two adjacent cell trenches, and the well region of the second conductivity type and the source region of the first conductivity type are in contact with the outer side walls of the cell trenches on both sides at the same time; When the power semiconductor device is forward-conducting, a full inversion conduction channel is formed between two cell trenches based on the fin structure, and the width of the formed full inversion conduction channel does not exceed 100 nm.

4. The power semiconductor device capable of reducing contact resistance according to claim 3, characterized in that: Any cell groove includes a cell wide groove and a cell narrow groove connected to the cell wide groove, wherein the width of the cell wide groove is greater than the groove width of the cell narrow groove, and the groove bottom of the cell narrow groove is located below the corresponding groove bottom of the cell wide groove; For any two adjacent cell grooves, the cell-width grooves of the two cell grooves are in direct correspondence, and the fin structure is in contact with the outer sidewalls of the two cell-width grooves; When the power semiconductor device is forward-conducting, a full inversion conduction channel is formed between two cell-wide trenches based on the fin structure.

5. The power semiconductor device capable of reducing contact resistance according to claim 4, characterized in that: An SGT cell structure is set in each cell groove, where: The SGT cell structure includes a control gate located in a wide cell trench and a shielding gate located in a narrow cell trench, wherein: The width of the control grid is greater than the width of the shielding grid, and the control grid and the shielding grid are insulated and isolated from each other; The control gate is insulated and isolated from the sidewall of the wide trench of the cell where it is located by a gate oxide layer; The shielding gate is insulated and isolated from the sidewalls and bottom wall of the narrow trench of the unit cell where it is located by a field oxide layer, and the field oxide layer also covers the bottom wall and corresponding sidewalls of the wide trench of the unit cell above; The thickness of the field oxide layer is greater than the thickness of the gate oxide layer; The shielding gate is electrically connected to the first electrode metal of the device above the semiconductor substrate, the control gate is electrically connected to the second electrode metal of the device above the semiconductor substrate, and the first electrode metal of the device is isolated from the second electrode metal of the second device.

6. The power semiconductor device capable of reducing contact resistance according to claim 5, characterized in that: The active area also includes a first conductive type enhancement layer, wherein: The first conductive type enhancement layer at least crosses the active area in the semiconductor substrate. The bottom surface of the first conductive type enhancement layer is not lower than the bottom of the cell-wide trench, and the first conductive type enhancement layer is in contact with the gate oxide layer in the cell-wide trench.

7. The power semiconductor device capable of reducing contact resistance according to any one of claims 1 to 2, characterized in that: The semiconductor substrate comprises a substrate and an epitaxial layer located on the substrate, wherein: The epitaxial layer is adjacent to the substrate, and the cell trench is prepared in the epitaxial layer; The epitaxial layer includes at least one epitaxial doping layer, wherein: When the epitaxial layer includes multiple epitaxial doped layers, the bottom of the cell trench is located in the epitaxial doped layer adjacent to the substrate.

8. A method for preparing a power semiconductor device capable of reducing contact resistance, characterized in that: Used to prepare the power semiconductor device according to any one of claims 1 to 7 above, wherein the preparation method comprises: A semiconductor substrate of a first conductivity type is provided, and a front cell process is performed on the front side of the semiconductor substrate to prepare an active area distributed in the central area of ​​the semiconductor substrate after the front cell process, wherein: The active region includes a plurality of unit cell trenches, wherein a channel source region body is provided at least on one side of the unit cell trench, and the channel source region body includes a second conductive type well region and a first conductive type source region adaptively connected to the second conductive type well region; The first conductive type source region extends into the electrode metal contact hole of the insulating dielectric layer, the first conductive type source region is in ohmic contact with the first electrode metal of the device filled in the electrode metal contact hole, and the first electrode metal of the device is also electrically connected to the second conductive type well region in the channel region; The insulating dielectric layer is supported on the semiconductor substrate, and the insulating dielectric layer covers the notch of the cell groove, so that the cell groove and the insulating dielectric layer are insulated and spaced by the insulating dielectric layer.

9. The method for preparing a power semiconductor device capable of reducing contact resistance according to claim 8, characterized in that: When performing front cell processing on a semiconductor substrate, it includes: Performing trench etching on the front surface of the semiconductor substrate to form a plurality of cell-wide trenches in the semiconductor substrate; Performing trench etching on the bottom of the cell wide trench to prepare a plurality of cell narrow trenches in the semiconductor substrate, wherein a cell trench is formed based on a cell narrow trench and a cell wide trench corresponding to the cell narrow trench, and for any cell trench, the notch of the cell narrow trench corresponds to the bottom of the cell wide trench, and the cell narrow trench is connected to the cell wide trench; Preparing a cell groove oxide layer in the cell groove, wherein the cell groove oxide layer covers the corresponding inner walls of the cell wide groove and the cell narrow groove; Filling a shielding grid in the above-mentioned cell narrow groove, wherein the shielding grid is insulated and isolated from the inner wall of the cell narrow groove by the cell groove oxide layer in the cell narrow groove; An isolation dielectric body is prepared in the cell trench, and the corresponding cell trench oxide layer in the cell wide trench is removed to obtain a field oxide layer located in the cell narrow trench, wherein the isolation dielectric body is pressed on the shielding grid, and the field oxide layer also covers the bottom wall of the cell wide trench and the side wall adjacent to the bottom wall; Prepare a gate oxide layer, wherein the gate oxide layer at least covers the sidewalls of the cell wide trench; Filling a control gate in the cell-wide trench, wherein the control gate is insulated and isolated from the shielding gate by an isolation dielectric, and is insulated and isolated from the sidewall of the cell-wide trench by a gate oxide substrate, and the thickness of the control gate is less than the depth of the cell-wide trench; Processing the gate oxide base layer to obtain a gate oxide layer corresponding to the control gate; Preparing an insulating first dielectric layer in the cell-wide trench, wherein the insulating first dielectric layer covers the control gate in the cell-wide trench and the insulating first dielectric layer is below the notch of the cell-wide trench; A channel source region body is prepared outside the cell-wide trench, wherein when the channel source region body is a fin structure, the fin structure is at least distributed between adjacent cell-wide trenches and is adaptively connected to adjacent cell-wide trenches on both sides, the fin structure includes a second conductivity type well region and a first conductivity type source region adaptively connected to the second conductivity type well region, and an end of the first conductivity type source region is located above the insulating first dielectric layer; Preparing an insulating second dielectric layer, and patterning the insulating second dielectric layer to obtain at least a plurality of electrode metal contact holes corresponding to the first conductive type source regions, wherein the electrode metal contact holes penetrate the insulating second dielectric layer, and the first conductive type source regions extend into the corresponding electrode metal contact holes; A front electrode metal is prepared on the front side of the semiconductor substrate, wherein the prepared metal electrode includes a first device electrode metal and a second device electrode metal, The first electrode metal of the device is filled in the electrode metal contact hole and is in ohmic contact with the first conductive type source region, and is electrically connected to the shielding gate in each cell narrow trench and the corresponding second conductive type well region in the active region; The second electrode metal of the device is electrically connected to the control gate, and the second electrode metal of the device is insulated and isolated from the first electrode metal of the device.

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