Display screen drive control method, device, display equipment and medium based on FPGA

Abstract

The present application relates to the field of display technology, and provides a display screen drive control method, device, display equipment and medium based on FPGA. The present application initializes and configures the first configuration parameters of the display screen panel and the second configuration parameters of the drive control circuit through FPGA, generates display data according to the first configuration parameters and the content to be displayed; transmits the display data to the display screen panel in real time for display through the drive control circuit in a low-power transmission mode; during the display process, monitors the working state of the display screen panel in real time through FPGA; adjusts the second configuration parameters according to the working state of the display screen panel, and sends the adjusted second configuration parameters to the drive control circuit in real time to adjust the display of the display screen panel. The present application uses FPGA for initialization configuration and real-time monitoring of the display screen panel, and dynamically adjusts the configuration parameters of the drive control circuit according to actual conditions, thereby adjusting the display effect of the display screen panel and reducing power consumption.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display screen drive control method, device, display equipment and medium based on FPGA. Background Art

[0002] With the continuous development of science and technology, display screens, as an important interface for human-computer interaction, have been widely used in various fields. Traditional display screen driving control methods are usually driven based on fixed configuration parameters, resulting in high power consumption and poor display effects. Summary of the invention

[0003] In view of this, the present application provides a display screen drive control method, apparatus, display device and medium based on FPGA to solve the technical problem that driving the display screen based on fixed configuration parameters results in high power consumption and poor display effect.

[0004] The first aspect of the present application provides a display screen driving control method based on FPGA, the method comprising:

[0005] Initialize and configure the first configuration parameters of the display panel and the second configuration parameters of the drive control circuit through the FPGA;

[0006] generating display data according to the first configuration parameter and the content to be displayed;

[0007] The display data is transmitted to the display panel in real time for display in a low-power transmission manner through the drive control circuit;

[0008] During the display process, the working status of the display panel is monitored in real time through the FPGA;

[0009] The second configuration parameter is adjusted according to the working state of the display screen panel, and the adjusted second configuration parameter is sent to the drive control circuit in real time to adjust the display of the display screen panel.

[0010] Optionally, adjusting the second configuration parameter according to the working state of the display panel includes:

[0011] Dividing the display panel into a plurality of display units according to the content to be displayed;

[0012] Determining an actual driving voltage value corresponding to each of the display units;

[0013] Acquiring an expected driving voltage value corresponding to the working state;

[0014] Calculate the corresponding driving voltage adjustment coefficient according to each of the actual driving voltage values ​​and the expected driving voltage value;

[0015] Calculate a target driving voltage adjustment coefficient according to the plurality of driving voltage adjustment coefficients;

[0016] The second configuration parameter is adjusted according to the target driving voltage adjustment coefficient.

[0017] Optionally, generating display data according to the first configuration parameter and the content to be displayed includes:

[0018] Calculating the complexity of the content to be displayed;

[0019] Determine a resource allocation strategy according to the complexity and the first configuration parameter;

[0020] Allocating target resources for the content to be displayed according to the resource allocation strategy;

[0021] Display data is generated based on the content to be displayed using the target resource.

[0022] Optionally, when the content to be displayed is an image, calculating the complexity of the content to be displayed includes:

[0023] Performing edge detection on the image and calculating the number of edges;

[0024] Compressing the image and calculating the change in image size before and after compression;

[0025] The complexity of the content to be displayed is calculated according to the number of edges and the change amount.

[0026] Optionally, when the content to be displayed is a video, calculating the complexity of the content to be displayed includes:

[0027] Calculating intra-frame residuals and inter-frame residuals of the video;

[0028] The complexity of the content to be displayed is calculated according to the intra-frame residual and the inter-frame residual.

[0029] Optionally, when the content to be displayed is text, calculating the complexity of the content to be displayed includes:

[0030] Obtain the number of characters and text layout in the text;

[0031] The complexity of the content to be displayed is calculated according to the number of characters and the text layout.

[0032] Optionally, the method further includes:

[0033] Performing fault detection on the display panel;

[0034] When a failure of the display screen panel is detected, a switch is made to a spare display screen panel or an alarm is sounded.

[0035] A second aspect of the present application provides a display screen drive control device based on FPGA, the device comprising:

[0036] A configuration module, used for initializing and configuring a first configuration parameter of the display panel and a second configuration parameter of the drive control circuit through FPGA;

[0037] A generating module, used for generating display data according to the first configuration parameters and the content to be displayed;

[0038] A transmission module, used for transmitting the display data to the display panel in real time for display in a low-power transmission manner through the drive control circuit;

[0039] A monitoring module, used to monitor the working status of the display panel in real time through the FPGA during the display process;

[0040] The adjustment module is used to adjust the second configuration parameter according to the working state of the display panel, and send the adjusted second configuration parameter to the drive control circuit in real time to adjust the display of the display panel.

[0041] The third aspect of the present application provides a display device, including a memory, an FPGA, and a computer program stored in the memory and executable on the FPGA, wherein the FPGA implements the steps of the FPGA-based display screen drive control method when executing the computer program.

[0042] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the FPGA-based display screen drive control method.

[0043] The FPGA-based display screen drive control method, device, display device and medium provided in the embodiment of the present application, initializes and configures the first configuration parameters of the display screen panel and the second configuration parameters of the drive control circuit through the FPGA, generates display data according to the first configuration parameters and the content to be displayed; transmits the display data to the display screen panel in real time for display through the drive control circuit in a low-power transmission mode; during the display process, monitors the working state of the display screen panel in real time through the FPGA; adjusts the second configuration parameters according to the working state of the display screen panel, and sends the adjusted second configuration parameters to the drive control circuit in real time to adjust the display of the display screen panel. The present application uses FPGA to perform initialization configuration and real-time monitoring of the working state of the display screen panel, dynamically adjusts the configuration parameters of the drive control circuit according to actual conditions, thereby adjusting the display effect of the display screen panel, ensuring that the display screen panel can operate with the optimal configuration parameters when displaying different content or in different environments, and avoiding unnecessary power consumption. In addition, through the low-power transmission of display data, the energy loss during data transmission can be reduced, further reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a flow chart of a display screen driving control method based on FPGA shown in an embodiment of the present application;

[0045] Figure 2 It is a functional module diagram of a display screen drive control device based on FPGA shown in an embodiment of the present application;

[0046] Figure 3 It is a structural diagram of a display device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to be used as limitations to the present application. As used in the specification of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear indication to the contrary in the context. It should also be understood that the term "and / or" used in the present application refers to any or all possible combinations comprising one or more of the listed items.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0049] The FPGA-based display screen driving control method provided in the embodiment of the present application is executed by a display device, and accordingly, the FPGA-based display screen driving control device runs in the display device.

[0050] Figure 1 The flowchart of the display screen driving control method based on FPGA provided in the first embodiment of the present application is shown in FIG. The display screen driving control method based on FPGA specifically includes the following steps.

[0051] S11, initializing and configuring first configuration parameters of the display panel and second configuration parameters of the drive control circuit through FPGA.

[0052] FPGA (Field Programmable Gate Array) is a programmable digital logic device that allows users to define the functions of its internal logic circuits through programming.

[0053] After the system is powered on or reset, the FPGA loads the configuration data stored in the internal or external memory of the FPGA to initialize the display panel and the drive control circuit respectively.

[0054] During the FPGA initialization configuration process, the FPGA configures the first configuration parameters to match the basic physical characteristics and electrical parameters of the display panel by sending a specific initialization sequence or command to the display panel. After the FPGA completes the first configuration parameters of the display panel, it will further configure the second configuration parameters of the drive control circuit. The second configuration parameters are usually stored in the internal memory of the FPGA and can be adjusted through software or user input. The control signal that controls the display of the display panel can be generated by the digital logic circuit of the FPGA, or it can be converted into an analog signal through an interface circuit such as a digital to analog converter (DAC).

[0055] Optionally, the first configuration parameter includes a resolution, a refresh rate, and a color mode of the display panel. These parameters can be configured according to actual needs to achieve the best display effect.

[0056] Optionally, the second configuration parameters include output voltage, output current and operating frequency of the drive control circuit. By dynamically adjusting these parameters, flexible control of the working state of the display screen can be achieved.

[0057] S12: Generate display data according to the first configuration parameters and the content to be displayed.

[0058] The content to be displayed can be images, text, or videos from the CPU, GPU, or other data sources. It needs to be converted into a format suitable for display.

[0059] Based on the first configuration parameter, the FPGA converts the content to be displayed into final display data. The generated display data is sent to the display device through the output interface of the FPGA. The output interface can be a digital interface (such as HDMI, DisplayPort) or an analog interface (such as VGA, LVDS).

[0060] In an optional implementation, generating display data according to the first configuration parameter and the content to be displayed includes:

[0061] Calculating the complexity of the content to be displayed;

[0062] Determine a resource allocation strategy according to the complexity and the first configuration parameter;

[0063] Allocating target resources for the content to be displayed according to the resource allocation strategy;

[0064] Display data is generated based on the content to be displayed using the target resource.

[0065] The FPGA can calculate the complexity of the content to be displayed based on the resolution, frame rate, color depth, number and speed of dynamically changing parts of the image (such as moving objects), etc.

[0066] After determining the complexity and the first configuration parameter, the FPGA determines a resource allocation strategy based on the complexity and the first configuration parameter to dynamically allocate target resources for the content to be displayed, specifically determining which hardware resources (such as computing units, memory bandwidth, DMA channels, etc.) should be allocated to process the current content, and how to allocate these resources to optimize performance or power consumption.

[0067] The resources allocated by the FPGA according to the resource allocation strategy are used as target resources. After the resource allocation is completed, the FPGA will use the target resources to process the content to be displayed, such as rendering graphics, processing images, synthesizing text, and generating the final display data. In the above optional implementation, the FPGA dynamically adjusts the resource allocation according to the actual content complexity and the configuration parameters of the display panel, thereby reducing power consumption or improving the overall efficiency of the system as much as possible without sacrificing performance.

[0068] In an optional implementation, when the content to be displayed is an image, calculating the complexity of the content to be displayed includes:

[0069] Performing edge detection on the image and calculating the number of edges;

[0070] Compressing the image and calculating the change in image size before and after compression;

[0071] The complexity of the content to be displayed is calculated according to the number of edges and the change amount.

[0072] Edge detection is a common technique in image processing. It is used to detect areas in an image where brightness changes significantly. These areas usually correspond to the boundaries or outlines of objects. FPGAs can use different edge detection algorithms (such as Canny edge detection, Sobel edge detection, etc.) to detect edges in images and count the number of edges detected. The more edges there are, the more details and textures the image contains.

[0073] FPGA can compress images (such as JPEG, PNG and other formats) and calculate the size change of the image before and after compression. The compression ratio (i.e., the ratio of the original image size to the compressed image size) can reflect the redundancy and complexity of the image. If the image can achieve a high compression ratio during the compression process, it means that there is more redundant information in the image, that is, the complexity of the image is low; conversely, if the compression ratio is low, it means that the complexity of the image is high.

[0074] After obtaining the number of edges and the change in image size before and after compression, the FPGA can combine these two indicators to calculate the complexity of the image. The FPGA can pre-set different weights for the number of edges and the change in image size before and after compression, thereby performing weighted calculation based on the number of edges, image size before and after compression, and the corresponding weights to obtain the complexity.

[0075] Since the number of edges and the change in image size before and after compression may have different dimensions and ranges, it is necessary to first standardize these two indicators so that they can be compared and weighted on the same scale. Different weights are assigned to the number of edges and the compression change according to the characteristics of the image and application requirements. For example, if the application pays more attention to the details and texture of the image, a higher weight can be assigned to the number of edges; if more attention is paid to the redundancy and compression efficiency of the image, a higher weight can be assigned to the compression change. The standardized number of edges and the compression change are weighted and summed according to the assigned weights to obtain the complexity score. The complexity score can be used to indicate the complexity level of the image. The higher the score, the higher the complexity of the image; conversely, the lower the complexity score, the lower the complexity of the image.

[0076] In the above optional implementation, the FPGA can dynamically adjust the resource allocation strategy according to the complexity of the image to optimize the display effect and performance. For example, for images with higher complexity, the FPGA can allocate more computing resources and memory bandwidth for processing to ensure smooth display and high-quality output of the image; while for images with lower complexity, the FPGA can reduce resource allocation to reduce power consumption and cost.

[0077] In an optional implementation, when the content to be displayed is a video, calculating the complexity of the content to be displayed includes:

[0078] Calculating intra-frame residuals and inter-frame residuals of the video;

[0079] The complexity of the content to be displayed is calculated according to the intra-frame residual and the inter-frame residual.

[0080] Intra-frame residual refers to the difference between each pixel or pixel block and the referenced prediction value within a frame. Intra-frame residual can be calculated by transform coding (such as discrete cosine transform DCT). Intra-frame residual reflects the texture and detail information within the current frame. If the intra-frame residual is large, it means that the frame contains more high-frequency information, that is, the image has rich details and textures, and therefore has a higher complexity.

[0081] Inter-frame residual refers to the difference between corresponding pixels or pixel blocks between adjacent frames. Inter-frame residual can be calculated through motion estimation and compensation process. Inter-frame residual reflects the motion information between video frames. If the inter-frame residual is large, it means that the changes between adjacent frames are large, that is, the video contains more motion or dynamic changes, so the complexity is high.

[0082] After obtaining the intra-frame residual and inter-frame residual, different weights can be assigned to the intra-frame residual and the inter-frame residual, and weighted sum calculation can be performed. The weight assignment can be determined according to the application scenario and requirements. For example, if the application pays more attention to the motion information of the video, a higher weight can be assigned to the inter-frame residual; if the application pays more attention to the details and texture of the video, a higher weight can be assigned to the intra-frame residual.

[0083] In the above optional implementation, according to the calculated video complexity, the FPGA can dynamically adjust its resource allocation strategy. For videos with higher complexity, the FPGA can allocate more computing resources and memory bandwidth for processing to ensure smooth video playback and high-quality output; while for videos with lower complexity, the FPGA can reduce resource allocation to reduce power consumption and cost.

[0084] In an optional implementation, when the content to be displayed is text, calculating the complexity of the content to be displayed includes:

[0085] Obtain the number of characters and text layout in the text;

[0086] The complexity of the content to be displayed is calculated according to the number of characters and the text layout.

[0087] The more characters in a text, the longer the text is, and the more information it contains, which increases the complexity of processing and display.

[0088] Text layout includes multiple elements such as font, font size, line spacing, paragraph spacing, alignment, etc. Typographical elements not only affect the visual presentation of the text, but also indirectly reflect the complexity of the text. For example, a text that uses multiple fonts and font sizes may have a higher level of typographical complexity.

[0089] After obtaining the number of characters and the text layout, weighted sum calculations can be performed based on the number of characters and the text layout to obtain the complexity of the text.

[0090] The above optional implementation method can dynamically adjust resource allocation and processing strategies according to the calculated text complexity. For example, for text with higher complexity, more computing resources can be allocated to render and display the text to ensure that the text can be presented to the user clearly and accurately.

[0091] S13, transmitting the display data to the display panel in real time for display in a low-power transmission manner through the drive control circuit.

[0092] The driver control circuit is responsible for receiving display data from the central processing unit (CPU) or graphics processing unit (GPU) and converting it into a signal format suitable for the display panel to understand. At the same time, the driver control circuit also manages the power, brightness, contrast and other parameters of the display panel.

[0093] In order to reduce the overall power consumption of the system, the display data needs to be transmitted to the display panel for display in a low-power transmission mode. For example, differential signal transmission technology, such as LVDS (Low-Voltage DifferentialSignaling) or MIPI DSI (Mobile Industry Processor Interface Display SerialInterface), is used to reduce signal loss and noise interference during transmission, thereby reducing power consumption. Another example is to adjust the refresh rate of the display panel according to the dynamic changes of the display content to avoid unnecessary screen refreshes, thereby reducing power consumption.

[0094] In order to ensure smoothness and real-time display, the drive control circuit needs to transmit the display data to the display panel in real time.

[0095] The display panel receives signals from the drive control circuit and converts them into visible images or text.

[0096] S14, during the display process, the working status of the display panel is monitored in real time through the FPGA.

[0097] The FPGA monitors the working status of the display panel in real time by receiving feedback signals or sensor data from the display panel. The feedback signals or data may include temperature, brightness, contrast, pixel status, etc.

[0098] S15, adjusting the second configuration parameter according to the working state of the display screen panel, and sending the adjusted second configuration parameter to the driving control circuit in real time to adjust the display of the display screen panel.

[0099] The FPGA can determine whether the current working state of the display panel needs to be adjusted according to the working state of the display panel. If adjustment is required, the FPGA will calculate a new second configuration parameter value. The second configuration parameter value is various settings related to the performance of the display panel, such as gamma correction value, backlight control signal, pixel clock frequency, etc.

[0100] The FPGA adjusts the second configuration parameter according to the calculated new second configuration parameter value, and sends the adjusted second configuration parameter to the drive control circuit of the display panel in real time through an appropriate interface (such as LVDS, eDP, HDMI, etc.), and after sending the new parameter, the FPGA will continue to monitor the working status of the display panel. If the status does not improve as expected or new problems arise, the FPGA can further adjust the second configuration parameter value.

[0101] By adjusting the second configuration parameter according to the working state of the display screen panel and sending the adjusted second configuration parameter to the drive control circuit in real time, it helps to ensure that the display screen panel always maintains the best working state.

[0102] In an optional implementation, adjusting the second configuration parameter according to the working state of the display panel includes:

[0103] Dividing the display panel into a plurality of display units according to the content to be displayed;

[0104] Determining an actual driving voltage value corresponding to each of the display units;

[0105] Acquiring an expected driving voltage value corresponding to the working state;

[0106] Calculate the corresponding driving voltage adjustment coefficient according to each of the actual driving voltage values ​​and the expected driving voltage value;

[0107] Calculate a target driving voltage adjustment coefficient according to the plurality of driving voltage adjustment coefficients;

[0108] The second configuration parameter is adjusted according to the target driving voltage adjustment coefficient.

[0109] A display unit is a small area divided on a display panel for independently controlling display. The display panel can be divided into multiple display units according to the content to be displayed. Each display unit can be a collection of pixels or a collection of pixel blocks. When the content to be displayed is text, the display panel can be divided into multiple display units according to the paragraphs of the text, and one paragraph corresponds to one display unit. When the content to be displayed is an image or video, the image can be divided into areas of different complexity or characteristics, and one area corresponds to one display unit.

[0110] The actual driving voltage value is the actual voltage value when the driving circuit drives the display unit to work in the current state. A voltage detection circuit is integrated in the driving control circuit, and the voltage detection circuit is used to monitor the driving voltage in real time.

[0111] The expected driving voltage value refers to the expected voltage value that should be reached to drive each display unit to work normally. According to the mapping relationship between the current working state of the display panel, the specifications and performance parameters of the display panel, and the configuration parameters of the driving control circuit, the expected driving voltage value corresponding to the current working state is obtained. Among them, the pre-stored mapping relationship between the current working state of the display panel, the specifications and performance parameters of the display panel, and the configuration parameters of the driving control circuit is established by performing actual tests on multiple working states of the display panel to obtain performance data of the display panel under different working states, and based on this.

[0112] For each display unit, the difference between its actual driving voltage value and the expected driving voltage value is calculated, and the difference reflects the difference between the current driving voltage and the ideal state. If the difference is greater than the preset difference threshold, the driving voltage adjustment coefficient is calculated based on the difference. The driving voltage adjustment coefficient is used to guide how to adjust the actual driving voltage to approach the expected driving voltage. The driving voltage adjustment coefficient can be based on the ratio between the difference and the preset proportional factor (which can be a constant or a dynamic value based on the characteristics of the display unit), and the driving voltage adjustment coefficient is between -1 and 1. In an optional embodiment, the driving voltage adjustment coefficients corresponding to all display units can be averaged, or weighted averaged, to obtain the target driving voltage adjustment coefficient.

[0113] Determine the direction and magnitude of the adjustment based on the sign and size of the target drive voltage adjustment coefficient. If the target drive voltage adjustment coefficient is positive, it means that the drive voltage needs to be increased; if it is negative, it means that the drive voltage needs to be reduced. Calculate a new second configuration parameter value based on the current second configuration parameter value and the target drive voltage adjustment coefficient. For example, when the target drive voltage adjustment coefficient is 0.1 (indicating that the drive voltage needs to be increased by 10%), and the current voltage offset is 10V, then the new voltage offset can be 11V. Write the calculated new second configuration parameter value into the control system of the display panel to adjust the drive voltage.

[0114] According to the target driving voltage adjustment coefficient, the driving control circuit parameters of the display panel are adjusted, including clock signal configuration parameters, data signal configuration parameters and other parameters related to the working performance of the display panel, so that the performance of the display panel approaches the expected state. If the target driving voltage adjustment coefficient indicates that the driving voltage needs to be increased, then the clock frequency needs to be increased (i.e., the cycle needs to be reduced) and the transmission rate of the data signal needs to be increased to improve the response speed and data processing capability of the system. If the target driving voltage adjustment coefficient indicates that the driving voltage needs to be reduced and the transmission rate of the data signal needs to be reduced, then the clock frequency needs to be reduced (i.e., the cycle needs to be increased) to reduce energy consumption and heat generation.

[0115] After adjusting the configuration parameters of the drive control circuit, the actual drive voltage value of each display unit is re-determined, and the actual drive voltage value is compared with the expected drive voltage value to evaluate the adjustment effect. If the difference between the adjusted actual drive voltage value and the expected drive voltage value is still large, the working state of the display panel is re-monitored, and the configuration parameters of the drive control circuit are further adjusted according to the working state until the difference between the actual drive voltage value and the expected drive voltage value meets the preset threshold condition, thereby achieving continuous optimization and dynamic adjustment of the working state of the display panel.

[0116] In the above optional implementations, due to process differences that may exist during the manufacturing process, different areas of the display panel may have brightness or color uniformity problems. By dividing the display panel into multiple display units, the driving voltage of each display unit can be adjusted independently, which can compensate for these differences and achieve more accurate local brightness and contrast control. Local adjustment can not only improve the dynamic contrast of the display screen, but also optimize the performance of dark and bright areas, thereby improving the overall image quality, and reduce unnecessary energy waste. When displaying dark or black content, the brightness of the corresponding display unit can be reduced, thereby reducing energy consumption and heat generation. For units displaying bright content, the brightness can be maintained or increased to ensure the display effect.

[0117] In an optional embodiment, the method further comprises:

[0118] Performing fault detection on the display panel;

[0119] When a failure of the display screen panel is detected, a switch is made to a spare display screen panel or an alarm is sounded.

[0120] The FPGA performs fault detection on the display panel periodically or in real time, for example, checking key parameters of the display panel such as pixel integrity, backlight brightness, response time, temperature, etc.

[0121] The actual output of the display panel can be obtained through various sensors and special diagnostic software, and the actual output of the display panel can be compared with the expected output to determine whether there is a fault. When the actual output of the display panel exceeds the expected output, it is determined that the display panel has a fault.

[0122] When the FPGA detects an abnormality or fault in the display panel, it immediately triggers the corresponding fault handling mechanism, sends an alarm to the system, adjusts the parameters of the display panel to try to fix the problem, or switches to a spare display panel.

[0123] It can also record key information such as the time, location, type, and processing results of the fault, so as to analyze the cause of the fault and evaluate the system performance. A fault report is generated based on key information such as the time, location, type, and processing results of the fault, providing relevant personnel with the operating status and fault history of the display panel.

[0124] After the fault is repaired, it can automatically or manually restore to normal operation and restart monitoring the working status of the display panel to reduce system downtime or service interruption time caused by display panel failure and provide users with more stable and efficient display services.

[0125] Since the present application uses FPGA to perform initialization configuration and real-time monitoring of the working status of the display panel, it can dynamically adjust the configuration parameters of the drive control circuit according to the actual situation, thereby adjusting the display effect of the display panel, reducing power consumption while ensuring the display effect, and improving the energy efficiency ratio of the display. Since FPGA has a high degree of programmability and flexibility, it can quickly adjust and optimize the configuration parameters of the display panel according to different application scenarios and requirements. Therefore, the present application can be widely used in various types of display panels and display devices, and has strong adaptability and scalability.

[0126] Figure 2 It is a structural diagram of a display screen drive control device based on FPGA provided in an embodiment of the present application.

[0127] In some embodiments, the FPGA-based display screen drive control device 20 may include a plurality of functional modules composed of computer program segments. The computer programs of the various program segments in the FPGA-based display screen drive control device 20 may be stored in a memory of a display device and executed by at least one processor to execute (see Figure 1 Description) The function of display screen drive control based on FPGA.

[0128] In this embodiment, the FPGA-based display screen drive control device 20 can be divided into multiple functional modules according to the functions it performs. The functional modules may include: a configuration module 201, a generation module 202, a transmission module 203, a monitoring module 204, an adjustment module 205 and a switching module 206. The module referred to in this application refers to a series of computer program segments that can be executed by at least one processor and can complete fixed functions, which are stored in a memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0129] The configuration module 201 is used to initialize and configure the first configuration parameters of the display panel and the second configuration parameters of the drive control circuit through the FPGA;

[0130] The generating module 202 is used to generate display data according to the first configuration parameters and the content to be displayed;

[0131] Optionally, when the content to be displayed is an image, calculating the complexity of the content to be displayed includes:

[0132] Performing edge detection on the image and calculating the number of edges;

[0133] Compressing the image and calculating the change in image size before and after compression;

[0134] The complexity of the content to be displayed is calculated according to the number of edges and the change amount.

[0135] Optionally, when the content to be displayed is a video, calculating the complexity of the content to be displayed includes:

[0136] Calculating intra-frame residuals and inter-frame residuals of the video;

[0137] The complexity of the content to be displayed is calculated according to the intra-frame residual and the inter-frame residual.

[0138] Optionally, when the content to be displayed is text, calculating the complexity of the content to be displayed includes:

[0139] Obtain the number of characters and text layout in the text;

[0140] The complexity of the content to be displayed is calculated according to the number of characters and the text layout.

[0141] The transmission module 203 is used to transmit the display data to the display panel in real time for display in a low-power transmission manner through the drive control circuit;

[0142] The monitoring module 204 is used to monitor the working status of the display panel in real time through the FPGA during the display process;

[0143] The adjustment module 205 is used to adjust the second configuration parameter according to the working state of the display panel, and send the adjusted second configuration parameter to the drive control circuit in real time to adjust the display of the display panel.

[0144] Optionally, adjusting the second configuration parameter according to the working state of the display panel includes:

[0145] Dividing the display panel into a plurality of display units according to the content to be displayed;

[0146] Determining an actual driving voltage value corresponding to each of the display units;

[0147] Acquiring an expected driving voltage value corresponding to the working state;

[0148] Calculate the corresponding driving voltage adjustment coefficient according to each of the actual driving voltage values ​​and the expected driving voltage value;

[0149] Calculate a target driving voltage adjustment coefficient according to the plurality of driving voltage adjustment coefficients;

[0150] The second configuration parameter is adjusted according to the target driving voltage adjustment coefficient.

[0151] Optionally, generating display data according to the first configuration parameter and the content to be displayed includes:

[0152] Calculating the complexity of the content to be displayed;

[0153] Determine a resource allocation strategy according to the complexity and the first configuration parameter;

[0154] Allocating target resources for the content to be displayed according to the resource allocation strategy;

[0155] Display data is generated based on the content to be displayed using the target resource.

[0156] The switching module 206 is used to perform fault detection on the display panel; when a fault is detected on the display panel, the switching module 206 switches to a spare display panel or issues an alarm.

[0157] It should be understood that the various variations and specific embodiments of the FPGA-based display screen drive control method provided in the above embodiments are also applicable to the FPGA-based display screen drive control device in this embodiment. Through the detailed description of the aforementioned FPGA-based display screen drive control method, those skilled in the art can clearly understand the implementation process of the FPGA-based display screen drive control device in this embodiment. For the sake of brevity of the specification, it will not be described in detail here.

[0158] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, all or part of the steps of the FPGA-based display screen drive control method are implemented.

[0159] See also Figure 3 As shown, it is a schematic diagram of the structure of the display device provided in the third embodiment of the present application. In the preferred embodiment of the present application, the display device 3 includes a display panel 30, a memory 31, at least one processor 32 and at least one communication bus 33, a drive control circuit 34 and a programmable digital logic device (Field Programmable Gate Array, FPGA) 35. The display panel 30 adopts low-power display technology, such as OLED or e-paper. The display panel 30 is based on the FPGA drive control circuit 34 for display control. Those skilled in the art should understand that Figure 3 The structure of the display device shown does not constitute a limitation of the embodiments of the present application, and can be either a bus structure or a star structure. The display device 3 can also include more or less other hardware or software than shown in the figure, or a different component arrangement.

[0160] In some embodiments, the display device 3 is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application-specific integrated circuits, programmable gate arrays, digital processors, and embedded devices. The display device 3 may also include client devices, which include but are not limited to any electronic product that can interact with a client through a keyboard, mouse, remote control, touchpad, or voice-controlled device, such as a personal computer, tablet computer, smart phone, digital camera, etc.

[0161] It should be noted that the display device 3 is only an example, and other existing or future electronic products that are suitable for the present application should also be included in the protection scope of the present application and included here by reference.

[0162] In some embodiments, the memory 31 stores a computer program, and when the computer program is executed by the at least one processor 32, all or part of the steps in the FPGA-based display screen drive control method are implemented. The memory 31 includes a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data. Further, the computer-readable storage medium may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function, and the like.

[0163] In some embodiments, the at least one processor 32 is the control core (ControlUnit) of the display device 3, and uses various interfaces and lines to connect various components of the entire display device 3, and executes various functions and processes data of the display device 3 by running or executing programs or modules stored in the memory 31, and calling data stored in the memory 31. For example, when the at least one processor 32 executes the computer program stored in the memory, it implements all or part of the steps of the display screen drive control method based on FPGA described in the embodiment of the present application; or implements all or part of the functions of the display screen drive control device based on FPGA. The at least one processor 32 can be composed of an integrated circuit, for example, it can be composed of a single packaged integrated circuit, or it can be composed of multiple integrated circuits with the same function or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips.

[0164] In some embodiments, the at least one communication bus 33 is configured to realize the connection and communication between the memory 31 and the at least one processor 32. Although not shown, the display device 3 may also include a power supply (such as a battery) for powering each component. Preferably, the power supply may be logically connected to the at least one processor 32 through a power management device, so as to realize the functions of managing charging, discharging, and power consumption management through the power management device. The power supply may also include any components such as one or more DC or AC power supplies, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, etc. The display device 3 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0165] The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a display device (which can be a personal computer, a display device, or a network device, etc.) or a processor to execute part of the method described in each embodiment of the present application.

[0166] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0167] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Claims

1. A display screen driving control method based on FPGA, characterized in that: The method comprises: Initialize and configure the first configuration parameters of the display panel and the second configuration parameters of the drive control circuit through the FPGA; generating display data according to the first configuration parameter and the content to be displayed; The display data is transmitted to the display panel in real time for display in a low-power transmission manner through the drive control circuit; During the display process, the working status of the display panel is monitored in real time through the FPGA; adjusting the second configuration parameter according to the working state of the display panel, and sending the adjusted second configuration parameter to the drive control circuit in real time to adjust the display of the display panel; The step of generating display data according to the first configuration parameter and the content to be displayed includes: Calculating the complexity of the content to be displayed; Determine a resource allocation strategy according to the complexity and the first configuration parameter; Allocating target resources for the content to be displayed according to the resource allocation strategy; generating display data based on the content to be displayed using the target resource; Wherein, adjusting the second configuration parameter according to the working state of the display panel includes: Dividing the display panel into a plurality of display units according to the content to be displayed; Determining an actual driving voltage value corresponding to each of the display units; Acquiring an expected driving voltage value corresponding to the working state; Calculate the corresponding driving voltage adjustment coefficient according to each of the actual driving voltage values ​​and the expected driving voltage value; Calculate a target driving voltage adjustment coefficient according to the plurality of driving voltage adjustment coefficients; The second configuration parameter is adjusted according to the target driving voltage adjustment coefficient.

2. The display screen driving control method based on FPGA according to claim 1, characterized in that: When the content to be displayed is an image, the calculating the complexity of the content to be displayed includes: Performing edge detection on the image and calculating the number of edges; Compressing the image and calculating the change in image size before and after compression; The complexity of the content to be displayed is calculated according to the number of edges and the change amount.

3. The display screen driving control method based on FPGA according to claim 1, characterized in that: When the content to be displayed is a video, the calculating the complexity of the content to be displayed includes: Calculating intra-frame residuals and inter-frame residuals of the video; The complexity of the content to be displayed is calculated according to the intra-frame residual and the inter-frame residual.

4. The display screen driving control method based on FPGA according to claim 1, characterized in that: When the content to be displayed is text, the calculating the complexity of the content to be displayed includes: Obtain the number of characters and text layout in the text; The complexity of the content to be displayed is calculated according to the number of characters and the text layout.

5. The display screen driving control method based on FPGA according to claim 1, characterized in that: The method further comprises: Performing fault detection on the display panel; When a failure of the display screen panel is detected, a switch is made to a spare display screen panel or an alarm is sounded.

6. A display screen drive control device based on FPGA, characterized in that: The device is used to execute the display screen driving control method based on FPGA according to any one of claims 1 to 5, the device comprising: A configuration module, used for initializing and configuring a first configuration parameter of the display panel and a second configuration parameter of the drive control circuit through FPGA; A generating module, used for generating display data according to the first configuration parameters and the content to be displayed; A transmission module, used for transmitting the display data to the display panel in real time for display in a low-power transmission manner through the drive control circuit; A monitoring module, used to monitor the working status of the display panel in real time through the FPGA during the display process; The adjustment module is used to adjust the second configuration parameter according to the working state of the display panel, and send the adjusted second configuration parameter to the drive control circuit in real time to adjust the display of the display panel.

7. A display device, characterized in that: The method comprises a memory, an FPGA and a computer program stored in the memory and executable on the FPGA. When the FPGA executes the computer program, the steps of the FPGA-based display screen driving control method as claimed in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the display screen driving control method based on FPGA as claimed in any one of claims 1 to 5 are implemented.

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