A congestion-based FPGA layout method and device

Abstract

A congestion-based FPGA layout method and device can reasonably adjust the position of the layout block so that routing congestion will not be caused by signal aggregation in one place during routing, thus avoiding routing failure and making the layout of areas where signals are too dispersed more compact, thereby improving performance. The method includes: (1) evaluating congestion; (2) finding the optimal area of ​​congested blocks and non-congested blocks; (3) finding candidate positions of congested blocks and non-congested blocks; and (4) adjusting congested blocks and non-congested blocks.

Description

Technical Field

[0001] The present invention relates to the technical field of field programmable gate arrays (FPGAs) in digital integrated circuits, and in particular to a congestion-based FPGA layout method and a congestion-based FPGA layout device. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a general-purpose logic circuit, and is known as one of the three major general-purpose signal processing devices along with CPU and DSP.

[0003] Currently, FPGA has become an indispensable way to achieve digital circuits. It has obvious advantages in development cycle and programmable flexibility. Its application fields are becoming more and more extensive, involving communications, aerospace, medical, mathematical computing, image processing, consumer products and many other fields. In the FPGA CAD (Computer Aided Design) process, layout is usually done first and then routing. If the layout does not take congestion factors into consideration, it may cause routing congestion and routing failure. Therefore, an efficient and practical method based on congestion-driven layout is urgently needed. Summary of the invention

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide an FPGA layout method based on congestion, which can reasonably adjust the position of the layout block so that wiring congestion will not be caused by signal concentration in one place during wiring, thereby avoiding wiring failure and making the layout of areas where signals are too dispersed more compact, thereby improving performance.

[0005] The technical solution of the present invention is: the FPGA layout method based on congestion degree comprises the following steps:

[0006] (1) Congestion evaluation: According to formula (1),

[0007] (1)

[0008] The FPGA board is divided into n boxes, each of which contains multiple clusters. i represents the i-th box. represents all the nets passing through the i-th box, NW is the weight of the net, and its value is related to the number of pins of net m. HPWL is the half-circle length of the bounding box of net m. represents the number of pins of net m in the ith box, represents the total number of pins of net m, and simulates the congestion of box i by the total length of all nets passing through box i in box i;

[0009] (2) Finding the optimal area of ​​congested blocks and non-congested blocks: When a block is on the critical path, the area where the bounding box of the previous block and the next block on the critical path of the block is located is taken as the optimal area;

[0010] (3) Finding candidate locations for congested blocks and non-congested blocks: For congested blocks, search for locations whose congestion degree is less than their own congestion degree among the candidate locations as candidate locations; for non-congested blocks, search for locations whose congestion degree is greater than their own congestion degree among the candidate locations as candidate locations;

[0011] (4) Adjusting congested blocks and non-congested blocks: The order of adjustment is congested blocks first and non-congested blocks later. Congested blocks are adjusted in order from large to small according to the congestion degree, and non-congested blocks are adjusted in order from small to large according to the congestion degree. Each block looks for a position from the candidate positions to be placed or exchanged.

[0012] The present invention evaluates congestion, finds optimal areas of congested blocks and non-congested blocks, finds candidate positions of congested blocks and non-congested blocks, and adjusts congested blocks and non-congested blocks, so as to reasonably adjust the positions of layout blocks, so that wiring congestion will not be caused by signal aggregation in one place during wiring, wiring failure is avoided, and the layout of areas where signals are too dispersed can be more compact, thereby improving performance.

[0013] A congestion-based FPGA layout device is also provided, comprising:

[0014] An evaluation unit, which is configured to evaluate congestion: according to formula (1)

[0015] (1)

[0016] The FPGA board is divided into n boxes, each of which contains multiple clusters. i represents the i-th box. represents all the nets passing through the i-th box, NW is the weight of the net, and its value is related to the number of pins of net m. HPWL is the half-circle length of the bounding box of net m. represents the number of pins of net m in the ith box, represents the total number of pins of net m, and simulates the congestion of box i by the total length of all nets passing through box i in box i;

[0017] A first search unit is configured to search for optimal regions of a congested block and a non-congested block: when a block is on a critical path, an area where a bounding box formed by a previous block and a next block on the critical path where the block is located is located is taken as the optimal region;

[0018] A second searching unit is configured to search for candidate positions of congested blocks and non-congested blocks: for a congested block, a position whose congestion degree among the candidate positions is less than its own congestion degree is searched as a candidate position; for a non-congested block, a position whose congestion degree among the candidate positions is searched as a candidate position;

[0019] The adjustment unit is configured to adjust the congested blocks and the non-congested blocks: the adjustment order is congested blocks first and then non-congested blocks, the congested blocks are adjusted in sequence from large to small according to the congestion degree, and the non-congested blocks are adjusted in sequence from small to large according to the congestion degree, and each block finds a position from the candidate positions to be placed or exchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a congestion-based FPGA placement method according to the present invention is shown. DETAILED DESCRIPTION

[0021] like Figure 1 As shown, this congestion-based FPGA layout method includes the following steps:

[0022] (1) Congestion evaluation: According to formula (1),

[0023] (1)

[0024] Divide the FPGA board into n bins (bins in English), each of which contains multiple clusters (cluster in English is the size of the area that a layout block can occupy), i represents the i-th bin, represents all the nets passing through the i-th box, NW is the weight of the net, and its value is related to the number of pins of net m, HPWL is the half-circle length of the bounding box of net m, represents the number of pins of net m in the ith box, represents the total number of pins of net m, and simulates the congestion of box i by the total length of all nets passing through box i in box i;

[0025] (2) Find the optimal area of ​​congested blocks and non-congested blocks: When a block is on the critical path, the area where the bounding box of the previous block and the next block on the critical path is located is taken as the optimal area;

[0026] (3) Finding candidate locations for congested blocks and non-congested blocks: For congested blocks, search for locations whose congestion degree is less than their own congestion degree among the candidate locations as candidate locations; for non-congested blocks, search for locations whose congestion degree is greater than their own congestion degree among the candidate locations as candidate locations;

[0027] (4) Adjusting congested blocks and non-congested blocks: The order of adjustment is congested blocks first and non-congested blocks later. Congested blocks are adjusted in order from large to small according to the congestion degree, and non-congested blocks are adjusted in order from small to large according to the congestion degree. Each block looks for a position from the candidate positions to be placed or exchanged.

[0028] The present invention evaluates congestion, finds optimal areas of congested blocks and non-congested blocks, finds candidate positions of congested blocks and non-congested blocks, and adjusts congested blocks and non-congested blocks, so as to reasonably adjust the positions of layout blocks, so that wiring congestion will not be caused by signal aggregation in one place during wiring, wiring failure is avoided, and the layout of areas where signals are too dispersed can be more compact, thereby improving performance.

[0029] Preferably, in step (1), the blocks are sorted from large to small according to the congestion degree of each block, the j% most congested blocks are taken as the blocks in the congested area to be adjusted, and the k% least congested blocks are taken as the blocks in the non-congested area to be adjusted, and j and k are adjustable.

[0030] Preferably, in step (2), when the block is not on the critical path, all the nets connected to the block are traversed and their bounding boxes are calculated. The bounding box here is the bounding box after removing the block. For n nets, a horizontal set of bounding boxes is obtained ( (1), (1), (2), (2),... (n), (n)) and vertical aggregation ( (1), (1), (2), (2),... (n), (n))

[0031] (2)

[0032] (3)

[0033] (4)

[0034] (5)

[0035] The left boundary of the optimal region is calculated according to formula (2), the right boundary of the optimal region is calculated according to formula (3), the lower boundary of the optimal region is calculated according to formula (4), and the upper boundary of the optimal region is calculated according to formula (5). Finally, the region formed by the four boundaries is the optimal region of the block.

[0036] Preferably, in step (3), the candidate position complies with the legally available position for structural modeling, and the type is consistent with the type of the block.

[0037] Preferably, in step (4), after adjustment, according to formula (6) ,like <0, keep the adjusted result, otherwise reselect the position from the candidate positions until the first one that makes <0; if the entire candidate position is not found, <0, proceed to the next block adjustment;

[0038] (6)

[0039] Among them, ΔCost is the required cost growth rate, ΔTimingCost is the difference between the timing costs before and after adjustment, PreviousTimingCost is the timing cost before adjustment, ΔWiringCost is the difference between the wire length costs before and after adjustment, PreviousWiringCost is the wire length cost before adjustment, 0≤α≤1, α is used as a weight value to adjust the impact of the timing cost and wire length cost on the required ΔCost.

[0040] Preferably, in step (4), when all blocks to be adjusted are adjusted, the current round of adjustment is completed, and whether there is any block that has been adjusted is recorded during each round of adjustment. <0, if it exists, proceed to the next round of adjustment, otherwise end the adjustment.

[0041] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, CD, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a congestion-based FPGA layout device, which is usually represented in the form of functional modules corresponding to the steps of the method. The device includes:

[0042] An evaluation unit, which is configured to evaluate congestion: according to formula (1)

[0043] (1)

[0044] The FPGA board is divided into n boxes, each of which contains multiple clusters. i represents the i-th box. represents all the nets passing through the i-th box, NW is the weight of the net, and its value is related to the number of pins of net m. HPWL is the half-circle length of the bounding box of net m. represents the number of pins of net m in the ith box, represents the total number of pins of net m, and simulates the congestion of box i by the total length of all nets passing through box i in box i;

[0045] A first search unit is configured to search for optimal regions of a congested block and a non-congested block: when a block is on a critical path, an area where a bounding box formed by a previous block and a next block on the critical path where the block is located is located is taken as the optimal region;

[0046] A second searching unit is configured to search for candidate positions of congested blocks and non-congested blocks: for a congested block, a position whose congestion degree among the candidate positions is less than its own congestion degree is searched as a candidate position; for a non-congested block, a position whose congestion degree among the candidate positions is searched as a candidate position;

[0047] The adjustment unit is configured to adjust the congested blocks and the non-congested blocks: the adjustment order is congested blocks first and then non-congested blocks, the congested blocks are adjusted in sequence from large to small according to the congestion degree, and the non-congested blocks are adjusted in sequence from small to large according to the congestion degree, and each block finds a position from the candidate positions to be placed or exchanged.

[0048] Preferably, in the evaluation unit, the blocks are sorted from large to small according to the congestion degree of each block, the j% most congested blocks are taken as the blocks in the congested area to be adjusted, and the k% least congested blocks are taken as the blocks in the non-congested area to be adjusted, and j and k are adjustable.

[0049] Preferably, in the first search unit, when the block is not on the critical path, all the nets connected to the block are traversed and their bounding boxes are calculated. The bounding box here is the bounding box of the block removed. For n nets, a horizontal set of bounding boxes is obtained ( (1), (1), (2), (2),... (n), (n)) and vertical aggregation ( (1), (1), (2), (2),... (n), (n))

[0050] (2)

[0051] (3)

[0052] (4)

[0053] (5)

[0054] The left boundary of the optimal region is calculated according to formula (2), the right boundary of the optimal region is calculated according to formula (3), the lower boundary of the optimal region is calculated according to formula (4), and the upper boundary of the optimal region is calculated according to formula (5). Finally, the region formed by the four boundaries is the optimal region of the block.

[0055] Preferably, in the adjustment unit, after adjustment, according to formula (6) ,like <0, keep the adjusted result, otherwise reselect the position from the candidate positions until the first one that makes <0; if the entire candidate position is not found, <0, proceed to the next block adjustment;

[0056] (6)

[0057] Wherein, ΔCost is the cost growth rate required, ΔTimingCost is the difference between the timing costs before and after adjustment, PreviousTimingCost is the timing cost before adjustment, ΔWiringCost is the difference between the wire length costs before and after adjustment, PreviousWiringCost is the wire length cost before adjustment, 0≤α≤1, α is used as a weight value to adjust the impact of the timing cost and the wire length cost on the required ΔCost;

[0058] When all blocks to be adjusted are adjusted, the current round of adjustment is completed. During each round of adjustment, it is recorded whether there is <0, if it exists, proceed to the next round of adjustment, otherwise end the adjustment.

[0059] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A congestion-based FPGA layout method, characterized in that: It includes the following steps: (1) Congestion evaluation: According to formula (1), （1） The FPGA board is divided into n boxes, each of which contains multiple clusters. i represents the i-th box. represents all the nets passing through the i-th box, NW is the weight of the net, and its value is related to the number of pins of net m. HPWL is the half-circumference length of the bounding box of net m. represents the number of pins of net m in the ith box, represents the total number of pins of net m, and simulates the congestion of box i through the total length of all nets passing through box i in box i; (2) Finding the optimal area of ​​congested blocks and non-congested blocks: When a block is on the critical path, the area where the bounding box of the previous block and the next block on the critical path of the block is located is taken as the optimal area; (3) Finding candidate locations for congested blocks and non-congested blocks: For congested blocks, search for locations whose congestion degree is less than their own congestion degree among the candidate locations as candidate locations; for non-congested blocks, search for locations whose congestion degree is greater than their own congestion degree among the candidate locations as candidate locations; (4) Adjusting congested blocks and non-congested blocks: The order of adjustment is congested blocks first and non-congested blocks later. Congested blocks are adjusted in order from large to small according to the congestion degree, and non-congested blocks are adjusted in order from small to large according to the congestion degree. Each block looks for a position from the candidate positions to be placed or exchanged.

2. The FPGA layout method based on congestion according to claim 1, characterized in that: In the step (1), the blocks are sorted from large to small according to the congestion degree of each block, and the j% most congested blocks are taken as the blocks in the congested area to be adjusted, and the k% least congested blocks are taken as the blocks in the non-congested area to be adjusted, and j and k are adjustable.

3. The FPGA layout method based on congestion according to claim 2, characterized in that: In step (2), when the block is not on the critical path, all the nets connected to the block are traversed and their bounding boxes are calculated. The bounding box here is the bounding box of the block removed. For n nets, the horizontal set of bounding boxes is obtained ( (1), (1), (2), (2),... (n), (n)) and vertical aggregation ( (1), (1), (2), (2),... (n), (n)) （2） （3） （4） （5） The left boundary of the optimal region is calculated according to formula (2), the right boundary of the optimal region is calculated according to formula (3), the lower boundary of the optimal region is calculated according to formula (4), and the upper boundary of the optimal region is calculated according to formula (5). Finally, the region formed by the four boundaries is the optimal region of the block.

4. The FPGA layout method based on congestion according to claim 3, characterized in that: In the step (3), the candidate position complies with the legal available position for structural modeling, and the type is consistent with the type of the block.

5. The FPGA layout method based on congestion according to claim 4, characterized in that: In step (4), after adjustment, according to formula (6), ,like <0, keep the adjusted result, otherwise reselect the position from the candidate positions until the first one that makes <0; if the entire candidate position is not found, <0, proceed to the next block adjustment; （6） Among them, ΔCost is the required cost growth rate, ΔTimingCost is the difference between the timing costs before and after adjustment, PreviousTimingCost is the timing cost before adjustment, ΔWiringCost is the difference between the wire length costs before and after adjustment, PreviousWiringCost is the wire length cost before adjustment, 0≤α≤1, α is used as a weight value to adjust the impact of the timing cost and wire length cost on the required ΔCost.

6. The FPGA layout method based on congestion according to claim 5, characterized in that: In step (4), when all blocks to be adjusted are adjusted, the current round of adjustment is completed. During each round of adjustment, it is recorded whether there is <0, if it exists, proceed to the next round of adjustment, otherwise end the adjustment.

7. A congestion-based FPGA layout device, characterized in that: It includes: An evaluation unit, which is configured to evaluate congestion: according to formula (1) （1） The FPGA board is divided into n boxes, each of which contains multiple clusters. i represents the i-th box. represents all the nets passing through the i-th box, NW is the weight of the net, and its value is related to the number of pins of net m. HPWL is the half-circumference length of the bounding box of net m. represents the number of pins of net m in the ith box, represents the total number of pins of net m, and simulates the congestion of box i through the total length of all nets passing through box i in box i; A first search unit is configured to search for optimal regions of a congested block and a non-congested block: when a block is on a critical path, an area where a bounding box formed by a previous block and a next block on the critical path where the block is located is located is taken as the optimal region; A second searching unit is configured to search for candidate positions of congested blocks and non-congested blocks: for a congested block, a position whose congestion degree among the candidate positions is less than its own congestion degree is searched as a candidate position; for a non-congested block, a position whose congestion degree among the candidate positions is searched as a candidate position; The adjustment unit is configured to adjust the congested blocks and the non-congested blocks: the adjustment order is congested blocks first and then non-congested blocks, the congested blocks are adjusted in sequence from large to small according to the congestion degree, and the non-congested blocks are adjusted in sequence from small to large according to the congestion degree, and each block finds a position from the candidate positions to be placed or exchanged.

8. The FPGA layout device based on congestion according to claim 7, characterized in that: In the evaluation unit, the blocks are sorted from large to small according to the congestion degree of each block, the j% most congested blocks are taken as the blocks in the congested area to be adjusted, and the k% least congested blocks are taken as the blocks in the non-congested area to be adjusted, and j and k are adjustable.

9. The FPGA layout device based on congestion according to claim 8, characterized in that: In the first search unit, when the block is not on the critical path, all the nets connected to the block are traversed and their bounding boxes are calculated. The bounding box here is the bounding box of the block removed. For n nets, the horizontal set of bounding boxes is obtained ( (1), (1), (2), (2),... (n), (n)) and vertical aggregation ( (1), (1), (2), (2),... (n), (n)) （2） （3） （4） （5） The left boundary of the optimal region is calculated according to formula (2), the right boundary of the optimal region is calculated according to formula (3), the lower boundary of the optimal region is calculated according to formula (4), and the upper boundary of the optimal region is calculated according to formula (5). Finally, the region formed by the four boundaries is the optimal region of the block.

10. The FPGA layout device based on congestion according to claim 9, characterized in that: In the adjustment unit, after adjustment, according to formula (6) ,like <0, keep the adjusted result, otherwise reselect the position from the candidate positions until the first one that makes <0; if the entire candidate position is not found, <0, proceed to the next block adjustment; （6） Wherein, ΔCost is the cost growth rate required, ΔTimingCost is the difference between the timing costs before and after adjustment, PreviousTimingCost is the timing cost before adjustment, ΔWiringCost is the difference between the wire length costs before and after adjustment, PreviousWiringCost is the wire length cost before adjustment, 0≤α≤1, α is used as a weight value to adjust the impact of the timing cost and the wire length cost on the required ΔCost; When all blocks to be adjusted are adjusted, the current round of adjustment is completed. During each round of adjustment, it is recorded whether there is <0, if it exists, proceed to the next round of adjustment, otherwise end the adjustment.

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