Method, device and equipment for transmitting GTX high-speed data in poor channels

Abstract

The present invention provides a GTX high-speed data transmission method, device and equipment for a bad channel, comprising determining a 192-bit synchronization bit group, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data; inserting the 192-bit synchronization bit group between each payload data sent by the sending end; capturing the 192-bit synchronization bit group based on the exhaustive detection principle when the receiving end receives the payload data sent by the sending end; if the 192-bit synchronization bit group is captured, synchronization locking is performed, the 192-bit synchronization bit group is determined to be the starting position of the serial-to-parallel conversion, and data transmission is performed based on the starting position; if the 192-bit synchronization bit group is not captured, it is determined that a bad channel fails, and since the 192-bit synchronization bit group that does not belong to the payload data is used as the identifier of the starting position for identification, compared with simple binary identifier identification, the stability and accuracy of data transmission in the bad channel are guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a method for transmitting GTX high-speed data in a poor channel. Background Art

[0002] With the development of communication technology, the speed of communication is getting faster and faster, and the scale and complexity of communication equipment are getting higher and higher. A single board can no longer meet the needs of communication functions. In actual application, a single communication machine requires many boards to cooperate with each other to complete complex communication functions. Only by configuring multiple single machines can a fully functional communication system be built. These boards / single machines need to perform a large amount of high-speed data transmission with each other to achieve information exchange. In special and highly customized communication equipment, Field Programmable Gate Array (FPGA) has been widely used and is the core device of this type of communication equipment. FPGA is used for information processing and exchange in communication equipment. In order to meet the needs of high-speed data transmission between boards / equipment, most FPGA manufacturers have integrated high-speed data transmission components in their products, and after several generations of development, they have formed serialized and standardized products to meet various high-speed data transmission application requirements in different occasions.

[0003] The high-speed data transmission components of FPGA are very complex from structure to function. FPGA manufacturers will package their high-speed data components at different levels to reduce the difficulty of development, and these packages are provided in the form of IP. The IP provided by FPGA is easy to use, but it can often only be used under ideal conditions. It has the defects of rigid usage mode and high requirements for transmission media (channels). Under the condition of poor transmission channels, the use of standard IP has the risk of high bit error rate and high probability of disconnection in transmission data, which reduces the performance of the entire device and even the entire system. When high-speed interconnection is performed between boards / devices, the physical medium of the communication path has a great impact on the quality of the channel. The firmness of the connector and the bending and deformation of the cable will reduce the quality of the channel.

[0004] For IP packaged by the manufacturer, the starting bit of the serial-to-parallel conversion is mainly determined based on the header[1:0]bit (the first two bits of every 66 bits are 2'b01) interspersed in the binary stream data.

[0005] However, under poor channel conditions, bit errors are prone to occur, and using this condition to judge the start bit will result in misjudgment. The wrong start bit will cause confusion in all subsequent serial-to-parallel conversions, resulting in unknown and unrecoverable errors. Summary of the invention

[0006] The present invention provides a method, device and equipment for transmitting GTX high-speed data in a bad channel, so as to solve the defect in the prior art that the starting position judgment of data transmission in a bad channel is prone to error.

[0007] In a first aspect, the present invention provides a method for transmitting GTX high-speed data in a bad channel, comprising:

[0008] Determine a synchronization bit group with a length of 192 bits, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data;

[0009] Insert the 192-bit synchronization bit group between each payload data sent by the sending end;

[0010] When the receiving end receives the payload data sent by the sending end, the receiving end captures the 192-bit synchronization bit group based on the exhaustive detection principle;

[0011] If the 192-bit synchronization bit group is captured, synchronization locking is performed, the 192-bit synchronization bit group is determined as the starting position of the serial-to-parallel conversion, and data transmission is performed based on the starting position;

[0012] If the 192-bit synchronization bit group is not captured, it is determined that the bad channel fails.

[0013] According to a GTX high-speed data transmission method for a bad channel provided by the present invention, the 192-bit synchronization bit group is inserted between each payload data sent by the transmitting end, comprising:

[0014] The transmitting end uses the tx clock as the clock for firmware programming, and sends the 192-bit synchronization bit group during the idle period when no payload data is sent;

[0015] After the 192-bit synchronization bit group is sent, the payload data is sent;

[0016] When the 192-bit synchronization bit group is sent, it is carried out in sequence according to the bit width of the sending interface. When the data of the synchronization bit group is not enough for the sending bit width, the low bits are filled with 0.

[0017] According to a GTX high-speed data transmission method for a bad channel provided by the present invention, the 192-bit synchronization bit group is captured based on the exhaustive detection principle, including:

[0018] Determine the 192-bit wide capture variable;

[0019] At each tx clock, the captured variable is controlled to shift leftward by the receiving bit width and then the received data is filled into the low bit;

[0020] It is determined whether the captured variable after the left shift is the same as the 192-bit synchronization bit group. If they are the same, the 192-bit synchronization bit group is captured and locked.

[0021] According to a method for transmitting GTX high-speed data in a bad channel provided by the present invention, before determining the variable with a 192-bit width, the method further includes:

[0022] Determining the frame length, transmission bit width and reception bit width of the transmitting end;

[0023] Determine a synchronous reception flag variable based on the frame length, the transmission bit width and the reception bit width;

[0024] Based on the synchronous reception flag variable, the 192-bit synchronous bit group is captured.

[0025] According to a GTX high-speed data transmission method for a bad channel provided by the present invention, the 192-bit synchronization bit group is captured based on the synchronization reception flag variable, including:

[0026] If the captured variable after the left shift is different from the 192-bit synchronization bit group, the synchronization reception flag variable is reduced by 1 every tx clock interval until the captured variable after the left shift is the same as the 192-bit synchronization bit group.

[0027] A method for transmitting GTX high-speed data in a bad channel provided by the present invention also includes:

[0028] If the captured variable is 0 and synchronization locking has not been performed, an adjustment pulse is output;

[0029] The start position of the propagation transition is adjusted by the adjustment pulse.

[0030] A method for transmitting GTX high-speed data in a bad channel provided by the present invention also includes:

[0031] If synchronization locking is not performed after sending the adjustment pulse 192 times, it is determined that the bad channel has a fault.

[0032] According to a method for transmitting GTX high-speed data in a bad channel provided by the present invention, the data transmission based on the starting position includes:

[0033] Based on the starting position, receiving the payload data of the sending end;

[0034] The payload data is descrambled and decoded and then outputted.

[0035] In a second aspect, the present invention further provides a transmission device for GTX high-speed data in a bad channel, comprising:

[0036] A determination module, used for determining a synchronization bit group with a length of 192 bits, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data;

[0037] An insertion module, used for inserting the 192-bit synchronization bit group between each payload data sent by the sending end;

[0038] A receiving module, configured to capture the 192-bit synchronization bit group based on an exhaustive detection principle when a receiving end receives the payload data sent by the sending end;

[0039] The capture module is used to perform synchronization locking if the 192-bit synchronization bit group is captured, determine that the 192-bit synchronization bit group is the starting position of the serial-to-parallel conversion, and perform data transmission based on the starting position; if the 192-bit synchronization bit group is not captured, determine that the bad channel has a fault.

[0040] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for transmitting GTX high-speed data in a poor channel as described in any one of the above is implemented.

[0041] In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described methods for transmitting GTX high-speed data in a poor channel.

[0042] In a fifth aspect, the present invention further provides a computer program product, comprising a computer program, which, when executed by a processor, implements any of the above-described methods for transmitting GTX high-speed data in a poor channel.

[0043] The present invention provides a method, device and equipment for transmitting GTX high-speed data in a bad channel. The method comprises the following steps: determining a 192-bit synchronization bit group, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data; inserting the 192-bit synchronization bit group between each payload data sent by the transmitting end; capturing the 192-bit synchronization bit group based on the exhaustive detection principle when the receiving end receives the payload data sent by the transmitting end; if the 192-bit synchronization bit group is captured, synchronization locking is performed, the 192-bit synchronization bit group is determined to be the starting position of the serial-to-parallel conversion, and data transmission is performed based on the starting position; if the 192-bit synchronization bit group is not captured, it is determined that a bad channel fails. Since the 192-bit synchronization bit group that does not belong to the payload data is used as the identifier of the starting position for identification and data synchronization is performed, compared with the simple binary 2'b01 identifier identification, the accuracy of the starting position identification can be better guaranteed, and the synchronization bit group will not be identified as the payload data, thereby ensuring the stability and accuracy of the data transmission in the bad channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 Schematic diagram of the GTX data transmission principle provided by this embodiment;

[0046] Figure 2 Schematic diagram of the GTX data receiving principle provided by this embodiment;

[0047] Figure 3 It is a flow chart of a method for transmitting GTX high-speed data in a bad channel provided by an embodiment of the present invention;

[0048] Figure 4 It is a schematic diagram of the structure of a transmission device for GTX high-speed data in a bad channel provided by an embodiment of the present invention;

[0049] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Figure 1 It is a schematic diagram of the GTX data transmission principle provided in this embodiment.

[0052] like Figure 1 As shown, the parallel port data is encoded, converted into a binary stream after parallel-to-serial conversion, and then converted into an electrical signal by a transmitting driver and sent out.

[0053] There are two types of encoding: one is 8B / 10B encoding, and the other is similar to 64B / 66B encoding (hereinafter referred to as 64B / 66B). High-speed data transmission generally uses 64B / 66B encoding. The purpose of encoding is to effectively extract valid payload data during the decoding process. The encoding process of 64B / 66B is as follows:

[0054] 64B / 66B adds a 2-bit header to every 64-bit data to form a data vector. The component that completes the encoding is called a gearbox, and the output of the gearbox is connected to the output of the transmit driver. The 64B / 66B encoded binary stream outputs 64 bits per tx clock, with the header encoding interspersed, and a large cycle of data every 33 tx clocks.

[0055] Figure 2 It is a schematic diagram of the GTX data receiving principle provided in this embodiment.

[0056] The input electrical signal is converted into a binary stream through data clock recovery (CDR), and the binary stream is converted into parallel data after serial-to-parallel conversion. It is then restored into 64-bit data and a 2-bit header by the 64B / 66B decoding module, and the data is output from the parallel data port.

[0057] At the receiving end, the bit stream interception position of the serial-to-parallel conversion (that is, determining which bit of the binary stream is the starting position B of the data) is determined by the head bit (2'b01) of 64B / 66B. Each large cycle of data transmission consists of 33 tx clocks, with a total of 66×32 data bits, bit[66n]=header[0]=1'b0, bit[66n+1]=header[1]=1'b1 (n=0-31).

[0058] Figure 3 It is a flow chart of a method for transmitting GTX high-speed data in a poor channel provided by an embodiment of the present invention.

[0059] like Figure 3 As shown, the method for transmitting GTX high-speed data in a bad channel provided by an embodiment of the present invention mainly includes the following steps:

[0060] 101. Determine a synchronization bit group with a length of 192 bits. The encoding of the synchronization bit group does not belong to the encoding of the payload data.

[0061] In a specific implementation process, in order to ensure accurate identification of the transmitted data, it is chosen to insert an identification mark, that is, a 192-bit synchronization bit group, between the payload data before sending the data. The encoding of the synchronization bit group does not belong to the encoding of the payload data, that is, the synchronization bit group will not appear in the data payload, thereby ensuring that as long as the synchronization bit group is identified, it is the starting position of the payload data. Compared with the existing conventional binary synchronization code, it can better ensure the accuracy of identifying the starting position of the payload data.

[0062] The values ​​of the 192-bit synchronization bit group are as follows:

[0063] sync_standard=192'h25D5C0CE8990F6C9461BF79CDA2A3F31766F0936B9E40863

[0064] The 192-bit synchronization bit group ensures the stability of data transmission under poor channels due to its uniqueness, and solves the problem that the existing binary identifier is prone to start position recognition errors during data transmission under poor channels.

[0065] 102. A 192-bit synchronization bit group is inserted between each payload data sent by the transmitter.

[0066] After the synchronization bit group is determined, before the transmitter sends the payload data, the transmitter uses the tx clock as the firmware programming clock and sends the 192-bit synchronization bit group in the idle period when no payload data is sent; when sending the 192-bit synchronization bit group, it is sent in sequence according to the bit width of the transmission interface. When the data of the synchronization bit group is not enough for the transmission bit width, the low bit is filled with 0. After the synchronization bit group is sent, the payload data is sent after a certain delay to ensure that at least one synchronization bit group is inserted between the payload data frames, so as to better separate the payload data for data decoding and recognition at the receiving end.

[0067] The transmitter sends synchronization bit groups when idle, so that the receiver can use the idle period to complete synchronization lock, avoiding the time cost and data loss of re-locking synchronization when sending data, making data reception more efficient.

[0068] 103. When the receiving end receives the payload data sent by the sending end, the receiving end captures the 192-bit synchronization bit group based on the exhaustive detection principle.

[0069] After the transmitter sends the data with the synchronization bit group inserted, the receiver receives the data. When receiving data, the exhaustive detection method is used to capture the synchronization, that is, the received data is monitored at all times to see if it is consistent with the inserted 192-bit synchronization bit group. If it is consistent, the capture is considered successful.

[0070] 104. If a 192-bit synchronization bit group is captured, synchronization locking is performed, the 192-bit synchronization bit group is determined as the starting position of the serial-to-parallel conversion, and data transmission is performed based on the starting position.

[0071] When the receiving end captures the 192-bit synchronization bit group, it performs synchronization locking, indicating that data synchronization is completed. At this time, the starting position of the serial-to-parallel conversion is accurately identified, and based on the starting position, the payload data of the sending end is received; after the payload data is descrambled and decoded, it is output.

[0072] When outputting data, ldpc7 / 8 encoding can be used when framing the array to reduce the bit error rate. You can also directly transmit data based on the bit error rate requirements if the data requirements are not high, such as audio, video data, AD sampling values, etc., to pursue a higher transmission speed.

[0073] 105. If the 192-bit synchronization bit group is not captured, it is determined that a bad channel fails.

[0074] If the 192-bit synchronization bit group is not captured after cyclic exhaustive detection, it indicates that there are other reasons that lead to the failure of data transmission, which also facilitates timely maintenance processing.

[0075] In poor channels where data recognition errors and unstable transmission are prone to occur, the 192-bit synchronization bit group that does not belong to the payload data is used as the starting position identifier for identification and data synchronization. Compared with the simple binary 2'b01 identifier identification, it can better ensure the accuracy of starting position identification and will not identify the synchronization bit group as payload data, thereby ensuring the stability and accuracy of data transmission in poor channels.

[0076] Furthermore, based on the above-mentioned embodiments, the present embodiment captures a 192-bit synchronization bit group based on the exhaustive detection principle, including: determining the frame length, transmission bit width and reception bit width of the transmitting end; based on the frame length, transmission bit width and reception bit width, determining the synchronization reception flag variable, setting it to sync_count, when sync_count is 0, it indicates synchronization loss, otherwise it is locked.

[0077] Then, determine the 192-bit wide capture variable sync_data, with an initial value of 192'h0; at each tx clock, control the capture variable sync_data to shift left by the receiving bit width and fill the received data into the low bit; at the same time, determine whether the captured variable sync_data after the left shift is the same as the 192-bit synchronization bit group. If they are the same, capture and lock the 192-bit synchronization bit group and reset sync_count.

[0078] If the captured variable after the left shift is different from the 192-bit synchronization bit group, the synchronization reception flag variable sync_count is reduced by 1 every tx clock interval until the captured variable after the left shift is the same as the 192-bit synchronization bit group, completing the synchronization lock.

[0079] Among them, a synchronous lock detection is performed every rx clock cycle. If the synchronous lock has not been performed after the capture variable is 0, the adjustment pulse rx_slip is output; the starting position of the transmission conversion is adjusted by the adjustment pulse, and the starting position of the serial-to-parallel conversion is adjusted, and the capture process of the same bit group is repeated. If the synchronous lock has not been performed after sending the adjustment pulse rx_slip 192 times, it is determined that the bad channel has failed, and other factors are checked to ensure the stability of data transmission. Among them, rx_slip is the input signal of the serial-to-parallel converter, which is used to adjust the starting position of the serial-to-parallel converter.

[0080] The present invention solves the synchronization problem of high-speed transmission under bad channel conditions without increasing any cost. On this basis, through redundant coding technology, the bit error rate is effectively reduced, the reliability and stability of GTX-based communication are improved, and the speed of inter-board communication and inter-device communication is increased. It can be conveniently used in satellite-borne equipment or ground equipment to replace the old-fashioned cable or optical fiber communication connection mode.

[0081] Based on the same general inventive concept, the present invention also protects a transmission device for GTX high-speed data in a poor channel. The transmission device for GTX high-speed data in a poor channel provided by the present invention is described below. The transmission device for GTX high-speed data in a poor channel described below and the transmission method for GTX high-speed data in a poor channel described above can be referenced to each other.

[0082] Figure 4 It is a schematic diagram of the structure of a transmission device for GTX high-speed data in a poor channel provided by an embodiment of the present invention.

[0083] like Figure 4 As shown, this embodiment provides a GTX high-speed data transmission device for a poor channel, including:

[0084] A determination module 401 is used to determine a synchronization bit group with a length of 192 bits, where the encoding of the synchronization bit group does not belong to the encoding of the payload data;

[0085] Insertion module 402, used for inserting a 192-bit synchronization bit group between each payload data sent by the sending end;

[0086] The receiving module 403 is used for capturing the 192-bit synchronization bit group based on the exhaustive detection principle when the receiving end receives the payload data sent by the sending end;

[0087] The capture module 404 is used to perform synchronization locking if a 192-bit synchronization bit group is captured, determine the 192-bit synchronization bit group as the starting position of the serial-to-parallel conversion, and perform data transmission based on the starting position; if the 192-bit synchronization bit group is not captured, determine that a bad channel fails.

[0088] Furthermore, the insertion module 402 in this embodiment is specifically used for:

[0089] The transmitting end uses the tx clock as the clock for firmware programming, and sends the 192-bit synchronization bit group during the idle period when no payload data is sent;

[0090] After the 192-bit synchronization bit group is sent, the payload data is sent;

[0091] When the 192-bit synchronization bit group is sent, it is carried out in sequence according to the bit width of the sending interface. When the data of the synchronization bit group is not enough for the sending bit width, the low bits are filled with 0.

[0092] Furthermore, the receiving module 403 in this embodiment is specifically used for:

[0093] Determine the 192-bit wide capture variable;

[0094] At each tx clock, the captured variable is controlled to shift leftward by the receiving bit width and then the received data is filled into the low bit;

[0095] It is determined whether the captured variable after the left shift is the same as the 192-bit synchronization bit group. If they are the same, the 192-bit synchronization bit group is captured and locked.

[0096] Furthermore, the receiving module 403 in this embodiment is specifically used for:

[0097] Determining the frame length, transmission bit width and reception bit width of the transmitting end;

[0098] Determine a synchronous reception flag variable based on the frame length, the transmission bit width and the reception bit width;

[0099] Based on the synchronous reception flag variable, the 192-bit synchronous bit group is captured.

[0100] Furthermore, the receiving module 403 in this embodiment is specifically used for:

[0101] If the captured variable after the left shift is different from the 192-bit synchronization bit group, the synchronization reception flag variable is reduced by 1 every tx clock interval until the captured variable after the left shift is the same as the 192-bit synchronization bit group.

[0102] Furthermore, the receiving module 403 in this embodiment is specifically used for:

[0103] If the captured variable is 0 and synchronization locking has not been performed, an adjustment pulse is output;

[0104] The start position of the propagation transition is adjusted by the adjustment pulse.

[0105] Furthermore, the receiving module 403 in this embodiment is specifically used for:

[0106] If synchronization locking is not performed after sending the adjustment pulse 192 times, it is determined that the bad channel has a fault.

[0107] Furthermore, the capture module 404 is specifically used for:

[0108] Based on the starting position, receiving the payload data of the sending end;

[0109] The payload data is descrambled and decoded and then outputted.

[0110] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0111] like Figure 5As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute a transmission method for GTX high-speed data in a bad channel, the method comprising: determining a 192-bit synchronization bit group, the encoding of which does not belong to the encoding of the payload data; inserting the 192-bit synchronization bit group between each payload data sent by the transmitting end; when the receiving end receives the payload data sent by the transmitting end, capturing the 192-bit synchronization bit group based on the exhaustive detection principle; if the 192-bit synchronization bit group is captured, performing synchronization locking, determining the 192-bit synchronization bit group as the starting position of the serial-to-parallel conversion, and performing data transmission based on the starting position; if the 192-bit synchronization bit group is not captured, determining that the bad channel has a fault.

[0112] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0113] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the GTX high-speed data transmission method provided by the above methods in a poor channel, the method including: determining a synchronization bit group with a length of 192 bits, the encoding of the synchronization bit group does not belong to the encoding of the payload data; inserting the 192-bit synchronization bit group between each payload data sent by the transmitting end; when the receiving end receives the payload data sent by the transmitting end, capturing the 192-bit synchronization bit group based on the exhaustive detection principle; if the 192-bit synchronization bit group is captured, performing synchronization locking, determining that the 192-bit synchronization bit group is the starting position of the serial-to-parallel conversion, and performing data transmission based on the starting position; if the 192-bit synchronization bit group is not captured, determining that the poor channel has failed.

[0114] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the GTX high-speed data transmission method for a poor channel provided by the above-mentioned methods, the method comprising: determining a synchronization bit group with a length of 192 bits, the encoding of the synchronization bit group not belonging to the encoding of the payload data; inserting the 192-bit synchronization bit group between each payload data sent by the transmitting end; when the receiving end receives the payload data sent by the transmitting end, capturing the 192-bit synchronization bit group based on the exhaustive detection principle; if the 192-bit synchronization bit group is captured, performing synchronization locking, determining the 192-bit synchronization bit group as the starting position of the serial-to-parallel conversion, and performing data transmission based on the starting position; if the 192-bit synchronization bit group is not captured, determining that the poor channel has failed.

[0115] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0116] Through the description of the above implementation modes, those skilled in the art can clearly understand that each implementation mode can be implemented by means of software plus a necessary general hardware platform, or of course by hardware. Based on such an understanding, the above technical solution can essentially or in other words be embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiment.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for transmitting GTX high-speed data in a bad channel, characterized in that: include: Determine a synchronization bit group with a length of 192 bits, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data; Inserting the 192-bit synchronization bit group between each payload data sent by the transmitting end; comprising: the transmitting end uses the tx clock as the clock for firmware programming, and sends the 192-bit synchronization bit group in an idle period when no payload data is sent; after the 192-bit synchronization bit group is sent, the payload data is sent; wherein, when sending the 192-bit synchronization bit group, the sending interface bit width is sequentially performed, and when the data of the sent synchronization bit group is not enough for the sending bit width, the low bit is filled with 0; When the receiving end receives the payload data sent by the transmitting end, the 192-bit synchronization bit group is captured based on the exhaustive detection principle, including: determining a capture variable with a width of 192 bits; at each tx clock, controlling the capture variable to shift left by the receiving bit width and then padding the received data into the low bit; judging whether the captured variable after the left shift is the same as the 192-bit synchronization bit group, and if they are the same, capturing and locking the 192-bit synchronization bit group; If the 192-bit synchronization bit group is captured, synchronization locking is performed, the 192-bit synchronization bit group is determined as the starting position of the serial-to-parallel conversion, and data transmission is performed based on the starting position; If the 192-bit synchronization bit group is not captured, it is determined that the bad channel fails.

2. The method for transmitting GTX high-speed data in a bad channel according to claim 1, characterized in that: Before determining the variable with a width of 192 bits, the method further includes: Determining the frame length, transmission bit width and reception bit width of the transmitting end; Determine a synchronous reception flag variable based on the frame length, the transmission bit width and the reception bit width; Based on the synchronous reception flag variable, the 192-bit synchronous bit group is captured.

3. The method for transmitting GTX high-speed data in a bad channel according to claim 2, characterized in that: The capturing of the 192-bit synchronization bit group based on the synchronization reception flag variable comprises: If the captured variable after the left shift is different from the 192-bit synchronization bit group, the synchronization reception flag variable is reduced by 1 every tx clock interval until the captured variable after the left shift is the same as the 192-bit synchronization bit group.

4. The method for transmitting GTX high-speed data in a bad channel according to claim 3, characterized in that: Also includes: If the captured variable is 0 and synchronization locking has not been performed, an adjustment pulse is output; The start position of the propagation transition is adjusted by the adjustment pulse.

5. The method for transmitting GTX high-speed data in a bad channel according to claim 4, characterized in that: Also includes: If synchronization locking is not performed after sending the adjustment pulse 192 times, it is determined that the bad channel has a fault.

6. The method for transmitting GTX high-speed data in a bad channel according to any one of claims 1 to 5, characterized in that: The transmitting of data based on the starting position comprises: Based on the starting position, receiving the payload data of the transmitting end; The payload data is descrambled and decoded and then outputted.

7. A device for transmitting GTX high-speed data in a bad channel, characterized in that: include: A determination module, used for determining a synchronization bit group with a length of 192 bits, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data; The inserting module is used to insert the 192-bit synchronization bit group between each payload data sent by the transmitting end, including: the transmitting end uses the tx clock as the clock for firmware programming, and sends the 192-bit synchronization bit group in an idle period when no payload data is sent; after the 192-bit synchronization bit group is sent, the payload data is sent; wherein, when sending the 192-bit synchronization bit group, it is sequentially performed according to the bit width of the sending interface, and when the data of the sent synchronization bit group is not enough for the sending bit width, the low bit is filled with 0; A receiving module, used for capturing the 192-bit synchronization bit group based on the exhaustive detection principle when the receiving end receives the payload data sent by the transmitting end, including: determining a capture variable with a width of 192 bits; at each tx clock, controlling the capture variable to shift left by the receiving bit width and then padding the received data into the low bit; judging whether the captured variable after the left shift is the same as the 192-bit synchronization bit group, and if they are the same, capturing and locking the 192-bit synchronization bit group; The capture module is used to perform synchronization locking if the 192-bit synchronization bit group is captured, determine that the 192-bit synchronization bit group is the starting position of the serial-to-parallel conversion, and perform data transmission based on the starting position; if the 192-bit synchronization bit group is not captured, determine that the bad channel has a fault.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method for transmitting GTX high-speed data in a poor channel as described in any one of claims 1 to 6 is implemented.

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