IGBT chip multi-cell electrothermal coupling simulation method and system

Abstract

The present invention discloses a multi-cell electrothermal coupling simulation method and system for an IGBT chip. The method and system are based on the principle of a unit cell electrothermal coupling model, divide the IGBT chip into detailed partitions, divide the IGBT chip layer by layer based on the particularity of the IGBT structure under electrothermal coupling, and obtain a large-scale IGBT chip electrothermal coupling model by combining and applying multiple partitions to the electrothermal coupling model. The electrothermal coupling simulation of the IGBT chip under the condition of continuous changes in external voltage and current is realized through the multi-cell electrothermal coupling model. Compared with the finite element method, the present invention can obtain the detailed distribution of the surface temperature of a large-area chip changing with time and the detailed situation of the change of the internal current of the chip changing with time more quickly, and accurately simulate the electrothermal coupling characteristics of the chip.

Description

Technical Field

[0001] The invention relates to power electronic devices, in particular to an IGBT chip multi-cell electrothermal coupling simulation method and system. Background Art

[0002] As a mainstream power semiconductor device, the insulated gate bipolar transistor (IGBT) is widely used as a core fully controlled switch in power electronic devices. The IGBT chip achieves high current through a large number of cells connected in parallel. In order to increase the current capacity of the IGBT chip, designers usually increase the number of parallel cells and increase the chip area. However, with the increase in chip area, factors such as cell size and arrangement will significantly affect the switching synchronization and current uniformity of the parallel cells inside the IGBT chip. The uneven current distribution causes uneven power loss inside the chip and produces surface temperature distribution differences. The surface temperature difference will affect the gate threshold voltage of the cell, causing the cell turn-on and turn-off time to change, resulting in the cells that are turned on earlier to bear a larger current at the moment the chip is turned on, resulting in a dynamic current sharing problem. The uneven temperature distribution of the chip will also affect the current distribution of the cells inside the chip. The higher resistance in the high-temperature area makes the current passing through the cells in this area relatively small when they are turned on, resulting in a static current sharing problem. This will make some chips vulnerable to damage due to overcurrent and high temperature. At the same time, uneven current will cause inconsistent heat generation of the chip package, further increasing the thermal stress in the part where electrical stress is concentrated, greatly reducing chip reliability.

[0003] In order to avoid stress damage caused by normal operation of the device as much as possible, IGBT devices are usually used at a reduced rating in order to pursue stable operation in actual applications. By achieving more accurate simulation of IGBT devices, the stress limit of the device can be more accurately understood, so that IGBT devices with lower margins can be selected in actual applications to achieve similar operating stability and reduce engineering costs.

[0004] Currently, most chip electrothermal coupling simulations are done at the chip level. There is no cellular solution for large-scale cellular electrothermal coupling that can accurately reflect the detailed differences in surface temperature when the chip is working and the detailed internal current distribution differences caused by the temperature differences. The traditional chip electrothermal coupling simulation solution uses finite element simulation. On the one hand, finite element commercial software usually uses Ohm's law to solve the electrothermal coupling effect, which is only applicable to passive devices; on the other hand, in actual applications, the external voltage and current of IGBT chips often change dramatically, and finite element simulation commercial software is difficult to perform electrothermal coupling simulation on IGBT chips under continuous and drastic changes in external electrical conditions. In addition, compared with general area chips, IGBT chips have more serious current and heat sharing problems, so their need for electrothermal coupling simulation is more urgent. When finite element simulation is used to simulate larger area chips, its shortcomings of slow running speed and high consumption of computing resources will be further magnified. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an IGBT chip multi-cell electrothermal coupling simulation method and system to accurately simulate the electrothermal coupling characteristics of the chip in view of the deficiencies in the prior art.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: an IGBT chip multi-cell electrothermal coupling simulation method, comprising the following steps:

[0007] S1. Establish an electrothermal coupling model of the IGBT chip unit cell;

[0008] S2. According to the structural characteristics of the IGBT chip, the chip layer and the packaging part of the IGBT are partitioned respectively, and the chip layer and the packaging part partitions are simplified respectively; each partition of the packaging part in the final simplified partition result and all the chip partitions above the partition are regarded as a cell, and the electrothermal behavior of the cell is simulated using the IGBT unit cell electrothermal coupling model to obtain the IGBT chip multi-cell electrothermal coupling model;

[0009] S3. Use the multi-cell electrothermal coupling model of the IGBT chip to perform simulation, calculate the overall temperature distribution change of the IGBT chip through power loss heat generation and heat dissipation, calculate the changes of related temperature sensitive parameters at different positions in the IGBT chip layer based on the overall temperature distribution of the IGBT chip, and obtain the detailed surface temperature distribution and internal current distribution of the IGBT chip;

[0010] S4. Repeat step S3 to obtain detailed distribution results of the surface temperature and internal current of the IGBT chip at different times.

[0011] The present invention is based on the principle of the unit cell electrothermal coupling model. By dividing the IGBT chip into detailed partitions, the IGBT chip is partitioned layer by layer based on the particularity of the IGBT structure under electrothermal coupling, and a large-scale IGBT chip electrothermal coupling model is obtained by combining multiple partitions and applying them to the electrothermal coupling model. The electrothermal coupling simulation of the IGBT chip under the condition of continuous changes in external voltage and current is realized through the multi-cell electrothermal coupling model. Compared with the finite element method, the present invention can obtain the detailed distribution of large-area chip surface temperature changes over time and the detailed changes of the chip internal current over time more quickly, and accurately simulate the chip electrothermal coupling characteristics.

[0012] In step S1, the specific implementation process of establishing the electrothermal coupling model of the unit cell of the IGBT chip includes:

[0013] According to the structure and physical characteristics of the IGBT chip, the IGBT chip is divided into a chip layer, a solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer and a substrate; the solder layer, the upper copper layer, the ceramic layer, the lower copper layer, the substrate solder layer and the substrate are the packaging part;

[0014] Divide the cells in the chip layer into a MOS part and a base part;

[0015] Establishing electrothermal coupling models for the chip layer and the packaging part respectively;

[0016] The electrothermal coupling model of the chip layer and the electrothermal coupling model of the packaging part are combined to obtain an IGBT chip unit cell electrothermal coupling model.

[0017] In step S2, the specific implementation process of partitioning the chip layer of the IGBT chip includes:

[0018] The gate resistance network of the IGBT chip is equivalent to a rectangular resistance network, and the gate resistance value from the cell near the grid point to the gate pad is estimated based on the resistivity brought by the material properties of the gate resistance network and the position of the grid point of the rectangular resistance network; the IGBT chip is divided into multiple rectangular grids;

[0019] All rectangular grids are numbered one by one, and the resistance value of all cells in a single grid is the gate resistance value corresponding to the grid.

[0020] In step S2, the specific implementation process of partitioning the packaging part of the IGBT chip includes:

[0021] The package part is divided into cuboids of the same specifications, each of which contains a solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer, and a part of the substrate area;

[0022] The heat flux density of different layers in each partition of the package part is obtained, and the thermal resistance and heat capacity of different layers in each partition are calculated based on the heat flux density.

[0023] In step S2, the specific implementation process of simplifying the chip layer and the packaging part partitions respectively includes:

[0024] For the chip layer, the maximum and minimum values ​​of the gate resistance of the cell inside the IGBT chip are obtained, and the interval of the gate resistance of the IGBT cell is determined by the maximum and minimum values. The interval is divided into multiple small intervals of equal length, and the resistance value of each gate resistance is approximated to the resistance value corresponding to the midpoint of the interval according to the interval in which it is located, so as to obtain the simplified chip layer partitioning result;

[0025] For the packaging part, an IGBT with a gate pad located in the center of the chip is selected, and the intersection of the diagonals of the IGBT chip is taken as the center point. The trisection points are determined on the line segments from the center point to the four corners of the chip. Four trisection points close to the center are connected, and four trisection points far from the center are connected to obtain two rectangles. The two rectangles divide the chip into three areas. The area where the midpoint is located without the gate pad is called the first area, the part between the two rectangles is the second area, and the outermost part is the third area. The small cells in the first and second areas are merged so that the cell areas of the three areas are 16:4:1, and the simplified packaging part partitioning result is obtained.

[0026] After obtaining the simplified partition results, the packaging part partition results are taken as the main body, each packaging part partition and all chip partitions directly above the partition are regarded as a whole, and the unit cell electrothermal coupling model is established after obtaining all relevant electrothermal parameters of the whole. The above operation is repeated for each partition of the packaging part to obtain a multi-cell electrothermal coupling model; the relevant electrothermal parameters include: solder layer thermal resistance R solder , solder layer heat capacity C solder , Thermal resistance of upper copper layer R Cu_upper 、The heat capacity of the upper copper layer C Cu_upper , Ceramic layer thermal resistance R ceramic 、Ceramic layer heat capacity C ceramic , thermal resistance of lower copper layer R Cu_lower , heat capacity of lower copper layer C Cu_lower , Thermal resistance of substrate solder layer R bp_solder 、The heat capacity of the substrate solder layer C bp_solder 、Substrate thermal resistance R baseplate 、Substrate heat capacity C baseplate , hole current I pmos 、Electron current I nmos , displacement current I disp , collector current I C , MOS side depletion layer voltage V DS and gate voltage VGS .

[0027] Run the IGBT chip multi-cell electrothermal coupling model under the current temperature sensitive parameter conditions, calculate the current distribution and the corresponding power loss distribution at this time, substitute the power loss distribution at this moment into the different partitions of the IGBT chip multi-cell electrothermal coupling model, and obtain the detailed temperature distribution changes under the current power loss distribution. Use the detailed temperature distribution changes to calculate the temperature sensitive parameters at the current moment, and substitute the new temperature sensitive parameters into the IGBT chip multi-cell electrothermal coupling model to complete an electrothermal coupling model simulation run.

[0028] As an inventive concept, the present invention also provides an IGBT chip multi-cell electrothermal coupling simulation system, comprising a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the steps of the above method.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The present invention takes into account multiple factors to explain the uneven current phenomenon inside the chip and more accurately simulates the electrothermal coupling characteristics of the chip;

[0031] 2. Compared with traditional finite element calculation, the present invention uses a 3-D thermal network model, which has a fast calculation speed and occupies less computing resources;

[0032] 3. The present invention uses a physical model for simulation. Compared with other methods, each parameter is related to the actual material and has physical meaning, which is convenient for better guiding subsequent related design, use and research. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of an IGBT chip electrothermal coupling simulation method according to an embodiment of the present invention;

[0034] Figure 2 Schematic diagram of the electrothermal coupling simulation model of the IGBT chip unit cell in the embodiment of the present invention; (a) schematic diagram of the IGBT chip and package partition, (b) Cauer thermal network model of the IGBT chip and package;

[0035] Figure 3 Schematic diagram of a rectangular resistor network at the gate of an IGBT chip layer in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the IGBT chip layer partitioning in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the partitioning of the IGBT packaging part in an embodiment of the present invention;

[0038] Figure 6 This is a simplified partition diagram of the multi-cell of the IGBT chip layer in an embodiment of the present invention;

[0039] Figure 7 This is a simplified partition diagram of a multi-cell of an IGBT packaging part according to an embodiment of the present invention;

[0040] Figure 8 Schematic diagram of the unit cell structure in the large-scale IGBT multi-cell electrothermal coupling model in an embodiment of the present invention;

[0041] Fig. 9 It is a schematic diagram of a large-scale IGBT multi-cell electrothermal coupling model in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Example 1

[0044] An IGBT chip multi-cell electrothermal coupling simulation method provided by an embodiment of the present invention comprises the following steps:

[0045] Step 1: Based on the physical mechanism of the IGBT cell, establish the electrothermal coupling model of the unit cell of the IGBT chip.

[0046] Method for establishing the electrothermal model of IGBT chip unit cell: According to the structure and physical characteristics of IGBT chip, IGBT chip modeling can be divided into the following parts: chip layer, solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer and substrate. Considering the different electrothermal behaviors in different layers, targeted electrothermal modeling is performed separately for different layers.

[0047] In the chip layer, the cells in the chip layer can be divided into MOS part and base part: the electron current I in the MOS part can be obtained through physical equations and cell material parameters. mosn , hole current I mosp 、MOS channel thermal resistance R 1 、MOS area P-well thermal resistance R 2 、MOS channel heat capacity C 1 、MOS area P-well heat capacity C 2 , where the MOS electron current controlled power source I can be obtained according to the electron current, hole current and MOS region voltage drop1 and MOS hole current controlled power source I 2 ; The base region can obtain the collector current I flowing through the collector region c , base voltage drop V base , base thermal resistance R 3 and base heat capacity C 3 According to the base current and base voltage drop, the base controlled power source I can be obtained. 3 .

[0048] Since the electrical behavior of the IGBT chip mainly occurs in the chip layer, and the package parts outside the chip layer have similar thermal behaviors, a unified modeling method is used for the solder layer below the chip layer, the upper copper layer, the ceramic layer, the lower copper layer, the substrate solder layer, and the substrate: According to the material properties of different layers of the package part, the thermal resistance R of the solder layer is obtained. solder , solder layer heat capacity C solder , Thermal resistance of upper copper layer R Cu_upper 、The heat capacity of the upper copper layer C Cu_upper , Ceramic layer thermal resistance R ceramic 、Ceramic layer heat capacity C ceramic , thermal resistance of lower copper layer R Cu_lower , heat capacity of lower copper layer C Cu_lower , Thermal resistance of substrate solder layer R baseplate_solder 、The heat capacity of the substrate solder layer C baseplate_solder 、Substrate thermal resistance R baseplate 、Substrate heat capacity C baseplate .

[0049] The unit cell electrothermal coupling model is as follows Figure 2As shown, the method of establishing the model can refer to the following literature: [1] P. 10.1109 / TPEL.2016.2570838. [2] 5863-5876, Dec. 2023, doi: 10.1109 / JESTPE.2023.3321210.

[0050] Step 2: Considering factors such as the cell size and arrangement of the chip, the IGBT chip is partitioned layer by layer according to the different requirements of the electrothermal coupling simulation of different layers of the IGBT chip.

[0051] Considering the obvious differences in the electrothermal behaviors of different layers in the electrothermal coupling simulation of the IGBT chip: in the chip layer, all cells realize the parallel connection of the overall emitter and collector through the upper metallization and the bottom solder, and the gate is interconnected through the gate oxide layer to realize the overall parallel connection. Therefore, it can be considered that all cells in the chip layer are connected in parallel through external parasitic parameters, and the thermal resistance and thermal capacity of the chip layer itself are relatively small, and there is no need to consider the thermal coupling of the chip layer itself. Therefore, there is no need to consider the geometric arrangement factors of the cells themselves, and the chip layer partition is based on the external parasitic parameters of the cells; in the packaging layer outside the chip layer, there is obvious thermal coupling between different regions in each layer, and different regions have different heat dissipation capabilities. The heat transfer between layers also affects the heat dissipation capacity of the packaging structure. Therefore, the division of the packaging part below the chip needs to consider the thermal behavior differences caused by the geometric relationship between the regions and the regions. At the same time, in order to simplify the interlayer heat transfer calculation, all structures outside the chip layer use the same area division method.

[0052] Chip layer partitioning method: Because the division is based on external parasitic parameters, the embodiment of the present invention only considers the gate resistance distribution, so it is necessary to obtain the detailed gate resistance of the chip layer cells to perform chip layer partitioning. For the convenience of estimation, the gate resistance network of the IGBT chip is approximated as a large-scale rectangular resistance network. According to the resistivity brought by the material properties of the gate resistance network and the position of the grid points of the rectangular resistance network, the gate resistance value from the cells near the grid points to the gate pad can be estimated. In order to improve the accuracy of gate resistance estimation, the density of the rectangular resistance network is increased as much as possible under the condition that the computing power permits, so that the number of cells that share the same grid points to determine the gate resistance value is reduced as much as possible. Using the above method, the IGBT chip can eventually be divided into tens of thousands or even hundreds of thousands of rectangular grids, and all grids are numbered n one by one. All cells in a single grid share the same gate resistance value of the grid, thereby realizing the estimation of the gate resistance Rg(n) of all cells inside the IGBT chip, such as Figure 4 shown.

[0053] Partitioning method of package part: Because the division is based on the geometric shape of the package part, the embodiment of the present invention uses a chip with a gate pad at the center of the chip. To simplify related operations, a large-scale rectangular grid is used as the partitioning method of the package part. The package part is divided into a large number of cuboids with completely identical specifications, each of which contains a solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer, and a part of the substrate area. The heat flux density of different layers in each partition of the packaging part can be obtained in relevant finite element simulation software (the embodiment of the present invention uses Ansys Workbench to extract parameters), and the thermal resistance and thermal capacity of different layers in each partition can be calculated by the heat flux density (see: X.Yang, S. Xu, K. Hengand X. Wu, "Distributed Thermal Modeling for Power Devices and Modules WithEquivalent Heat Flow Path Extraction," in IEEEJournal of Emerging andSelected Topics in Power Electronics, vol. 11, no. 6, pp. 5863-5876, Dec.2023, doi: 10.1109 / JESTPE.2023.3321210.), so as to describe the electrothermal behavior of the packaging part, such as Figure 5 shown.

[0054] Step 3: Based on the two partitioning methods in step 2, the two partitioning methods are integrated to build a large-scale IGBT chip multi-cell electrothermal coupling simulation model.

[0055] Referring to the method of establishing the electrothermal coupling model of the IGBT chip unit cell in step 1, based on the hierarchical partitioning method of the IGBT chip in step 2, a large-scale IGBT multi-cell electrothermal coupling model with a multi-layer structure can be established for the IGBT chip. Directly using the partitioning method in step 2 and its supporting related parameter calculation method can achieve a very high degree of simulation accuracy, but on the one hand, this will greatly increase the workload of establishing a large-scale IGBT electrothermal coupling model, and on the other hand, the simulation itself will consume a lot of computing resources, and the simulation efficiency is low. Therefore, in order to establish a large-scale IGBT multi-cell electrothermal coupling simulation model, on the one hand, it is necessary to simplify the partitioning method in step 2 for the trade-off between accuracy and simulation efficiency; on the other hand, it is necessary to consider how to use the simplified partitioning method and establish a large-scale IGBT electrothermal coupling simulation model by synthesizing the partitioning method.

[0056] Simplified processing method of chip layer partitioning: Taking into account the actual working conditions of the IGBT chip, cells with small differences in gate resistance have similar electrical behaviors when the chip is turned on and off. Therefore, the chip layer in step 2 is simplified here according to the gate resistance value to balance the simulation accuracy and simulation efficiency. From step 2, we can know the maximum and minimum values ​​of the gate resistance of the cells inside the IGBT chip. The maximum and minimum values ​​can be used to determine the interval of the IGBT cell gate resistance value. The interval is divided into 10 small intervals of equal length. The resistance values ​​corresponding to the midpoints of the 10 small intervals are Rg1, Rg2, Rg3...Rg10. Approximate the resistance value of each gate resistance to the resistance value corresponding to the midpoint of the interval according to the interval in which it is located. Then, 10 different numbers of cell models with different gate resistances can be used to approximate the electrothermal behavior of all cells, such as Figure 6 shown.

[0057] Simplified processing method of the packaging part partition method: Through the packaging part partition method in step 2, a very detailed distribution of thermal parameters of the packaging part can be obtained, and decoupling is achieved between the partitions. The relevant parameters of the partitions already include the impact of thermal coupling. Considering the actual working conditions of the IGBT, the area where the IGBT thermal failure usually occurs is the edge of the IGBT chip. In order to balance the simulation accuracy and simulation efficiency, the small cells of equal area in the packaging part are selectively merged, and a large-scale multi-cell simulation model with cell area differences is established for the packaging part. In the embodiment of the present invention, an IGBT with a gate pad located in the center of the chip is selected, so the intersection of the chip diagonal is taken as the center point, and the three-division points are determined on the line segments from the center point to the four corners of the chip. The four three-division points close to the center and the four three-division points far from the center are connected respectively, and the chip is divided into three areas by two rectangles. The part of the area where the midpoint is located without the gate pad is called the first area, the part between the two rectangles is the second area, and the outermost part is the third area. The small cells in the first and second areas are merged to achieve a cell area of ​​16:4:1 in the three areas, so as to improve the simulation speed while retaining the simulation accuracy of the key areas as much as possible, such as Figure 7 shown.

[0058] Method for establishing a large-scale IGBT multi-cell electrothermal coupling model: After completing the above simplification of the different layers of the IGBT partition, according to the structural characteristics of the IGBT chip itself, a large-scale IGBT electrothermal coupling simulation model is established based on the final partition results of the packaging part below the IGBT chip layer. By geometrically matching the chip layer partitions with the packaging part partitions, determining the type and number of chip layer cells that match the packaging part according to the area and location of the packaging part partitions, combining the corresponding chip layer part and the packaging part as a whole, obtaining the required related electrothermal parameters according to the requirements of the unit cell electrothermal coupling model, and establishing a unit cell electrothermal coupling model for the whole, performing the above operations on all chip partitions, and combining all unit cell electrothermal coupling models, you can get a multi-cell model of the entire IGBT chip, which can describe the electrothermal behavior of the IGBT chip when it is working. The unit cell model is as follows: Figure 8 shown.

[0059] Step 4: Use a large-scale IGBT chip multi-cell electrothermal coupling model for simulation. The model calculates the overall temperature distribution change of the IGBT chip through power loss heat generation and heat dissipation, and calculates the changes in related temperature sensitive parameters at different positions in the IGBT chip layer based on the overall temperature distribution of the IGBT chip, thereby realizing real-time calculation of the detailed surface temperature distribution and internal current distribution of the IGBT chip.

[0060] In this embodiment, when the IGBT chip is turned on, the chip layer generates heat through loss, which causes the local temperature of the chip to rise. The temperature rise affects the temperature-sensitive parameters of the semiconductor inside the chip layer, thereby affecting the conductivity of the IGBT cell, which in turn affects the loss and heat of the IGBT chip. There is an electrothermal coupling effect. Therefore, the relevant temperature sensitivity coefficient of the IGBT cell and the power loss and heat generation are used in conjunction with the large-scale multi-cell model completed in step 3 to obtain a large-scale multi-cell electrothermal coupling simulation model, such as Fig. 9 As shown. Under the current temperature sensitive parameter conditions, the model is run to calculate the current distribution and the corresponding power loss distribution at this time. The power loss distribution at this moment is substituted into different partitions of the multi-cell electrothermal coupling model to obtain the detailed short-term temperature distribution changes under the current power loss distribution. The temperature distribution at this moment is used to calculate the temperature sensitive parameters at this moment, and the new temperature sensitive parameters are substituted into the multi-cell electrothermal coupling model to complete an electrothermal coupling model simulation run.

[0061] In this embodiment, the temperature sensitive parameters of the IGBT physical model include the electron mobility μ of each region. ni , hole mobility μ pi , carrier lifetime τ i , transconductance coefficient K p , threshold voltage V TH . For details on the IGBT cell area division method, please refer to Figure 2 Chip layer part.

[0062] Electron mobility μ in each region ni The calculation formula is as follows:

[0063] ;

[0064] where i=1,3,μ n1 is the electron mobility in the channel region, μ n3 is the electron mobility in the N-drift region, T 1 is the average temperature of the channel region, T 3 is the average temperature of the N-drift region, N B is the base region doping concentration.

[0065] Hole mobility μ in each region pi The calculation formula is as follows:

[0066] ;

[0067] where i=1,3,μ p2 is the hole mobility in the P-well region, μ p3 is the hole mobility in the N-drift region, T 2 is the average temperature of the P-well area.

[0068] The calculation formula of carrier lifetime τ is as follows:

[0069] ;

[0070] where τ 300K is the carrier lifetime at 300 K, τ represents T 3 Carrier lifetime in the N-drift region under .

[0071] Transconductance coefficient K p The calculation formula is as follows:

[0072] ;

[0073] Where K p300K is the transconductance coefficient of the MOS part at a temperature of 300 K.

[0074] Threshold voltage V TH The calculation formula is as follows:

[0075] ;

[0076] Where V TH300K is the threshold voltage at 300 K.

[0077] Step 5: Repeat step 4 and iterate the model to obtain detailed distribution results of the IGBT chip surface temperature and internal current at different times.

[0078] Use a large-scale IGBT chip multi-cell electrothermal coupling model to simulate, determine the simulation conditions, obtain the relevant parameters of the simulation device, and determine the specific scale of the electrothermal coupling simulation model, the single electrothermal coupling simulation time, and all the initial conditions of the chip based on all the above parameters and simulation accuracy requirements. Import all the above parameters into the large-scale electrothermal coupling simulation model, and perform electrothermal coupling simulation on the simulated device. The single electrothermal simulation method refers to the method described in step 4. Based on the current temperature and input voltage and current, the chip obtains all the current temperature-sensitive parameters and power loss distribution inside it, and forms a temperature distribution on the chip surface; then, because the power loss of each cell partition of the chip continues to rise on the basis of the local temperature at each location, a new surface temperature distribution is formed, and the temperature-sensitive parameters and internal power loss distribution of the chip need to be recalculated. The detailed electrothermal distribution of the chip surface at the latest moment is obtained through repeated iterations. At this time, the calculated chip surface temperature and current distribution are the chip simulation results after the electrothermal interaction of the IGBT chip cells.

[0079] Example 2

[0080] Embodiment 2 of the present invention provides a terminal device corresponding to the above-mentioned embodiment 1. The terminal device may be a processing device for a client, such as a mobile phone, a laptop computer, a tablet computer, a desktop computer, etc., to execute the method of the above-mentioned embodiment.

[0081] The terminal device of this embodiment includes a memory, a processor, and a computer program stored in the memory; the processor executes the computer program in the memory to implement the steps of the method in the above-mentioned embodiment 1.

[0082] In some implementations, the memory may be a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0083] In some other implementations, the processor may be a central processing unit (CPU), a digital signal processor (DSP), or other general-purpose processors of various types, which are not limited herein.

[0084] Example 3

[0085] Embodiment 3 of the present invention provides a computer-readable storage medium corresponding to the above embodiment 1, on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the method of the above embodiment 1 are implemented.

[0086] Computer readable storage media can be tangible devices that hold and store instructions used by instruction execution devices. Computer readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any combination thereof.

[0087] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The schemes in the embodiments of the present application may be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0088] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0090] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0091] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for simulating electrothermal coupling of multi-cells of an IGBT chip, characterized in that: The following steps are involved: S1. Establish an electrothermal coupling model of the IGBT chip unit cell; S2. According to the structural characteristics of the IGBT chip, the chip layer and the packaging part of the IGBT are partitioned respectively, and the chip layer and the packaging part partitions are simplified respectively; Each partition of the packaging part in the final simplified partition result and all chip partitions above the partition are regarded as a cell, and the electrothermal behavior of the cell is simulated using the IGBT unit cell electrothermal coupling model to obtain an IGBT chip multi-cell electrothermal coupling model; according to the structure and physical properties of the IGBT chip, the IGBT chip is divided into a chip layer, a solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer and a substrate; the solder layer, the upper copper layer, the ceramic layer, the lower copper layer, the substrate solder layer and the substrate are the packaging part; The specific implementation process of partitioning the chip layer of the IGBT chip includes: The gate resistance network of the IGBT chip is equivalent to a rectangular resistance network, and the gate resistance value from the cell near the grid point to the gate pad is estimated based on the resistivity brought by the material properties of the gate resistance network and the position of the grid point of the rectangular resistance network; the IGBT chip is divided into multiple rectangular grids; All rectangular grids are numbered one by one, and the resistance value of all cells in a single grid is the gate resistance value corresponding to the grid; The specific implementation process of partitioning the packaging part of the IGBT chip includes: The package part is divided into cuboids of the same specifications, each of which contains a solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer, and a part of the substrate area; Obtain the heat flux density of different layers in each partition of the package part, and calculate the thermal resistance and heat capacity of different layers in each partition through the heat flux density; The specific implementation process of simplifying the chip layer and the packaging part partitions respectively includes: 1) For the chip layer, the maximum and minimum values ​​of the gate resistance of the cell inside the IGBT chip are obtained, and the interval of the gate resistance of the IGBT cell is determined by the maximum and minimum values. The interval is divided into multiple small intervals of equal length, and the gate resistance value of each small interval is approximated to the resistance value corresponding to the midpoint of the small interval, so as to obtain the simplified chip layer partitioning result; For the packaging part, select the IGBT with the gate pad located in the center of the chip, take the intersection of the diagonals of the IGBT chip as the center point, determine the trisection points from the center point to the four corners of the chip, connect the four trisection points close to the center, and connect the four trisection points far from the center to get two rectangles. The two rectangles divide the chip into three areas. The area where the midpoint is located minus the gate pad is called the first area, the middle part of the two rectangles is the second area, and the outermost part is the third area; merge the small cells in the first and second areas respectively, so that the cell areas of the three areas are 16:4:1, and get the simplified packaging part partition result; 2) After obtaining the simplified chip layer partition results and the simplified package part partition results, take the package part partition results as the main body, regard each package part partition and all the chip partitions directly above the partition as a whole, refer to the unit cell electrothermal coupling model, obtain all relevant electrothermal parameters of the whole, and then establish the unit cell electrothermal coupling model; 3) Repeat the above step 2) for each partition of the package part to obtain a multi-cell electrothermal coupling model; the relevant electrothermal parameters include: solder layer thermal resistance R solder , solder layer heat capacity C solder , Thermal resistance of upper copper layer R Cu_upper 、The heat capacity of the upper copper layer C Cu_upper , Ceramic layer thermal resistance R ceramic 、Ceramic layer heat capacity C ceramic , thermal resistance of lower copper layer R Cu_lower , heat capacity of lower copper layer C Cu_lower , Thermal resistance of substrate solder layer R bp_solder 、The heat capacity of the substrate solder layer C bp_solder , substrate thermal resistance R baseplate 、Substrate heat capacity C baseplate , hole current I pmos 、Electron current I nmos , displacement current I disp , collector current I C , MOS side depletion layer voltage V DS and gate voltage V GS ; S3. Use the multi-cell electrothermal coupling model of the IGBT chip to perform simulation, calculate the overall temperature distribution change of the IGBT chip through power loss heat generation and heat dissipation, calculate the changes of related temperature sensitive parameters at different positions in the IGBT chip layer based on the overall temperature distribution of the IGBT chip, and obtain the detailed surface temperature distribution and internal current distribution of the IGBT chip; S4. Repeat step S3 to obtain detailed distribution results of the surface temperature and internal current of the IGBT chip at different times.

2. The IGBT chip multi-cell electrothermal coupling simulation method according to claim 1, characterized in that: In step S1, the specific implementation process of establishing the electrothermal coupling model of the unit cell of the IGBT chip includes: Divide the cells in the chip layer into a MOS part and a base part; Establishing electrothermal coupling models for the chip layer and the packaging part respectively; The electrothermal coupling model of the chip layer and the electrothermal coupling model of the packaging part are combined to obtain an IGBT chip unit cell electrothermal coupling model.

3. The IGBT chip multi-cell electrothermal coupling simulation method according to claim 1, characterized in that: Run the IGBT chip multi-cell electrothermal coupling model under the current temperature sensitive parameter conditions, calculate the current distribution and the corresponding power loss distribution at this time, substitute the power loss distribution at this moment into the different partitions of the IGBT chip multi-cell electrothermal coupling model, and obtain the detailed temperature distribution changes under the current power loss distribution. Use the detailed temperature distribution changes to calculate the temperature sensitive parameters at the current moment, and substitute the new temperature sensitive parameters into the IGBT chip multi-cell electrothermal coupling model to complete an electrothermal coupling model simulation run.

4. An IGBT chip multi-cell electrothermal coupling simulation system, comprising a memory, a processor and a computer program stored in the memory; characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 3.

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