A PFC circuit for Flyback and a switching power supply

Abstract

The present application discloses a PFC circuit applied to Flyback and a switching power supply, belonging to the field of power electronics technology, the circuit includes: a transformer, a voltage divider module, a control chip, a capacitor module, a switch tube and a delay module arranged inside the control chip; the delay module can use the target delay signal to keep the working current of the transformer in the same phase with the AC voltage; the primary winding of the transformer is used to receive the AC voltage, the secondary winding is connected to the load, the first end of the auxiliary winding is grounded, the second end is connected to the FB pin of the control chip through the voltage divider module, the DRV pin of the chip is connected to the control end of the switch tube, one end of the switch tube is connected to the primary winding of the transformer, the other end is grounded, the Comp pin of the control chip is connected to the first end of the capacitor module, and the second end of the capacitor module is grounded. Through this structure, the PF value of the circuit can be equal to 1, and the utilization rate of the output energy of the power grid can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a PFC circuit applied to Flyback and a switching power supply. Background Art

[0002] PFC (Power Factor Correction) is an important measure to improve the power factor of the power grid. In Flyback (single-ended flyback transformer), the signal that determines the on-time of the switch tube in a power frequency cycle is mainly filtered through a large filter capacitor, that is, the on-time of the switch tube in a power frequency cycle will hardly change, and the system will work in the critical conduction mode (Critical Conduction Mode, CrM), so that the input current and the input voltage amplitude are in phase, thereby realizing the PFC function of the Flyback circuit. Although this PFC implementation method is relatively simple, the PF value of the circuit will be less than 1 under this setting. If the losses caused by other factors in actual applications are considered, the PF value of the entire circuit will be smaller than 1, which will result in a low utilization rate of Flyback's output energy for the power grid. At present, there is no more effective solution to this technical problem. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a PFC circuit and a switching power supply applied to Flyback to solve the technical problem of low utilization rate of Flyback output energy to the power grid in the prior art. The specific scheme is as follows:

[0004] In order to solve the above technical problems, the present invention provides a PFC circuit applied to Flyback, comprising: a transformer, a voltage dividing module, a control chip, a capacitor module, a switch tube and a delay module arranged inside the control chip; the delay module outputs a target delay signal, and uses the target delay signal to compensate the conduction time of the switch tube, so that the working current of the transformer maintains the same phase as the AC voltage;

[0005] Among them, the primary winding of the transformer is used to receive AC voltage, the secondary winding of the transformer is connected to a load, the first end of the auxiliary winding of the transformer is grounded, the second end of the secondary winding of the transformer is connected to the FB pin of the control chip through the voltage divider module, the DRV pin of the control chip is connected to the control end of the switch tube, the first end of the switch tube is grounded, the second end of the switch tube is connected to the primary winding of the transformer, the Comp pin of the control chip is connected to the first end of the capacitor module, and the second end of the capacitor module is grounded.

[0006] Preferably, the delay module comprises:

[0007] A signal amplifying unit, configured to amplify the first voltage to obtain a first amplified signal, and amplify the second voltage to obtain a second amplified signal; wherein the first voltage and the second voltage are the voltages of the FB pin of the control chip when the switch tube is turned on and off, respectively;

[0008] a current mirror unit, connected to the signal amplifying unit, and configured to mirror-copy the first amplified signal and the second amplified signal;

[0009] A signal generating unit is connected to the current mirror unit and is used to generate the target delay signal according to the first amplified signal and the second amplified signal output by the current mirror unit.

[0010] Preferably, the voltage dividing module comprises: a first resistor and a second resistor;

[0011] The first end of the first resistor is connected to the second end of the secondary winding of the transformer, the second end of the first resistor is respectively connected to the FB pin of the control chip and the first end of the second resistor, and the second end of the second resistor is grounded.

[0012] Preferably, the first voltage and the second voltage are obtained by sampling an auxiliary winding of the transformer.

[0013] Preferably, the signal amplification unit comprises: an operational amplifier, an NMOS tube and a third resistor;

[0014] The output end of the operational amplifier is connected to the gate of the NMOS tube, the positive input end of the operational amplifier is used to receive the first voltage and the second voltage, the negative input end of the operational amplifier is respectively connected to the source of the NMOS tube and the first end of the third resistor, the second end of the third resistor is grounded, and the drain of the NMOS tube is used to output the first amplified signal and the second amplified signal.

[0015] Preferably, the current mirror unit comprises: a first PMOS tube, a second PMOS tube and a third PMOS tube;

[0016] The drain of the NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube.

[0017] The source of the first PMOS tube is connected to the source of the second PMOS tube and the source of the third PMOS tube respectively, the drain of the second PMOS tube is used to output the first amplified signal, and the drain of the third PMOS tube is used to output the second amplified signal.

[0018] Preferably, the signal generating unit comprises: a first switch, a second switch, a first capacitor, a second capacitor and a comparator;

[0019] Among them, the first end of the first switch is connected to the drain of the second PMOS tube, the second end of the first switch is respectively connected to the positive input end of the comparator and the first end of the first capacitor, the second end of the first capacitor is grounded, the first end of the second switch is connected to the drain of the third PMOS tube, the second end of the second switch is respectively connected to the first end of the second capacitor and the negative input end of the comparator, the second end of the second capacitor is grounded, and the output end of the comparator is used to output the target delay signal.

[0020] Preferably, the first capacitor and the second capacitor have the same capacitance.

[0021] Preferably, it also includes:

[0022] The AND gate circuit is used to compensate the conduction time of the switch tube through the target delay signal.

[0023] In order to solve the above technical problem, the present invention further provides a switching power supply, including a PFC circuit applied to Flyback as disclosed above.

[0024] Beneficial effect: In the present invention, a PFC circuit applied to Flyback is provided, and the circuit includes: a transformer, a voltage divider module, a control chip, a capacitor module, a switch tube and a delay module arranged inside the control chip; the delay module outputs a target delay signal, and uses the target delay signal to compensate for the conduction time of the switch tube, so that the working current of the transformer and the AC voltage maintain the same phase; wherein, the primary winding of the transformer is used to receive the AC voltage, the secondary winding of the transformer is connected to a load, the first end of the auxiliary winding of the transformer is grounded, the second end of the auxiliary winding of the transformer is connected to the FB pin of the control chip through the voltage divider module, the DRV pin of the control chip is connected to the control end of the switch tube, the first end of the switch tube is grounded, the second end of the switch tube is connected to the primary winding of the transformer, the Comp pin of the control chip is connected to the first end of the capacitor module, and the second end of the capacitor module is grounded.

[0025] Compared with the prior art, in the PFC circuit provided by the present invention, the target delay signal output by the delay module can compensate for the conduction time of the switch tube, and the working current of the transformer can maintain the same phase as the AC voltage input to the transformer. Under this setting, the PF value of the entire circuit can be equal to 1, thereby improving the utilization rate of Flyback for the output energy of the power grid. Correspondingly, a switching power supply provided by the present application also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0027] Figure 1 A structural diagram of a PFC circuit applied to Flyback provided by an embodiment of the present invention;

[0028] Figure 2 This is the signal timing diagram when Flyback works in critical conduction mode;

[0029] Figure 3 A structural diagram of a delay module provided by an embodiment of the present invention;

[0030] Figure 4 This is the working timing diagram of the FB pin on the control chip. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] See also Figure 1 , Figure 1 The structure diagram of a PFC circuit applied to Flyback provided by an embodiment of the present invention includes: a transformer T, a voltage dividing module 10, a control chip 20, a capacitor module C01, a switch tube S and a delay module 30 arranged inside the control chip 20; the delay module 30 outputs a target delay signal, and uses the target delay signal to compensate the conduction time of the switch tube S, so that the working current of the transformer T and the AC voltage maintain the same phase;

[0033] Among them, the primary winding of the transformer T is used to receive an AC voltage, the secondary winding of the transformer T is connected to a load, the first end of the auxiliary winding of the transformer T is grounded, the second end of the auxiliary winding of the transformer T is connected to the FB pin of the control chip 20 through the voltage divider module 10, the DRV pin of the control chip 20 is connected to the control end of the switch tube S, the first end of the switch tube S is grounded, the second end of the switch tube S is connected to the primary winding of the transformer T, the Comp pin of the control chip 20 is connected to the first end of the capacitor module C01, and the second end of the capacitor module C01 is grounded.

[0034] exist Figure 1 In the circuit shown, BG represents the rectifier module, C02 represents the capacitor module, D represents the diode, and C03 represents the capacitor module. These functional modules are peripheral circuits of the PFC circuit and are used to assist the function realization of the PFC circuit. Figure 1 The transformer T, voltage divider module 10, control chip 20, capacitor module C01, switch tube S and delay module 30 are the main functional modules in the PFC circuit. Among them, Vac represents the AC voltage, Np represents the primary winding of the transformer T, Ns represents the secondary winding of the transformer T, and Na represents the auxiliary winding of the transformer T.

[0035] In addition, it should be noted that, in practical applications, the switch tube S can be set to an NMOS tube, wherein the gate of the NMOS tube is the control end of the switch tube S, the source of the NMOS tube is the first end of the switch tube S, and the drain of the NMOS tube is the second end of the switch tube S. Furthermore, in order to reduce the difficulty of building the PFC circuit and the complexity of the circuit structure, as a preferred implementation, the voltage divider module 10 can also be set to a resistor voltage divider structure.

[0036] That is, the voltage dividing module 10 includes: a first resistor R1 and a second resistor R2;

[0037] The first end of the first resistor R1 is connected to the second end of the secondary winding of the transformer T, the second end of the first resistor R1 is connected to the FB pin of the control chip 20 and the first end of the second resistor R2 respectively, and the second end of the second resistor R2 is grounded.

[0038] In order to enable those skilled in the art to more clearly understand the implementation principle of the present application, in this embodiment, firstly Figure 1 The working principle of the circuit excluding the delay module 30 is specifically described. Figure 1In the Flyback shown in the figure, the signal (Vcomp, where Vcomp is the output voltage of the pin 20Comp of the control chip) that determines the on-time of the switch tube S within a power frequency cycle is filtered out mainly through a large filter capacitor. That is, the on-time of the switch tube S hardly changes within a power frequency cycle. At the same time, the system is set in the critical conduction mode, so that the input current and the input voltage amplitude can be in phase, thereby realizing the PFC function of the Flyback circuit.

[0039] See also Figure 2 , Figure 2 This is the signal timing diagram when Flyback works in critical conduction mode. Since the winding of transformer T can be equivalent to an inductor, then: Figure 2 Iin represents the average value of the inductor input current, Ipk represents the peak current of the inductor, Ilp is the current flowing through the inductor, tonp represents the on-time of the switch tube S, tons represents the freewheeling time of the secondary side of the transformer T, and DRV represents the drive signal output by the DRV pin on the control chip 20.

[0040] Although the above PFC implementation method is relatively simple, the following formula can be derived based on theoretical knowledge:

[0041] Iin=1 / 2*Ipk*tonp / (tonp+tons) Vin=Vac*1.414;

[0042] Ipk=Vin*sinθ / Lp*ton;

[0043] Iin=1 / 2*Vin*sinθ / Lp*ton*tonp / (tonp+tons);

[0044] At the same time, according to the inductor volt-second balance characteristics, we can get:

[0045] Vin*sinθ / Lp*tonp*Nps=Vout / Ls*tons;

[0046] Lp / Ls=Nps*Nps, Nps=Np / Ns;

[0047] Iin=1 / 2*Vin*sinθ / Lp*tonp / (1+Vin*sinθ / (Nps*Vout));

[0048] In the above formula, Iin represents the average value of the inductor input current (the winding of transformer T can be equivalent to the inductor), Ipk represents the peak current of the inductor, tonp represents the conduction time of the switch tube S, tons represents the freewheeling time of the secondary side of the transformer T, Vin represents the peak value of the AC voltage Vac, sinθ represents the phase coefficient of the AC voltage Vac, Lp represents the primary inductance of the transformer T, Ls represents the secondary inductance of the transformer T, Np represents the number of turns of the primary winding of the transformer T, and Ns represents the number of turns of the secondary winding of the transformer T; if it is assumed that L is the inductance value of the system inductor, then the inductor current satisfies I=V / L*t, I is the current change at both ends of the inductor, V is the voltage at both ends of the inductor, t is the time that V is applied to both ends of the inductor, and the Ipk corresponding to a certain moment is generated by the voltage Vin*sinθ at both ends of the inductor and the time that the voltage is applied to both ends of the inductor, that is, ton.

[0049] It is understandable that because tonp is fixed within a power frequency cycle, Vin remains unchanged under a specific input line voltage, and Lp is the primary inductance of the transformer T, which is a fixed inductance value, the input current can maintain a phase output of θ with the input voltage. However, the effect of sinθ on the current phase in (1+Vin*sinθ / (Nps*Vout)) is ignored here, so the PF value of the circuit will be less than 1. If the losses caused by other factors in actual applications are considered, the PF value of the entire circuit will be smaller than 1, which will result in a low utilization rate of Flyback's output energy from the power grid.

[0050] In order to solve the above technical problems, in the present application, a delay module 30 is added to the original PFC circuit, and the input current is optimized through the delay module 30, so that Flyback can allow the input current to change with the input voltage in the critical conduction mode, and make the PF value of Flyback equal to 1, thereby achieving a high PF modulation effect.

[0051] From the above discussion, we can know that:

[0052] Iin=1 / 2*Vin*sinθ / Lp*ton*tonp / (tonp+tons);

[0053] Iin=1 / 2*Vin*sinθ / Lp*tonp / (1+Vin*sinθ / (Nps*Vout));

[0054] Since the signal Vcomp outputted by the output terminal Comp pin of the control chip 20 will affect tonp, we can record it as tonp=K*Vcomp here. Wherein, Vcomp is the signal outputted by the error amplifier inside the control chip 20 after comparing the signal sampled by the FB pin with the reference signal. In this embodiment, we set tonp to be determined by the comp signal and introduce the coefficient term of (tonp+tons) / tonp, recorded as Tonp, and then the following formula will exist:

[0055] Tonp=K*Vcomp*(tonp+tons) / tonp;

[0056] Substitute Tonp into Iin=1 / 2*Vin*sinθ / L*Tonp*tonp / (tonp+tons), then the original coefficient tonp / (tonp+tons) will be offset by the coefficient (tonp+tons) / tonp contained in Tonp, and the following formula will exist:

[0057] Iin=1 / 2*Vin*sinθ / L*K*Vcomp=1 / 2*Vin / L*K*Vcomp*sinθ.

[0058] Because Vcomp is almost unchanged in a later period of power frequency, Vin, L, and K are constants. Therefore, after optimization, the amplitude and phase of the input current and input voltage in the circuit are the same, both are θ, and the optimized input current makes the circuit work in CrM mode.

[0059] In this embodiment, in order to introduce the coefficient term (tonp+tons) / tonp into the circuit, it is also necessary to transform Tonp, that is:

[0060] Tonp=K*Vcomp*(tonp+tons) / tonp;

[0061] Tonp=K*Vcomp*(1+tons / tonp);

[0062] Tonp=K*Vcomp+K*Vcomp*tons / tonp;

[0063] In the above formula, K*Vcomp is determined by the signal output by the Comp pin of the control chip 20, and can be recorded as tonp0 to distinguish it from the actual on-time of the switch tube S. On this basis, it is necessary to add another term of K*Vcomp*tons / tonp, that is, tonp0*tons / tonp, which is recorded as tdelay here.

[0064] It should be noted that tonp0 is the value generated by the output voltage signal Vcomp of the Comp pin of the control chip, which will remain almost unchanged within an industrial frequency cycle, while tonp and tons represent the conduction time of the switch tube S in the current cycle and the freewheeling time of the secondary side, respectively, and their values ​​are variable.

[0065] To sum up, Tonp=tonp0+tdelay.

[0066] From the above formula, we can see that if we use a delay module to generate a delay signal tdelay, and use the delay signal tdelay to compensate for the conduction time of the switch tube S, the operating current of the transformer can be kept in the same phase as the AC voltage, so that the PF value of the PFC circuit is equal to 1, thereby improving the utilization rate of Flyback for the grid output energy.

[0067] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the delay module 30 includes:

[0068] A signal amplifying unit, used to amplify the first voltage to obtain a first amplified signal, and to amplify the second voltage to obtain a second amplified signal; wherein the first voltage and the second voltage are respectively the voltages of the FB pin of the control chip when the switch tube is turned on and off;

[0069] A current mirror unit, connected to the signal amplifying unit, and used for mirroring the first amplified signal and the second amplified signal;

[0070] The signal generating unit is connected to the current mirror unit and is used to generate a target delay signal according to the first amplified signal and the second amplified signal output by the current mirror unit.

[0071] In this embodiment, the structure of the delay module is specifically described. In the delay module provided in this embodiment, a signal amplification unit, a current mirror unit and a signal generating unit are provided. Among them, the signal amplification unit is used to amplify the first voltage and the second voltage, and thereby improve the accuracy of the target delay signal output by the delay module. The first voltage is the voltage of the FB pin of the control chip when the switch tube is turned on, and the second voltage is the voltage of the FB pin of the control chip when the switch tube is turned off. The current mirror unit is used to mirror the first amplified signal and the second signal, so that the signal generating unit can generate the target delay signal tdelay according to the first amplified signal and the second amplified signal output by the current mirror unit.

[0072] See also Figure 3 , Figure 3A structural diagram of a delay module provided by an embodiment of the present invention. As a preferred implementation, the signal amplification unit includes: an operational amplifier U, an NMOS tube N and a third resistor R3;

[0073] Among them, the output end of the operational amplifier U is connected to the gate of the NMOS tube N, the positive input end of the operational amplifier U is used to receive the first voltage VFB_N and the second voltage VFB_P, the negative input end of the operational amplifier U is respectively connected to the source of the NMOS tube N and the first end of the third resistor R3, the second end of the third resistor R3 is grounded, and the drain of the NMOS tube N is used to output the first amplified signal and the second amplified signal.

[0074] As a preferred implementation, the current mirror unit includes: a first PMOS tube P1, a second PMOS tube P2 and a third PMOS tube P3;

[0075] Among them, the drain of the NMOS tube N is respectively connected to the drain of the first PMOS tube P1, the gate of the first PMOS tube P1, the gate of the second PMOS tube P2 and the gate of the third PMOS tube P3, the source of the first PMOS tube P1 is respectively connected to the source of the second PMOS tube P2 and the source of the third PMOS tube P3, the drain of the second PMOS tube P2 is used to output the first amplified signal, and the drain of the third PMOS tube P3 is used to output the second amplified signal.

[0076] As a preferred implementation, the signal generating unit includes: a first switch K1, a second switch K2, a first capacitor C1, a second capacitor C2 and a comparator M;

[0077] Among them, the first end of the first switch K1 is connected to the drain of the second PMOS tube P2, the second end of the first switch K1 is respectively connected to the positive input end of the comparator M and the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, the first end of the second switch K2 is connected to the drain of the third PMOS tube P3, the second end of the second switch K2 is respectively connected to the first end of the second capacitor C2 and the negative input end of the comparator M, the second end of the second capacitor C2 is grounded, and the output end of the comparator M is used to output the target delay signal tdelay.

[0078] In this embodiment, the arrangement structure of the signal amplifying unit, the current mirror unit and the signal generating unit in the delay module is specifically described. In order to facilitate the technical understanding of those skilled in the art, the signal amplifying unit, the current mirror unit and the signal generating unit are described together here, and the working principle of the delay module is specifically described.

[0079] See also Figure 4 , Figure 4 This is the working timing diagram of the FB pin on the control chip. Figure 4In the figure, DRV represents the driving signal output by the DRV pin on the control chip 20, tonp represents the on-time of the switch tube S, tons represents the freewheeling time of the secondary side of the transformer T, VFB_N represents the voltage detected by the FB pin on the control chip when the switch tube S is in the on-state, and VFB_P represents the voltage detected by the FB pin on the control chip when the switch tube S is in the off-state.

[0080] Since tonp0 is a value generated solely by the value of Vcomp, it will remain almost unchanged during the power frequency cycle. In order to obtain the value of tons / tonp, we use the inductor volt-second balance characteristics to replace tons / tonp. According to the above formulas Vin*sinθ / Lp*tonp*Nps=Vout / Ls*tons, Lp / Ls=Nps*Nps and Nps=Np / Ns, we can get: tons / tonp=(Vin*sinθ) / (Nps*Vout).

[0081] In order to reduce the complexity of the circuit, we can reuse the auxiliary winding in the transformer to sample the proportional voltage of Vin*sinθ and Vout, and thereby achieve the purpose of multiplexing the auxiliary winding in the transformer to collect the first voltage VFB_N and the second voltage VFB_P, wherein the first voltage VFB_N and the second voltage VFB_P are the voltages of the FB pin of the control chip when the switch tube S is on and off, respectively. When the switch tube S is turned on, the inductor current of the primary winding of the transformer T gradually increases, and the negative voltage detected by the auxiliary winding is the mirror image of the input voltage Vin, that is, -Vin*sinθ*Nap. For the convenience of calculation, the absolute value of the negative voltage is used. At this time, after the FB pin in the control chip passes through the first resistor R1 and the second resistor R2, the voltage value collected is:

[0082] VFB_N=Vin*sinθ*Nap*RFB_L / (RFB_H+RFB_L);

[0083] When the switch tube S is turned off, the inductor current of the secondary winding of the transformer T gradually decreases, and the voltage detected by the auxiliary winding is: Vout*Nas. At this time, the voltage obtained by the FB pin of the control chip through the first resistor R1 and the second resistor R2 is: VFB_P=Vout*Nas*RFB_L / (RFB_H+RFB_L). At this time, VFB_N / VFB_P=(Vin*sinθ*Nap) / (Vout*Nas)=(Vin*sinθ) / (Vout*Nps)= tons / tonp.

[0084] In order to obtain the ratio of VFB_N and VFB_P, we can convert VFB_N and VFB_P into currents Icharge1 and Icharge2 through a current mirror, and use Icharge1 and Icharge2 as the charging currents of the first capacitor C1 and the second capacitor C2 respectively. For ease of calculation, the capacitance of the first capacitor C1 and the second capacitor C2 can be set to the same capacitance. In this case, Icharge1=VFB_N / R, Icharge2=VFB_P / R, where R is the resistance of the first capacitor C1 or the second capacitor C2.

[0085] During the time of tonp0, Icharge1 is used to charge the first capacitor C1. At this time, Icharge1*tonp0=C1*ΔV1, ΔV1=VFB_N / R*tonp0 / C1, and ΔV1 is the voltage change of the first capacitor C1.

[0086] Let C1=C2, and keep the voltage after the first capacitor C1 is fully charged, and then control Icharge2 to charge the second capacitor C2. When the voltage ΔV2 (ΔV2 is the voltage change of the second capacitor C2) on the second capacitor C2 is equal to the voltage value on the first capacitor C1, the output voltage of the comparator M is reversed.

[0087] If we record the charging time of the second capacitor C2 as t_c, then we have:

[0088] VFB_P / R*t_c / C2=ΔV2=ΔV1=VFB_N / R*tonp0 / C1;

[0089] t_c=VFB_N / VFB_P*tonp0;

[0090] According to the previous derivation: VFB_N / VFB_P=tons / tonp;

[0091] Therefore, t_c=(tons / tonp)*tonp0, t_c is the target delay signal.

[0092] In addition, it should be noted that, because the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are equal, the capacitance changes corresponding to the first capacitor C1 and the second capacitor C2 are also equal, and the products of the corresponding capacitance charging time and charging current are also equal. Therefore, when the product of the charging time and charging current of a certain capacitor is determined, in order to obtain the same capacitance value and the same capacitance voltage change of another capacitor, the product of the charging time and charging current of the other capacitor is also determined.

[0093] Obviously, by setting in this way, we can get the target delay signal tdelay we need. In practical applications, by controlling the switch tube to conduct within the time Tonp=tonp0+tdelay, high PF modulation in the flyback critical conduction mode can be achieved, and the PF value can be equal to 1.

[0094] It should be noted that in this embodiment, the first voltage VFB_N and the second voltage VFB_P are received in time-sharing manner by reusing an operational amplifier U. Of course, in practical applications, two operational amplifiers can also be set in the circuit to receive the first voltage VFB_N and the second voltage VFB_P respectively. Although this setting method is simple, it will also increase the area of ​​the circuit chip. In addition, charging capacitors with equal capacitance can also be reused by adding an additional control logic circuit to obtain a higher matching accuracy, but the additional control logic circuit will bring design difficulties.

[0095] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the above PFC circuit further includes:

[0096] The AND gate circuit is used to compensate the conduction time of the switch tube through the target delay signal.

[0097] In practical applications, in order to reduce the complexity of the circuit structure and the setting cost, an AND gate circuit can be used to apply the target delay signal to the RDV pin of the control chip 20, so as to compensate the conduction time of the switch tube S.

[0098] Correspondingly, an embodiment of the present invention further provides a switching power supply, including a PFC circuit applied to Flyback as disclosed above.

[0099] A switching power supply provided by an embodiment of the present invention has the beneficial effects of the aforementioned PFC circuit applied to Flyback.

[0100] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0101] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0102] The above is a detailed introduction to a PFC circuit applied to Flyback and a switching power supply provided by the present invention. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A PFC circuit applied to Flyback, characterized in that: include: A transformer, a voltage dividing module, a control chip, a capacitor module, a switch tube and a delay module arranged inside the control chip; The delay module outputs a target delay signal, and uses the target delay signal to compensate for the on-time of the switch tube, so that the working current of the transformer maintains the same phase as the AC voltage; The primary winding of the transformer is used to receive an AC voltage, a load is connected to the secondary winding of the transformer, a first end of the auxiliary winding of the transformer is grounded, a second end of the auxiliary winding of the transformer is connected to the FB pin of the control chip through the voltage divider module, a DRV pin of the control chip is connected to the control end of the switch tube, a first end of the switch tube is grounded, a second end of the switch tube is connected to the primary winding of the transformer, a Comp pin of the control chip is connected to the first end of the capacitor module, and a second end of the capacitor module is grounded; The delay module comprises: A signal amplifying unit, configured to amplify the first voltage to obtain a first amplified signal, and amplify the second voltage to obtain a second amplified signal; wherein the first voltage and the second voltage are the voltages of the FB pin of the control chip when the switch tube is turned on and off, respectively; a current mirror unit, connected to the signal amplifying unit, and configured to mirror-copy the first amplified signal and the second amplified signal; A signal generating unit is connected to the current mirror unit and is used to generate the target delay signal according to the first amplified signal and the second amplified signal output by the current mirror unit.

2. The PFC circuit applied to Flyback according to claim 1, characterized in that: The voltage dividing module comprises: a first resistor and a second resistor; The first end of the first resistor is connected to the second end of the secondary winding of the transformer, the second end of the first resistor is respectively connected to the FB pin of the control chip and the first end of the second resistor, and the second end of the second resistor is grounded.

3. The PFC circuit applied to Flyback according to claim 1, characterized in that: The first voltage and the second voltage are obtained by sampling the auxiliary winding of the transformer.

4. The PFC circuit applied to Flyback according to claim 3, characterized in that: The signal amplification unit includes: an operational amplifier, an NMOS tube and a third resistor; The output end of the operational amplifier is connected to the gate of the NMOS tube, the positive input end of the operational amplifier is used to receive the first voltage and the second voltage, the negative input end of the operational amplifier is respectively connected to the source of the NMOS tube and the first end of the third resistor, the second end of the third resistor is grounded, and the drain of the NMOS tube is used to output the first amplified signal and the second amplified signal.

5. The PFC circuit applied to Flyback according to claim 4, characterized in that: The current mirror unit includes: a first PMOS tube, a second PMOS tube and a third PMOS tube; The drain of the NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube. The source of the first PMOS tube is connected to the source of the second PMOS tube and the source of the third PMOS tube respectively, the drain of the second PMOS tube is used to output the first amplified signal, and the drain of the third PMOS tube is used to output the second amplified signal.

6. The PFC circuit applied to Flyback according to claim 5, characterized in that: The signal generating unit includes: a first switch, a second switch, a first capacitor, a second capacitor and a comparator; Among them, the first end of the first switch is connected to the drain of the second PMOS tube, the second end of the first switch is respectively connected to the positive input end of the comparator and the first end of the first capacitor, the second end of the first capacitor is grounded, the first end of the second switch is connected to the drain of the third PMOS tube, the second end of the second switch is respectively connected to the first end of the second capacitor and the negative input end of the comparator, the second end of the second capacitor is grounded, and the output end of the comparator is used to output the target delay signal.

7. The PFC circuit applied to Flyback according to claim 6, characterized in that: The capacitance of the first capacitor is equal to that of the second capacitor.

8. The PFC circuit applied to Flyback according to claim 1, characterized in that: Also includes: The AND gate circuit is used to compensate the conduction time of the switch tube through the target delay signal.

9. A switching power supply, characterized in that: The invention comprises a PFC circuit applied to Flyback as claimed in any one of claims 1 to 8.

Images