Low-latency digital and analog dual-channel synchronous display method and system

Abstract

The present application discloses a low-latency digital and analog dual-channel synchronous display method and system, which relates to the field of image display, and writes detection images from different detectors into a memory device; calculates the line-by-line display timing parameters and generates the line-by-line display timing according to the line-by-line display resolution of the line-by-line display, and reads the image data of the detection image from the memory; performs image processing on the read image data, and sends them to the line-by-line display for line-by-line encoding display and image scaling processing; performs line-by-line conversion to interlaced operation on the scaled image to generate odd-field image data and even-field image data; interlaced encodes the odd-field image data and the even-field image data, and sends them to the interlaced display for interlaced encoding display. The internal logic resources of the chip are used to generate the timing control logic for digital and analog signals, and the corresponding timing logic is used at different stages to adjust and encode the image data, so as to achieve the effect of digital and analog synchronous display with one access, and reduce the memory bandwidth occupancy rate.

Description

Technical Field

[0001] The present application relates to the field of image display, and in particular to a low-latency digital and analog dual-channel synchronous display method and system. Background Art

[0002] At present, in low-power, low-latency, miniaturized mobile optoelectronic devices, high-definition micro-displays combined with eyepiece magnification are usually used for display. At the same time, in order to facilitate video acquisition and transmission by external display, analog video output is usually used to synchronize the detection video output and display. The display solutions of related products are as follows: Figure 1 As shown. Digital microdisplays usually use 24-bit RGB / YCbCr data parallel transmission and independent transmission of synchronization signals to drive the display. Its display frame rate, line blanking and frame blanking can be flexibly set. Analog video usually uses PAL video output interface and uses BT656 video encoding protocol to drive analog encoding chip. In hardware, only two ordinary signal lines are needed to output and display the video synchronously. It is easy to use and has a simple interface. Therefore, it is widely used in low-power, low-latency, miniaturized mobile optoelectronic devices. Digital microdisplays usually use silicon-based OLED displays below 1 inch. This type of display can receive the drive of high-definition progressive parallel digital video and display images in real time at a high frame rate. The resolution of this type of display can usually reach 1280×1024 and above. Its display pixel arrangement format is usually RGB or YCbCr and other forms. The settings of line blanking, frame blanking and display frame rate are relatively flexible, which can provide users with real-time digital display images with high image quality. It is mostly used for real-time observation through eyepieces.

[0003] Although analog video has a simple interface and greatly reduces the difficulty of product hardware design, it usually uses the BT656 video encoding protocol, which has specific and clear constraints. Unlike digital video, which uses progressive scanning, BT656 video uses interlaced scanning and embeds the synchronization signal into the data. The driving encoding method is relatively complex, and the video frame rate and pixel clock, line blanking and frame blanking duration are all fixed values, which greatly restricts the flexibility of the processing circuit.

[0004] In the traditional dual-channel display technology solution, the image needs to be read and written twice, which occupies a large amount of memory bandwidth, is not conducive to system stability and low power consumption performance. In addition, interlaced video introduces additional time overhead due to memory, resulting in increased delay in analog interlaced display, and the two have the problem of display asynchrony. Summary of the invention

[0005] The embodiments of the present application provide a low-latency digital and analog dual-channel synchronous display method and system to solve the problems of digital and analog dual-channel synchronous display in terms of flexibility, large latency and display asynchrony.

[0006] On the one hand, the present application provides a low-latency digital and analog dual-channel synchronous display method, the method comprising:

[0007] Writing detection images from different detectors into a memory device and performing time alignment on the detection images;

[0008] Calculating a progressive display timing parameter and generating a progressive display timing according to a progressive display resolution of a progressive display, and reading the image data of the detection image from a memory according to the generated progressive display timing; the progressive display timing parameter includes a pixel clock, a line blanking, and a frame blanking parameter;

[0009] The read image data is processed into images, and the image data is sent to a progressive display for progressive encoding display and image scaling processing;

[0010] The scaled image is subjected to a progressive-to-interlaced conversion operation to generate odd-field image data and even-field image data;

[0011] The odd field image data and the even field image data are interlaced encoded and sent to an interlaced display for interlaced encoding display.

[0012] Specifically, the step of calculating the line-by-line display timing parameters according to the line-by-line display resolution of the line-by-line display includes:

[0013] Set the progressive readout timing frame rate, line blanking, frame blanking and progressive pixel clock, aiming to make the time taken for every two lines of valid data of progressive video equal to the time taken for every line of valid data of interlaced data, and construct the following relational expression of blanking parameters:

[0014]

[0015]

[0016] With the goal of ensuring that the time for each two frames to correspond line by line is equal to the time for odd and even field interlaced video, the following relational expression of blanking parameters is constructed:

[0017]

[0018] in, represents the progressive pixel clock, m represents the row pixels of the progressively displayed image, n represents the column pixels of the progressively displayed image, h represents the number of row blanking pixels, v represents the number of frame blanking pixels, and f represents the progressive readout timing frame rate.

[0019] Specifically, the step of reading the image data of the detection image from the memory includes:

[0020] Based on the calculated line blanking pixel number h, frame blanking pixel number v and line-by-line pixel clock Generate line-by-line display timing;

[0021] According to the line-by-line pixel clock The odd-numbered line data and even-numbered line data of the detection image are extracted line by line from the memory frame by frame and used as output image data; the odd-numbered line data constitute the odd field data of the interlaced video, and the even-numbered line data constitute the even field data of the interlaced video.

[0022] Specifically, the step of sending the image data to the progressive display for progressive encoding and display and image scaling includes:

[0023] The image data is multiplexed in two channels, one channel is used as a digital signal and sent to the progressive display for progressive encoding and display, and the other channel is used as an analog signal to continue image scaling according to the size of the interlaced display.

[0024] Specifically, the image scaling process includes:

[0025] The image data is scaled to a resolution of 720×576 using a bilinear interpolation algorithm or a bicubic interpolation algorithm.

[0026] Specifically, performing a progressive-to-interlaced conversion operation on the scaled image to generate odd-field image data and even-field image data includes:

[0027] According to the preset timing interval, the first frame after scaling is used as the odd field image, and the odd-numbered line data of the first frame is retained; the second frame after scaling is used as the even field image, and the even-numbered line data of the second frame is retained, and so on, to form two odd and even field image data; the resolutions of the odd field image and the even field image are 720×288 respectively.

[0028] Specifically, the interlaced encoding of the odd field image data and the even field image data, and sending the interlaced encoding to an interlaced display for interlaced encoding display, includes:

[0029] Adjust the data timing of the generated odd field image data and even field image data according to the BT656 timing requirements;

[0030] The adjusted BT656 data is encoded and sent to the interlaced display for interlaced encoding display after analog display driving.

[0031] On the other hand, the present application provides a low-latency digital and analog two-way synchronous display system, which is used for the low-latency digital and analog two-way synchronous display method described in the above aspects, and the system includes an FPGA chip, a crystal oscillator and a memory device connected to the FPGA chip; the FPGA chip is connected to an external detector through an input interface, and is connected to a progressive display and an interlaced display through an output interface; the FPGA chip includes:

[0032] A memory read-write module is used to write the detection image and read out the detection image data line by line according to the corresponding timing control;

[0033] An image processing module, connected to the output of the memory read-write module, performs image processing on the input detection image data, and sends the image data to the image scaling module and the line-by-line display;

[0034] An image scaling module is used to connect to the output of the image processing and scale the input image data;

[0035] The progressive-to-interlaced module is used to connect the scaled image output by the image scaling module and convert the scaled image data into odd-field image data and even-field image data according to the timing control;

[0036] The interlaced encoding module is used to connect the output of the progressive-to-interlaced module, perform interlaced encoding on the odd-field image data and the even-field image data according to the timing control, and send the encoded data to the interlaced display.

[0037] Specifically, the memory read-write module includes two write units, an arbitration unit and a read unit;

[0038] The arbitration unit is connected to the two write units and the read unit respectively, and controls the read and write operation states of the write unit and the read unit;

[0039] The two writing units respectively write the detector images input by the detectors connected to them into the memory device according to the instructions of the arbitration unit;

[0040] The readout unit is used to read out the detector image data stored in the memory device to the image processing module according to the instruction of the arbitration unit.

[0041] Specifically, the FPGA chip also includes a clock management module and a line-by-line video timing module;

[0042] The line-by-line video timing module is connected to the clock management module, calculates the line-by-line display timing parameters according to the system clock generated by the clock management module and the line-by-line display resolution, and generates the line-by-line display timing according to the line-by-line display timing parameters; the readout unit reads the detector image data from the memory device according to the line-by-line display timing.

[0043] Specifically, the FPGA chip further includes an interlaced timing adjustment module, and the interlaced encoding module includes a progressive-to-interlaced unit and a BT656 encoding unit;

[0044] The interlaced timing adjustment module generates an interlaced timing according to the system clock of the clock management module. The line-to-line interlaced conversion unit adjusts the data timing of the odd field image data and the even field image data according to the BT656 timing requirements according to the interlaced timing, and sends the adjusted BT656 data to the BT656 encoding unit; the BT656 encoding unit encodes and outputs the BT656 data.

[0045] Specifically, the FPGA chip also includes a digital display driver module and an analog display driver module; the digital display driver module is connected to the output of the image processing module to drive the line-by-line display to display digital video; the analog display driver module is connected to the output of the BT656 encoding unit to convert the data from digital signals to analog signals for analog video display.

[0046] The beneficial effects of the technical solution provided by the embodiment of the present application include at least: writing the detection images from different detectors into the memory for timing alignment, and designing a memory read operation that only needs one time to meet the needs of line-by-line display and the analog video processing needs of image scaling and timing adjustment by FPGA on-chip resources in response to the needs of two-way display and their respective characteristics. In comparison, its external storage resources and storage bandwidth are smaller, and more storage resources can be saved for other image processing, and the digital line-by-line display and analog interlaced display have good synchronization and strong real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a structural schematic diagram of a related dual-channel synchronous display product;

[0048] Figure 2 It is a schematic diagram of the principle of a dual-channel display system implementation scheme in the related art;

[0049] Figure 3 It is a structural schematic diagram of a low-latency digital and analog dual-channel synchronous display system provided by an embodiment of the present application;

[0050] Figure 4 is a flow chart of a low-latency digital and analog dual-channel synchronous display method provided by an embodiment of the present application;

[0051] Figure 5 It is a schematic diagram of the data processing flow of dual-channel synchronous display provided by an embodiment of the present application;

[0052] Figure 6 This is a schematic diagram of the internal resource management architecture of the FPGA chip provided by this application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0054] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0055] In response to the needs of low-power, miniaturized mobile optoelectronic devices in multi-channel video input processing and multi-channel video display, the commonly used technical solution is to use FPGA chips and memory devices (such as SDRAM\LPDDR\DDR3, etc.) to directly drive the digital micro display according to the resolution size of the display screen for the processed image. At the same time, the FPGA uses the memory device again to perform image scaling and timing adjustment based on the timing and resolution of BT656, and performs line-by-line conversion to interlaced operation to achieve dual-channel video display driving. The implementation method is as follows: Figure 2 shown.

[0056] from Figure 2 It can be seen that this dual-channel display technology solution is divided into two major steps. The first step is to write the data of the original image into memory address 1 after the previous image processing, and generate a timing that meets the requirements of the progressive display according to the timing requirements of the progressive display. The image data is read from address 1 for image processing and then the progressive display is driven to display the image. At the same time, the processed image is written again to address 2 of the storage device, and then a data read timing that meets the BT656 timing requirements is designed. According to the data read timing, the interlaced data is read again from address 2 in the memory for image scaling processing, and finally the BT656 encoding drive and analog video drive display are realized.

[0057] Figure 2 The implementation scheme of the dual-channel display system has two main disadvantages: first, the memory bandwidth is large, and the image data needs to be read and written twice, which greatly increases the memory read and write bandwidth occupancy rate, which is not conducive to system stability. At the same time, a large amount of logical resources are wasted for multiple reading and writing of memory, which is not conducive to the low power consumption performance of the system. Secondly, the interlaced analog display lags behind the progressive digital image display. Interlaced video requires writing progressive data to the memory again, which introduces additional time overhead, resulting in an increase in the delay of the analog interlaced display. There is a problem of display asynchrony between the two. This application focuses on solving the above two problems through system and timing design.

[0058] Figure 3It is a structural diagram of a low-latency digital and analog dual-channel synchronous display system provided by an embodiment of the present application, and the system includes an FPGA chip, a crystal oscillator connected to the FPGA chip, and a memory device. In a possible implementation, the FPGA chip is connected to an external detector via an input interface, and is connected to a progressive display and an interlaced display via an output interface. The memory can be a dynamic random access memory such as SDRAM, LPDDR, DDR2, DDR3, DDR4, etc. The progressive display of the present application is a device for displaying digital signals, and the interlaced display is a device for displaying analog signals. In addition, the system is also provided with a FLASH storage device for storing data and cache information. The FPGA chip collects the detection image of the detector end according to the instruction, and processes the image and sends it to the progressive display and the interlaced display for synchronous display.

[0059] Figure 4 : is a flow chart of a low-latency digital and analog dual-channel synchronous display method provided by an embodiment of the present application. The method is specifically applied to a FGPA chip and may include the following steps:

[0060] S1, write the detection images from different detectors into the memory device and perform time alignment on the detection images;

[0061] The detection image of this application is from two different non-detected images, such as Figure 5 As shown in the data processing flow diagram of dual-channel synchronous display, the memory device will synchronously read and align the writing of two detection images according to the system timing.

[0062] S2, calculating a line-by-line display timing parameter and generating a line-by-line display timing according to a line-by-line display resolution of the line-by-line display, and reading image data of the detection image from a memory according to the generated line-by-line display timing;

[0063] This stage is mainly for the memory data readout stage. If you want to reduce the memory bandwidth usage, you need to optimize the image data reading method. This application uses digital signal display as a prerequisite to extract image data. Digital display uses line-by-line encoding display, so it is necessary to build a line-by-line display timing for line-by-line encoding display. This timing design needs to consider the line-by-line display resolution of the line-by-line display and calculate the line-by-line display timing parameters. The line-by-line display timing parameters in this application include pixel clock , line blanking and frame blanking pixel number parameters. These parameters need to obtain the display device parameters in advance, such as the line-by-line display resolution, row and column pixel size and other data, so as to design a pixel clock that meets the digital image display , image reading and outputting the image data of the detection image at this time sequence frequency.

[0064] S3, processing the read image data into images, and sending the image data to a progressive display for progressive encoding display and image scaling processing;

[0065] For the extracted image data, a dual-channel multiplexing scheme is used for synchronous display. After the image processing, one of the channels is directly used as a digital display signal and sent to the line-by-line display for line-by-line encoding display, and the other channel is used as a subsequent analog signal display for scaling processing. In this application, the size of the interlaced display is smaller than the size of the original detection image, so the image scaling in this step is to adapt to the size of the model display.

[0066] S4, performing a progressive-to-interlaced conversion operation on the scaled image to generate odd-field image data and even-field image data;

[0067] The scaled image after scaling is essentially still extracted according to the pixel clock of the original progressive display, so it must be converted before interlaced encoding display, that is, the image data is adjusted from progressive to interlaced. In response to this operation scheme, the present application numbers the image frames according to the reading timing, and starts to operate the image data in a timely manner at the set time, and defines the sequence into odd-numbered row data and even-numbered row data. The odd-numbered row data constitutes the odd-field image data, and the even-numbered row data constitutes the even-field image data. The odd-field image data and the even-field image data are the data sources for the subsequent interlaced display.

[0068] S5, interlacing-encode the odd-field image data and the even-field image data, and send them to an interlaced display for interlaced-encoded display.

[0069] The interlaced encoding of mobile optoelectronic devices needs to be displayed in PAL mode video, so the signal encoding adjustment needs to be carried out according to its specific BT656 encoding format (that is, BT656 video encoding protocol). The encoded image data can then be sent to the interlaced display for interlaced encoding display.

[0070] In summary, through the technical solution designed in this application, the detection images from different detectors are written into the memory for timing alignment. In view of the two-way display requirements and in combination with their respective characteristics, a memory read operation is designed that only requires one operation to meet the requirements of line-by-line display and the analog video processing requirements of image scaling and timing adjustment using FPGA on-chip resources. In comparison, its external storage resources and storage bandwidth are smaller, and more storage resources can be saved for other image processing. The digital line-by-line display and analog interlaced display have good synchronization and strong real-time performance.

[0071] In some embodiments, in order to allow the digital signal display to directly drive the progressive display display without other redundant data processing and adjustment, the present application may specifically design the progressive display timing parameters, which may include the following steps:

[0072] Design the frame rate f of the progressive readout timing, design the pixel clock pclk of the progressive readout timing, and assume that the number of row pixels of the progressive display resolution is m, and the number of column pixels is n. In order to minimize the use of internal resources of the FPGA, the time required for each 2 lines of valid data of the progressive video is equal to the time required for each line of valid data of the interlaced data. Therefore, the number of pixels per line m and the pixel clock pclk of the progressive display image satisfy the following relationship:

[0073]

[0074] Continuing with the number of line blanking pixels h and frame blanking pixels v, m, n, h, v and pclk should satisfy the following relationship:

[0075]

[0076] Furthermore, in order to use the storage resources inside the FPGA for progressive and interlaced operations, the odd and even fields of the interlaced video are formed by extracting the odd and even lines of data from every two frames. In terms of timing, the time corresponding to every two frames is equal to the time used for two fields of interlaced video, and the following relational expression of the blanking parameters is constructed:

[0077]

[0078] in, represents the progressive pixel clock, m represents the row pixels of the progressively displayed image, n represents the column pixels of the progressively displayed image, h represents the number of row blanking pixels, v represents the number of frame blanking pixels, and f represents the progressive readout timing frame rate.

[0079] The above three expressions can be used to calculate the pixel clock pclk, line blanking h and frame blanking v pixel values ​​for a specific progressive display, and then the progressive display timing can be generated based on these parameters.

[0080] In the data reading phase, according to the line-by-line pixel clock The odd-numbered line data and even-numbered line data of the detection image are extracted line by line from the memory frame by frame and used as output image data, wherein the odd-numbered line data constitutes the odd field data of the interlaced video, and the even-numbered line data constitutes the even field data of the interlaced video.

[0081] The image data is double-multiplexed, one channel is used as a digital signal and sent to the progressive display for progressive encoding and display, and the other channel is used as an analog signal to continue image scaling according to the size of the interlaced display. For the image processing step, the image data can be scaled to a resolution of 720×576 using a bilinear interpolation algorithm or a bicubic interpolation algorithm.

[0082] In particular, in the above formula, because the international standard of analog PAL video uses a 27MHz pixel clock, its resolution can only be 720×576, and 720 represents the number of pixels in the horizontal direction. And 1728 is the total number of effective pixels in a line of PAL video, which includes 1440 image data, 720 grayscale components, 720 color components, and 288 blanking data.

[0083] Because the phase sequence step is designed with the goal of equalizing the time between two frames and the time of odd and even field interlaced video, its purpose is essentially to generate odd field image data and even field image data later. Therefore, the step of converting the scaled image to interlaced line by line can specifically include the following steps:

[0084] According to the preset timing interval, the first frame after scaling is used as the odd field image, and the odd-numbered line data of the first frame is retained; the second frame after scaling is used as the even field image, and the even-numbered line data of the second frame is retained, and so on, to form two odd and even field image data; the resolutions of the odd field image and the even field image are 720×288 respectively.

[0085] Furthermore, the internal storage resources of the FPGA are used to adjust the data timing of the generated odd-field image data and the even-field image data according to the BT656 timing requirements; then the adjusted BT656 data is encoded, and the synchronization signal and the blanking signal are embedded into the encoded data through encoding, and then converted through a digital-to-analog driver chip or module and sent to the interlaced display for interlaced encoded display.

[0086] The above solution is mainly aimed at FPGA image processing and encoding systems. Through system timing design and writing corresponding modules based on the FPGA platform, it can achieve synchronous display of progressive digital video and interlaced analog video with less time and resource consumption.

[0087] Figure 6 This is a schematic diagram of the internal resource management architecture of the FPGA chip provided by this application, which specifically includes:

[0088] A memory read-write module is used to write the detection image and read out the detection image data line by line according to the corresponding timing control;

[0089] An image processing module, connected to the output of the memory read-write module, performs image processing on the input detection image data, and sends the image data to the image scaling module and the line-by-line display;

[0090] An image scaling module is used to connect to the output of the image processing and scale the input image data;

[0091] The progressive-to-interlaced module is used to connect the scaled image output by the image scaling module and convert the scaled image data into odd-field image data and even-field image data according to the timing control;

[0092] The interlaced encoding module is used to connect the output of the progressive-to-interlaced module, perform interlaced encoding on the odd-field image data and the even-field image data according to the timing control, and send the encoded data to the interlaced display.

[0093] Because it is a dual-detection image input, the memory read-write module includes two write units, an arbitration unit, and a read-out unit;

[0094] The arbitration unit is connected to the two write units and the read unit respectively, and controls the read and write operation states of the write unit and the read unit;

[0095] The two writing units respectively write the detector images input by the detectors connected to them into the memory device according to the instructions of the arbitration unit;

[0096] The readout unit is used to read out the detector image data stored in the memory device to the image processing module according to the instruction of the arbitration unit.

[0097] In order to realize different timing control of each module, a clock management module and a line-by-line video timing module are also designed in the FPGA chip;

[0098] The line-by-line video timing module is connected to the clock management module, calculates the line-by-line display timing parameters according to the system clock generated by the clock management module and the line-by-line display resolution, and generates the line-by-line display timing according to the line-by-line display timing parameters; the readout unit reads the detector image data from the memory device according to the line-by-line display timing.

[0099] In addition, the FPGA chip also includes an interlaced timing adjustment module, because the progressive video timing module is specifically designed to generate timing control for digital signal transmission, while the interlaced timing adjustment module is for timing control of analog signal transmission. The interlaced encoding module includes a progressive to interlaced unit and a BT656 encoding unit;

[0100] The interlaced timing adjustment module generates an interlaced timing according to the system clock of the clock management module. The line-to-line interlaced unit adjusts the odd-field image data and the even-field image data according to the BT656 timing requirements according to the interlaced timing, and sends the adjusted BT656 data to the BT656 encoding unit; the BT656 encoding unit encodes the BT656 data.

[0101] Optionally, the FPGA chip also includes a digital display driver module and an analog display driver module. The digital display driver module is connected to the output of the image processing module to drive the line-by-line display for digital video display; the analog display driver module is connected to the output of the BT656 encoding unit to drive the interlaced display for analog video display. Alternatively, the interlaced display may include an analog encoding chip (i.e., an analog display driver module), and the FPGA chip directly outputs the output through the BT656 encoding unit, and then the digital signal is converted by the analog display driver module of the display to display an analog image.

[0102] by Figure 3 For example, Xilinx A7 series FPGA XC7A50T is selected, the memory is Tsinghua Unigroup's 1Gb DDR3 random dynamic memory MT41K64M16, the line-by-line display is Orled's SXGA060 micro display, with a resolution of 1280×1024; the analog video encoding is ADI's ADV7393 encoding chip. The input video is input to the FPGA through the input interface, and the processed display video is output to the line-by-line display and analog encoding chip through the output interface.

[0103] The system executes as follows:

[0104] Step 1: External video is input into FPGA through the input interface;

[0105] Step 2: The frame rate of the line-by-line display is designed to be f=50Hz;

[0106] Step 3: Based on the display resolution m=1280, n=1024, the pixel clock pclk can be calculated as:

[0107] Hz

[0108] Step 4: The number of pixels to be blanked line by line is h=448, and the vertical blanking v can be calculated to be 150528.

[0109] Step 5: Use the crystal oscillator input clock combined with the clock management module inside the FPGA to generate a 96MHz clock and generate a row-by-row readout timing with a resolution of 1280×1024, a row blanking of 448 pixels, and a frame blanking of 150528 pixels;

[0110] Step 6: Perform subsequent image processing according to the timing generated in step 5, including progressive display, progressive conversion to interlaced, image scaling, and interlaced encoding. Progressive conversion to interlaced and interlaced timing adjustment can be achieved through the storage resources inside the FPGA.

[0111] It is particularly noted that the above solution can also be used to calculate the corresponding timing parameters for other display resolutions such as 800×600 for progressive display.

[0112] In summary, the present application utilizes the internal logic resources of the FPGA chip to generate timing control logic for digital signals and analog signals, and uses the corresponding timing logic to adjust and encode the image data at different stages, so that the effect of digital and analog synchronous display can be achieved with a single memory read, thereby reducing memory bandwidth occupancy.

[0113] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A low-latency digital and analog dual-channel synchronous display method, characterized in that: The method comprises: Writing detection images from different detectors into a memory device and performing time alignment on the detection images; Calculate the progressive display timing parameters and generate the progressive display timing according to the progressive display resolution of the progressive display, and read the image data of the detection image from the memory according to the generated progressive display timing; the progressive display timing parameters include pixel clock, line blanking and frame blanking parameters; specifically set the progressive readout timing frame rate, line blanking, frame blanking and progressive pixel clock, with the goal of making the time taken for every two lines of valid data of the progressive video equal to the time taken for every line of valid data of the interlaced data, and construct the following relational expression of the blanking parameters: With the goal of ensuring that the time for each two frames to correspond line by line is equal to the time for odd and even field interlaced video, the following relational expression of blanking parameters is constructed: in, represents the line-by-line pixel clock, m represents the row pixels of the line-by-line displayed image, n represents the column pixels of the line-by-line displayed image, h represents the number of line blanking pixels, v represents the number of frame blanking pixels, and f represents the line-by-line readout timing frame frequency; The read image data is processed into images, and the image data is double-multiplexed, one of which is directly sent to the progressive display as a digital signal for progressive encoding and display, and the other is output as a subsequent analog signal for image scaling processing; For analog signal output, the scaled image is converted from line to interlaced, and odd-field image data and even-field image data are sequentially numbered according to the pixel clock sequence; The odd field image data and the even field image data are interlaced encoded according to the BT656 encoding format, and sent to an interlaced display for interlaced encoding display.

2. The method according to claim 1, characterized in that The step of reading the image data of the detection image from the memory comprises: Based on the calculated line blanking pixel number h, frame blanking pixel number v and line-by-line pixel clock Generate line-by-line display timing; According to the line-by-line pixel clock The odd-numbered line data and even-numbered line data of the detection image are extracted line by line from the memory frame by frame and used as output image data; the odd-numbered line data constitute the odd field data of the interlaced video, and the even-numbered line data constitute the even field data of the interlaced video.

3. The method according to claim 1, characterized in that The step of sending the image data to the progressive display for progressive encoding and display and image scaling includes: The image data is multiplexed in two channels, one channel is used as a digital signal and sent to the progressive display for progressive encoding and display, and the other channel is used as an analog signal to continue image scaling according to the size of the interlaced display.

4. The method according to claim 3, characterized in that: Image scaling processing includes: The image data is scaled to a resolution of 720×576 using a bilinear interpolation algorithm or a bicubic interpolation algorithm.

5. The method according to claim 2, characterized in that: The step of performing a progressive-to-interlaced conversion operation on the scaled image to generate odd-field image data and even-field image data includes: According to the preset timing interval, the first frame after scaling is used as the odd field image, and the odd-numbered line data of the first frame is retained; the second frame after scaling is used as the even field image, and the even-numbered line data of the second frame is retained, and so on, to form two odd and even field image data; the resolutions of the odd field image and the even field image are 720×288 respectively.

6. The method according to claim 5, characterized in that The step of interlacing the odd field image data and the even field image data and sending the interlaced encoding data to an interlaced display for interlaced encoding display comprises: Adjust the data timing of the generated odd field image data and even field image data according to the BT656 timing requirements; The adjusted BT656 data is encoded and sent to the interlaced display for interlaced encoding display after analog display driving.

7. A low-latency digital and analog dual-channel synchronous display system, characterized in that: A low-latency digital and analog dual-channel synchronous display method according to any one of claims 1 to 6, wherein the system comprises an FPGA chip, a crystal oscillator and a memory device connected to the FPGA chip; the FPGA chip is connected to an external detector via an input interface, and is connected to a progressive display and an interlaced display via an output interface; the FPGA chip comprises: A memory read-write module is used to write the detection image and read out the detection image data line by line according to the corresponding timing control; An image processing module, connected to the output of the memory read-write module, performs image processing on the input detection image data, and sends the image data to the image scaling module and the line-by-line display; An image scaling module is used to connect to the output of the image processing and scale the input image data; The progressive-to-interlaced module is used to connect the scaled image output by the image scaling module and convert the scaled image data into odd-field image data and even-field image data according to the timing control; The interlaced encoding module is used to connect the output of the progressive-to-interlaced module, perform interlaced encoding on the odd-field image data and the even-field image data according to the timing control, and send the encoded data to the interlaced display.

8. The low-latency digital and analog dual-channel synchronous display system according to claim 7, characterized in that: The memory read-write module includes two write units, an arbitration unit and a read unit; The arbitration unit is connected to the two write units and the read unit respectively, and controls the read and write operation states of the write unit and the read unit; The two writing units respectively write the detector images input by the detectors connected to them into the memory device according to the instructions of the arbitration unit; The readout unit is used to read out the detector image data stored in the memory device to the image processing module according to the instruction of the arbitration unit.

9. The low-latency digital and analog dual-channel synchronous display system according to claim 8, characterized in that: The FPGA chip also includes a clock management module and a line-by-line video timing module; The progressive video timing module is connected to the clock management module, calculates the progressive display timing parameters according to the system clock generated by the clock management module and the progressive display resolution, and generates the progressive display timing according to the progressive display timing parameters; The readout unit reads the detector image data from the memory device according to a line-by-line display timing.

10. The low-latency digital and analog dual-channel synchronous display system according to claim 8, characterized in that: The FPGA chip also includes an interlaced timing adjustment module, and the interlaced encoding module includes a progressive to interlaced unit and a BT656 encoding unit; The interlaced timing adjustment module generates an interlaced timing according to the system clock of the clock management module. The line-to-line interlaced conversion unit adjusts the data timing of the odd field image data and the even field image data according to the BT656 timing requirements according to the interlaced timing, and sends the adjusted BT656 data to the BT656 encoding unit; the BT656 encoding unit encodes and outputs the BT656 data.

11. The low-latency digital and analog dual-channel synchronous display system according to claim 10, characterized in that: The FPGA chip also includes a digital display driver module and an analog display driver module; the digital display driver module is connected to the output of the image processing module to drive the line-by-line display to display digital video; the analog display driver module is connected to the output of the BT656 encoding unit to convert data from digital signals to analog signals for analog video display.

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