Chip and method for preparing the same

Abstract

The present invention provides a chip and a preparation method thereof, and relates to the technical field of semiconductor lasers. The chip comprises: a semiconductor layer structure, a first electrode, a second electrode and a dielectric layer. The semiconductor layer structure comprises an ohmic contact layer and a P-type cladding layer arranged in sequence from top to bottom, and the doping concentration of the ohmic contact layer is higher than the doping concentration of the P-type cladding; the area of ​​the ohmic contact layer is smaller than the area of ​​the P-type cladding, so that a part of the upper surface of the P-type cladding is not covered by the ohmic contact layer; the first electrode is connected to the ohmic contact layer, and the contact resistance between the first electrode and the ohmic contact layer is Rc1; the second electrode is connected to a part of the P-type cladding layer that is not covered by the ohmic contact layer, and the contact resistance between the second electrode and the part of the P-type cladding layer that is not covered by the ohmic contact layer is Rc2, and Rc2 is greater than Rc1; the dielectric layer is connected to the ohmic contact layer; and in the transverse direction, the dielectric layer is located between the first electrode and the second electrode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to a chip and a preparation method thereof. Background Art

[0002] The existing two-stage chip has two parts in the horizontal direction, a first part and a second part. The first part has a first electrode and the second part has a second electrode. A segmented power supply is usually adopted, that is, a first voltage is applied to the first electrode and a second voltage is applied to the second electrode, so that the first part generates a larger current and the second part generates a smaller current.

[0003] The existing power supply method of the dual-stage chip requires two power supply circuits, which has a complex structure and is not conducive to the large-scale application of the dual-stage chip. Summary of the invention

[0004] The object of the present invention is to provide a chip and a method for preparing the same, so as to alleviate the problem that two power supply circuits are required for power supply in the existing dual-stage chip.

[0005] In a first aspect, the present invention provides a chip, comprising:

[0006] A semiconductor layer structure, wherein the semiconductor layer structure comprises an ohmic contact layer and a P-type cladding layer arranged in sequence from top to bottom, wherein the doping concentration of the ohmic contact layer is higher than the doping concentration of the P-type cladding layer; and the area of ​​the ohmic contact layer is smaller than the area of ​​the P-type cladding layer, so that a portion of the upper surface of the P-type cladding layer is not covered by the ohmic contact layer;

[0007] A first electrode, the first electrode is connected to the ohmic contact layer, and a contact resistance between the first electrode and the ohmic contact layer is Rc1;

[0008] A second electrode, the second electrode is connected to a portion of the P-type cladding layer that is not covered by the ohmic contact layer, and a contact resistance between the second electrode and the portion of the P-type cladding layer that is not covered by the ohmic contact layer is Rc2, and Rc2 is greater than Rc1;

[0009] A dielectric layer is connected to the ohmic contact layer; the dielectric layer is located between the first electrode and the second electrode, so that the second electrode is spaced apart from the first electrode.

[0010] Furthermore, from top to bottom, the doping concentration of the P-type cladding layer decreases gradually;

[0011] An upper surface of a portion of the P-type cladding layer that is not covered by the ohmic contact layer is lower than an upper surface of a portion of the P-type cladding layer that is covered by the ohmic contact layer.

[0012] Furthermore, the value range of Rc2 / Rc1 is less than or equal to 200.

[0013] Furthermore, the value range of Rc2 / Rc1 is between 40-100.

[0014] Furthermore, the doping concentration of the ohmic contact layer is greater than 1×10 19 ;

[0015] The doping concentration of the part of the P-type cladding layer not covered by the ohmic contact layer is less than 5×10 18 .

[0016] Furthermore, the lower surface of the dielectric layer contacts the upper surface of the ohmic contact layer.

[0017] Furthermore, the lower surface of the dielectric layer is connected to a portion of the P-type cladding layer that is not covered by the ohmic contact layer.

[0018] Furthermore, a portion of the P-type cladding layer that is not covered by the ohmic contact layer is provided with a downwardly extending groove, and the groove is formed by extending downward from the bottom of the dielectric layer.

[0019] Furthermore, the groove includes a first groove wall and a second groove wall arranged in a transverse direction, the first groove wall is close to the first electrode, and the second groove wall is close to the second electrode; the second groove wall extends in an up-down direction;

[0020] From top to bottom, there are at least two positions, wherein at the upper position, the distance between the second groove wall and the first groove wall is L1; at the lower position, the distance between the second groove wall and the first groove wall is L2, and L1 is greater than L2.

[0021] Furthermore, from top to bottom, the first groove wall is inclined toward one side of the second groove wall;

[0022] Alternatively, the first groove wall includes a first side wall and a second side wall connected in sequence from top to bottom, the first side wall and the second side wall both extend in the up-down direction, and the distance between the first side wall and the second groove wall is greater than the distance between the second side wall and the second groove wall.

[0023] In a second aspect, the present invention provides a method for preparing a chip, which is used to prepare the above-mentioned chip, comprising the steps of:

[0024] Step S1. preparing a semiconductor layer structure, the semiconductor layer structure comprising an ohmic contact layer and a P-type cladding layer arranged in sequence from top to bottom, wherein the doping concentration of the ohmic contact layer is higher than the doping concentration of the P-type cladding layer;

[0025] Step S2. etching a portion of the ohmic contact layer to expose a portion of the P-type cladding layer;

[0026] Step S3. preparing a dielectric layer on the top surface of the semiconductor layer structure; etching the dielectric layer to expose a portion of the ohmic contact layer and a portion of the P-type cladding layer;

[0027] Step S4. Deposit a metal layer and define a patterned metal structure, then form a first electrode on the upper surface of the ohmic contact layer and a second electrode on the upper surface of the exposed portion of the P-type cladding layer through an annealing process, wherein the first electrode and the second electrode are located on opposite sides of the dielectric layer.

[0028] The present invention has at least the following advantages or beneficial effects:

[0029] The chip provided by the present invention includes: a semiconductor layer structure, a first electrode, a second electrode and a dielectric layer, the semiconductor layer structure includes an ohmic contact layer and a P-type cladding layer arranged in sequence from top to bottom, the doping concentration of the ohmic contact layer is higher than the doping concentration of the P-type cladding; the area of ​​the ohmic contact layer is smaller than the area of ​​the P-type cladding, so that a part of the upper surface of the P-type cladding is not covered by the ohmic contact layer; the first electrode is connected to the ohmic contact layer, and the contact resistance between the first electrode and the ohmic contact layer is Rc1; the second electrode is connected to the part of the P-type cladding that is not covered by the ohmic contact layer, and the contact resistance between the second electrode and the part of the P-type cladding that is not covered by the ohmic contact layer is Rc2, and Rc2 is greater than Rc1; the dielectric layer is connected to the ohmic contact layer; and in the horizontal direction, the dielectric layer is located between the first electrode and the second electrode, so that the second electrode is spaced apart from the first electrode.

[0030] The first electrode is connected to the ohmic contact layer. Since the doping concentration in the ohmic contact layer is relatively high, after annealing, the ohmic contact layer contacts the first electrode, and a good ohmic contact can be formed, and the contact resistance Rc1 is relatively small. On the contrary, the second electrode is connected to the P-type cladding. Since the doping concentration in the P-type cladding is relatively low, after annealing, the P-type cladding is not in sufficient contact with the second electrode, forming a non-ohmic contact, and the contact resistance Rc2 is relatively large. The dielectric layer arranged between the first electrode and the second electrode plays an insulating role, and the same voltage can be applied to the first electrode and the second electrode using a circuit. Since Rc2 is greater than Rc1, the current of the corresponding part of the semiconductor layer structure under the first electrode is relatively large, while the current of the corresponding part of the semiconductor layer structure under the second electrode is relatively small. The chip provided in this embodiment can realize single-circuit power supply, and the power supply structure is simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of a chip provided in Example 1 of the present invention;

[0033] Figure 2 A schematic diagram of a chip provided in Example 2 of the present invention;

[0034] Figure 3 A schematic diagram of a first chip provided in Embodiment 3 of the present invention;

[0035] Figure 4 A schematic diagram of a second chip provided in Example 3 of the present invention;

[0036] Figure 5 This is a schematic diagram of a third chip provided in Example 3 of the present invention.

[0037] Icon: 1-substrate; 2-N-type cladding; 3-N-type waveguide layer; 4-quantum well; 5-P-type waveguide layer; 6-P-type cladding; 7-ohmic contact layer; 8-first electrode; 9-second electrode; 10-dielectric layer; 11-groove; 12-first groove wall; 13-second groove wall; 14-first sidewall; 15-second sidewall. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0041] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0042] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0043] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] Example 1

[0045] The semiconductor layer structure grows from the substrate 1 in a bottom-up direction. For the convenience of describing the chip structure, the substrate 1 side is set as the bottom side and the electrode side is set as the top side. Figure 1 As shown, the chip provided by the present invention includes: a semiconductor layer structure, the semiconductor layer structure includes an ohmic contact layer 7 and a P-type cladding layer 6 arranged in sequence from top to bottom, the doping concentration of the ohmic contact layer 7 is higher than the doping concentration of the P-type cladding layer 6; the area of ​​the ohmic contact layer 7 is smaller than the area of ​​the P-type cladding layer 6, so that a part of the upper surface of the P-type cladding layer 6 is not covered by the ohmic contact layer 7.

[0046] Specifically, the semiconductor layer structure may include a substrate 1, an N-type cladding layer 2, an N-type waveguide layer 3, a quantum well 4, a P-type waveguide layer 5, a P-type cladding layer 6 and an ohmic contact layer 7 which are sequentially connected from bottom to top.

[0047] The quantum well 4 is an undoped semiconductor material layer, and the doping concentration gradually increases from the quantum well 4 layer upward through the P-type waveguide layer 5, the P-type cladding layer 6 to the ohmic contact layer 7, wherein the doping concentration of the ohmic contact layer 7 is greater than 1×10 19The doping concentration of the P-type cladding layer 6 is less than the doping concentration of the ohmic contact layer 7. The doping concentrations of the P-type waveguide layer 5 and the P-type cladding layer 6 are gradually changed. For the semiconductor layer structure of gallium arsenic material, the element doped in the P-type cladding layer is carbon.

[0048] The upper surface area of ​​the ohmic contact layer 7 is smaller than that of the P-type cladding layer 6 and does not completely cover the upper surface of the P-type cladding layer 6 . A portion of the upper surface of the P-type cladding layer 6 is exposed for contact with the second electrode 9 during subsequent preparation.

[0049] During preparation, a first electrode 8 is prepared on the ohmic contact layer 7. After annealing, the contact resistance between the first electrode 8 and the ohmic contact layer 7 is Rc1. Correspondingly, the second electrode 9 is connected to the portion of the P-type cladding layer 6 that is not covered by the ohmic contact layer 7. After annealing, the contact resistance between the second electrode 9 and the portion of the P-type cladding layer 6 that is not covered by the ohmic contact layer 7 is Rc2. Since the first electrode 8 is in ohmic contact with the ohmic contact layer 7, and the second electrode 9 is in non-ohmic contact with the P-type cladding layer 6, Rc2 is much larger than Rc1. Moreover, Rc2 is less than 200 times Rc1.

[0050] Preferably, Rc2 is approximately 40 to 100 times greater than Rc1.

[0051] In this embodiment, the dielectric layer 10 is arranged on the upper surface of the ohmic contact layer 7. In the horizontal direction, the dielectric layer 10 is located between the first electrode 8 and the second electrode 9. For the convenience of explaining the structure, the side of the first electrode 8 is set as the left side, and the side of the second electrode 9 is set as the right side. The dielectric layer 10 is set at the right end of the first electrode 8, and correspondingly, the dielectric layer 10 is set at the left end of the second electrode 9. It is necessary to specially explain that the series resistance of the part of the semiconductor layer structure where the first electrode 8 is located is set as Rs1, and the value range of Rs1 is 0.05Ω-1Ω, and the series resistance of the part of the semiconductor layer structure where the second electrode 9 is located is set as Rs2, wherein the thinner the layer structure is, the smaller the resistance is, but the difference in thickness between the first part and the second part is only the thickness value of the ohmic contact layer 7, therefore, Rs1 is slightly larger than Rs2, and Rs1 is approximately 3 to 10 times of Rs2. On the basis that Rc2 is much larger than Rc1, the layer structure resistance has little effect on the overall value, therefore, (Rs1+Rc1) is smaller than (Rs2+Rc2). Since the input voltages are equal, according to the formula, I1×(Rc1+Rs1)=I2× (Rc2+Rs2) and related data, it can be obtained that the range of I1 is 1A-2A, the value range of I2 can be 10 mA -100 mA, I1 is the current of the partial semiconductor layer structure corresponding to the first electrode 8, and I2 is the current of the partial semiconductor layer structure corresponding to the second electrode 9.

[0052] The first electrode 8 is connected to the ohmic contact layer 7. Since the doping concentration in the ohmic contact layer 7 is relatively high, after annealing, the ohmic contact layer 7 is in contact with the first electrode 8, and a good ohmic contact can be formed, and the contact resistance Rc1 is relatively small. On the contrary, the second electrode 9 is connected to the P-type cladding 6. Since the doping concentration in the P-type cladding 6 is relatively low, after annealing, the P-type cladding 6 is not in sufficient contact with the second electrode 9, forming a non-ohmic contact, and the contact resistance Rc2 is relatively large. The dielectric layer 10 arranged between the first electrode 8 and the second electrode 9 plays an insulating role. The same voltage can be applied to the first electrode 8 and the second electrode 9 by a circuit. Since Rc2 is greater than Rc1, the current of the corresponding part of the semiconductor layer structure under the first electrode 8 is relatively large, and the current of the corresponding part of the semiconductor layer structure under the second electrode 9 is relatively large. The chip provided in this embodiment can realize single-circuit power supply, and the power supply structure is simpler. Improve the reliable working power and reliability of the chip and enhance product competitiveness.

[0053] From top to bottom, the doping concentration of the P-type cladding layer 6 gradually decreases; the upper surface of the portion of the P-type cladding layer 6 not covered by the ohmic contact layer 7 is lower than the upper surface of the portion of the P-type cladding layer 6 covered by the ohmic contact layer 7 .

[0054] The lower the doping concentration, the greater the contact resistance formed after annealing. Therefore, according to the expected contact resistance value of the partial semiconductor layer structure corresponding to the second electrode 9, it is possible to choose to etch the portion of the P-type cladding 6 not covered by the ohmic contact layer 7 before forming the second electrode 9 to reduce the height of this portion, thereby making the doping concentration at the contact position between the P-type cladding 6 and the second electrode 9 lower and the contact resistance greater.

[0055] Specifically, in this embodiment, the doping concentration of the ohmic contact layer 7 is greater than 1×10 19 The doping concentration of the portion of the P-type cladding layer 6 not covered by the ohmic contact layer 7 is less than 5×10 18 That is to say, the doping concentration in the P-type cladding layer 6 is greater than 5×10 18 The etching depth is about 300 nm to 500 nm. Of course, the etching can be continued downwards, for example, the P-type cladding layer 6 with a thickness greater than 5×10 16 The above highly doped parts are etched away, and the specific etching depth is about 1 micron.

[0056] It should be noted that the P-type waveguide layer 5 cannot be etched. The P-type waveguide layer 5 has a higher refractive index and is used to limit the waveguide. The P-type waveguide layer 5 is where the light field energy is concentrated. The deeper the P-type cladding layer 6 is etched below the second electrode 9, the more contact with the light field and the greater the loss. Therefore, the P-type cladding layer 6 cannot be etched too deep.

[0057] Example 2

[0058] like Figure 2 As shown, the difference from Embodiment 1 is that, in this embodiment, the lower surface of the dielectric layer 10 is connected to the portion of the P-type cladding layer 6 that is not covered by the ohmic contact layer 7. That is, when preparing the chip, the ohmic contact layer 7 at the corresponding position of the dielectric layer 10 is also etched away, so that the dielectric layer 10 is directly in contact with the P-type cladding layer 6, which can reduce the ohmic contact layer leakage in the lateral direction from the first electrode to the second electrode.

[0059] Example 3

[0060] like Figure 3 As shown, the difference from Example 2 is that a groove 11 extending downward is provided in the portion of the P-type cladding layer 6 not covered by the ohmic contact layer 7, and the groove 11 extends downward from the bottom of the dielectric layer 10. Since the groove 11 is provided, the horizontal resistance can be increased, and the horizontal leakage problem can be solved. In addition, a groove is provided between the first electrode 8 and the second electrode 9 to form a resistor, thereby reducing the crosstalk between the first electrode 8 and the second electrode 9.

[0061] like Figure 3 As shown, the cross-sectional shape of the groove 11 can be rectangular or other shapes. The groove 11 includes a first groove wall 12 and a second groove wall 13 arranged in the transverse direction, the first groove wall 12 is close to the first electrode 8, and the second groove wall 13 is close to the second electrode 9; the second groove wall 13 extends in the up-down direction; from top to bottom, there are at least two positions, wherein at the upper position, the distance between the second groove wall 13 and the first groove wall 12 is L1; at the lower position, the distance between the second groove wall 13 and the first groove wall 12 is L2, and L1 is greater than L2.

[0062] The reason for setting the first groove wall 12 as a non-vertical plane is that the larger the distance between the first groove wall 12 and the second groove wall 13, the better. However, the corresponding position of the left first electrode 8 is a large current area, which will affect the surface of the first groove wall 12, generate more heat, and reduce stability. Therefore, from top to bottom, the first groove wall 12 can be set in a way that gradually approaches the second groove wall 13 to increase the lateral width of the groove 11 as much as possible.

[0063] like Figure 4 As shown, the cross-sectional shape of the groove 11 can be a step-type. Specifically, the first groove wall 12 includes a first side wall 14 and a second side wall 15 connected in sequence from top to bottom. The groove 11 is formed by an upper and lower part with different widths. The first side wall 14 and the second side wall 15 both extend in the up and down directions. The distance between the first side wall 14 and the second groove wall 13 is greater than the distance between the second side wall 15 and the second groove wall 13.

[0064] like Figure 5As shown, the cross-sectional shape of the groove 11 may also be a trapezoid, and from top to bottom, the first groove wall 12 is inclined toward the second groove wall 13 .

[0065] The chip preparation method provided by the present invention is used to prepare the above-mentioned chip, comprising the steps of:

[0066] Step S1 . preparing a semiconductor layer structure, the semiconductor layer structure comprising an ohmic contact layer 7 and a P-type cladding layer 6 arranged in sequence from top to bottom, the doping concentration of the ohmic contact layer 7 being higher than the doping concentration of the P-type cladding layer 6 .

[0067] The N-type cladding layer 2, the N-type waveguide layer 3, the quantum well 4, the P-type waveguide layer 5, the P-type cladding layer 6 and the ohmic contact layer 7 are sequentially prepared on the substrate 1 in a layer-by-layer manner. The doping concentration of each layer needs to be adjusted during the preparation.

[0068] Step S2: Etch a portion of the ohmic contact layer 7 to expose a portion of the P-type cladding layer 6.

[0069] After the semiconductor layer structure is completed, the right side portion of the ohmic contact layer 7 is etched away using a mask, thereby exposing the P-type cladding layer 6 to facilitate the subsequent formation of the second electrode 9 .

[0070] Step S3: preparing a dielectric layer 10 on the top surface of the semiconductor layer structure.

[0071] A complete dielectric layer 10 can be first prepared on the top surface of the semiconductor layer structure, and then the left and right ends of the complete dielectric layer 10 are etched away to expose a portion of the ohmic contact layer 7 and a portion of the P-type cladding layer 6, thereby exposing the locations where the first electrode 8 and the second electrode 9 are prepared.

[0072] It should be noted that the dielectric layer 10 can be prepared on the ohmic contact layer 7 or on the P-type cladding layer 6. Furthermore, a groove 11 can be etched on the surface of the P-type cladding layer 6 to increase the lateral resistance.

[0073] Step S4. Deposit a metal layer and define a patterned metal structure, and then form a first electrode 8 on the upper surface of the ohmic contact layer 7 through an annealing process, and form a second electrode 9 on the upper surface of the exposed portion of the P-type cladding layer 6. The first electrode 8 and the second electrode 9 are respectively located on opposite sides of the dielectric layer 10.

[0074] During preparation, a metal layer is deposited on the ohmic contact layer 7 by photolithography exposure and development, and a patterned metal structure is defined by a lift-off process, and then a first electrode 8 and a second electrode 9 are formed by annealing. The contact resistance between the first electrode 8 and the ohmic contact layer 7 is Rc1. Correspondingly, the second electrode 9 is connected to the portion of the P-type cladding 6 that is not covered by the ohmic contact layer 7. After annealing, the contact resistance between the second electrode 9 and the portion of the P-type cladding 6 that is not covered by the ohmic contact layer 7 is Rc2. Since the first electrode 8 is in ohmic contact with the ohmic contact layer 7, and the second electrode 9 is in non-ohmic contact with the P-type cladding 6, Rc2 is much larger than Rc1. Rc2 is approximately 40 to 100 times of Rc1, but not more than 200 times.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip, characterized in that: include: A semiconductor layer structure, the semiconductor layer structure comprising an ohmic contact layer (7) and a P-type cladding layer (6) arranged in sequence from top to bottom, the doping concentration of the ohmic contact layer (7) being higher than the doping concentration of the P-type cladding layer (6); the area of ​​the ohmic contact layer (7) being smaller than the area of ​​the P-type cladding layer (6), so that a portion of the upper surface of the P-type cladding layer (6) is not covered by the ohmic contact layer (7); A first electrode (8), the first electrode (8) being connected to the ohmic contact layer (7), and a contact resistance between the first electrode (8) and the ohmic contact layer (7) being Rc1; a second electrode (9), the second electrode (9) being connected to a portion of the P-type cladding layer (6) not covered by the ohmic contact layer (7), the contact resistance between the second electrode (9) and the portion of the P-type cladding layer (6) not covered by the ohmic contact layer (7) being Rc2, and Rc2 being greater than Rc1; a dielectric layer (10), the dielectric layer (10) being connected to the ohmic contact layer (7); the dielectric layer (10) being located between the first electrode (8) and the second electrode (9), so that the second electrode (9) and the first electrode (8) are spaced apart; The dielectric layer plays an insulating role.

2. The chip according to claim 1, characterized in that: From top to bottom, the doping concentration of the P-type cladding layer (6) gradually decreases; The upper surface of the portion of the P-type cladding layer (6) not covered by the ohmic contact layer (7) is lower than the upper surface of the portion of the P-type cladding layer (6) covered by the ohmic contact layer (7).

3. The chip according to claim 2, characterized in that: The value range of Rc2 / Rc1 is less than or equal to 200.

4. The chip according to claim 3, characterized in that: The value range of Rc2 / Rc1 is between 40-100.

5. The chip according to claim 3, characterized in that: The doping concentration of the ohmic contact layer (7) is greater than 1×10 19 ; The doping concentration of the portion of the P-type cladding layer (6) not covered by the ohmic contact layer (7) is less than 5×10 18 .

6. The chip according to claim 1, characterized in that: The lower surface of the dielectric layer (10) contacts the upper surface of the ohmic contact layer (7).

7. The chip according to claim 1, characterized in that: The lower surface of the dielectric layer (10) is connected to a portion of the P-type cladding layer (6) that is not covered by the ohmic contact layer (7).

8. The chip according to claim 7, characterized in that: A portion of the P-type cladding layer (6) that is not covered by the ohmic contact layer (7) is provided with a downwardly extending groove (11), and the groove (11) is formed by extending downward from the bottom of the dielectric layer (10).

9. The chip according to claim 8, characterized in that: The groove (11) comprises a first groove wall (12) and a second groove wall (13) arranged in a transverse direction, the first groove wall (12) being close to the first electrode (8), and the second groove wall (13) being close to the second electrode (9); the second groove wall (13) extending in an up-down direction; From top to bottom, there are at least two positions, wherein at the upper position, the distance between the second groove wall (13) and the first groove wall (12) is L1; at the lower position, the distance between the second groove wall (13) and the first groove wall (12) is L2, and L1 is greater than L2.

10. The chip according to claim 9, characterized in that: From top to bottom, the first groove wall (12) is inclined toward the second groove wall (13); Alternatively, the first groove wall (12) comprises a first side wall (14) and a second side wall (15) which are connected in sequence from top to bottom, the first side wall (14) and the second side wall (15) both extend in an up-down direction, and the distance between the first side wall (14) and the second groove wall (13) is greater than the distance between the second side wall (15) and the second groove wall (13).

11. A method for preparing a chip, characterized in that: The method for preparing the chip according to any one of claims 1 to 10 comprises the steps of: Step S1. preparing a semiconductor layer structure, the semiconductor layer structure comprising an ohmic contact layer (7) and a P-type cladding layer (6) arranged in sequence from top to bottom, the doping concentration of the ohmic contact layer (7) being higher than the doping concentration of the P-type cladding layer (6); Step S2. etching a portion of the ohmic contact layer (7) to expose a portion of the P-type cladding layer (6); Step S3. preparing a dielectric layer (10) on the top surface of the semiconductor layer structure; etching the dielectric layer (10) to expose a portion of the ohmic contact layer (7) and a portion of the P-type cladding layer (6); Step S4. Depositing a metal layer and defining a patterned metal structure, and then forming a first electrode (8) on the upper surface of the ohmic contact layer (7) through an annealing process, and forming a second electrode (9) on the upper surface of the exposed portion of the P-type cladding layer (6), wherein the first electrode (8) and the second electrode (9) are respectively located on opposite sides of the dielectric layer (10).

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