Semiconductor device and method for manufacturing the same

Abstract

The embodiments of the present application relate to a semiconductor device and a method for preparing the same. The semiconductor device includes: a semiconductor material layer; a well region and a drift region, which are located in the semiconductor material layer and are adjacent to each other; a source region and a drain region, which are respectively located in the well region and the drift region; at least one isolation trench, which is located in the drift region and between the source region and the drain region; at least one field oxide layer, which is located in at least one isolation trench; a plurality of field plate trenches, which are located in the field oxide layer; a plurality of field plates, which are respectively located in the corresponding plurality of field plate trenches; wherein the field plates are isolated from the drift region by the field oxide layer. The embodiments of the present application can adjust the surface electric field of the drift region, improve the surface electric field distribution of the drift region in three dimensions, effectively reduce the surface peak electric field near the near-drain drift region, and increase the breakdown voltage of the drain region. In this way, a semiconductor device with ultra-high withstand voltage can be obtained without increasing the on-resistance of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration process technology that can produce Bipolar, CMOS (Complementary Metal Oxide Semiconductor) and DMOS (Double-diffused Metal Oxide Semiconductor) devices on the same chip. The BCD process combines the advantages of the above three devices and has become the mainstream process technology for integrated circuits, achieving the requirements of low power consumption, high integration, high speed and high driving capability of the entire circuit, and has better reliability.

[0003] In addition to combining the high transconductance and strong load driving capability of bipolar devices, and the high integration and low power consumption of CMOS devices, the BCD process also combines the high voltage and high current driving capability of DMOS devices. DMOS devices usually occupy about half of the area in the chip. The BCD process can integrate a variety of DMOS power devices, such as LDMOS (Lateral Double-diffused MOSFET, lateral double diffused metal oxide semiconductor) devices, VDMOS (Vertical Double-diffused MOSFET, vertical double diffused metal oxide semiconductor) devices and trench DMOS devices. Among them, LDMOS high-voltage power devices are one of the core devices in product design. Therefore, how to optimize the structure and process of LDMOS devices to obtain higher withstand voltage has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, the semiconductor device comprising:

[0006] a semiconductor material layer;

[0007] A well region and a drift region are located in the semiconductor material layer and are adjacent to each other;

[0008] A source region and a drain region, respectively located in the well region and the drift region;

[0009] at least one isolation trench located in the drift region and between the source region and the drain region;

[0010] at least one field oxide layer located in the at least one isolation trench;

[0011] A plurality of field plate trenches are located in the field oxide layer;

[0012] A plurality of field plates are respectively located in the corresponding plurality of field plate trenches; wherein the field plates are isolated from the drift region by the field oxide layer.

[0013] In combination with the first aspect of the present application, in an optional implementation manner, the number of the isolation trenches is multiple, the number of the field oxide layers is multiple, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches;

[0014] The plurality of field oxide layers extend along a first direction and are arranged at intervals along a second direction; the first direction is parallel to a direction from the source region to the drain region, and the second direction is a direction perpendicular to the first direction in a plane direction of the semiconductor material layer;

[0015] Each of the field oxide layers includes at least one field plate.

[0016] In combination with the first aspect of the present application, in an optional implementation manner, each of the field oxide layers includes a plurality of the field plates distributed at equal intervals along the first direction;

[0017] The distance between the plurality of field plates in the same field oxide layer and the first side wall of the field oxide layer is equal to the distance between the plurality of field plates and the second side wall of the field oxide layer; the first side wall and the second side wall are two side walls opposite to each other along the second direction.

[0018] In combination with the first aspect of the present application, in an optional implementation manner, the depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.

[0019] In conjunction with the first aspect of the present application, in an optional implementation manner, the semiconductor device further includes:

[0020] The gate structure is located on the semiconductor material layer, covers the top surface of the well region between the source region and the drain region, and extends to the top surface of the field oxide layer.

[0021] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0022] providing a semiconductor material layer;

[0023] A well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates are formed in the semiconductor material layer; wherein the well region and the drift region are located in the semiconductor material layer and are adjacent to each other; the source region and the drain region are located in the well region and the drift region, respectively; at least one isolation trench is located in the drift region and between the source region and the drain region, and at least one field oxide layer is filled in the at least one isolation trench; a plurality of field plate trenches are located in the field oxide layer, a plurality of field plates are filled in the corresponding plurality of field plate trenches, and the field plates are isolated from the drift region by the field oxide layer.

[0024] In combination with the first aspect of the present application, in an optional implementation manner, the number of the isolation trenches is multiple, the number of the field oxide layers is multiple, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches;

[0025] The plurality of field oxide layers extend along a first direction and are arranged at intervals along a second direction; the first direction is parallel to a direction from the source region to the drain region, and the second direction is a direction perpendicular to the first direction in a plane direction of the semiconductor material layer;

[0026] Each of the field oxide layers includes at least one field plate.

[0027] In combination with the first aspect of the present application, in an optional implementation manner, each of the field oxide layers includes a plurality of the field plates distributed at equal intervals along the first direction;

[0028] The distance between the plurality of field plates in the same field oxide layer and the first side wall of the field oxide layer is equal to the distance between the plurality of field plates and the second side wall of the field oxide layer; the first side wall and the second side wall are two side walls opposite to each other along the second direction.

[0029] In combination with the first aspect of the present application, in an optional implementation manner, the depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.

[0030] In combination with the first aspect of the present application, in an optional implementation, after forming a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates in the semiconductor material layer, the method for preparing the semiconductor device further includes:

[0031] A gate structure is formed on the semiconductor material layer, wherein the gate structure covers a top surface of the well region between the source region and the drain region and extends onto a top surface of the field oxide layer.

[0032] The semiconductor device and the preparation method thereof provided by the embodiment of the present application can introduce multiple electric field peaks in the three-dimensional directions of the drift region, i.e., the length direction, the width direction, and the thickness direction, by setting multiple field plates in the field oxide layer located in the drift region, thereby adjusting the surface electric field of the drift region, improving the surface electric field distribution of the drift region in the three-dimensional direction, effectively reducing the surface peak electric field near the near-drain drift region, and improving the drain breakdown voltage. In this way, a semiconductor device with ultra-high withstand voltage can be obtained without increasing the on-resistance of the device.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0035] Figure 1 A schematic diagram of a semiconductor device layout provided for related technology;

[0036] Figure 2 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a three-dimensional structure of a semiconductor device provided for a specific example of the present application;

[0038] Figure 4 A schematic diagram of a layout of a semiconductor device provided in an embodiment of the present application;

[0039] Figure 5 A schematic diagram of a three-dimensional structure of a semiconductor device provided for another specific example of the present application;

[0040] Figure 6 A schematic top view of a semiconductor device provided in an embodiment of the present application;

[0041] Figure 7 for Figure 6 Schematic diagram of the distribution of equipotential lines of the corresponding semiconductor device;

[0042] Figure 8 A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0043] Description of reference numerals:

[0044] 100, semiconductor material layer; 101, field plate dielectric; 110, substrate; 120, buried layer; 130, epitaxial layer; 210, well region; 220, drift region; 230, source region; 240, drain region; 250, well region contact region; 310, field oxide layer; 320, field plate; 410, gate structure; 420, gate dielectric layer; 430, gate sidewall; 500, crystallization layer; 510, well region contact plug; 520, source region contact plug; 530, drain region contact plug; 540, gate contact plug; 610, device isolation structure; 620, deep well region; T1, isolation trench; T2, field plate trench. DETAILED DESCRIPTION

[0045] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0046] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0047] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0049] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0050] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0052] Figure 1 A schematic diagram of a semiconductor device layout provided for related technology.

[0053] Please refer to Figure 1 The LDMOS device includes: a well region 210 and a drift region 220; a source region (not shown in the figure) and a drain region 240, which are respectively located in the well region 210 and the drift region 220; a field plate dielectric 101, which is located in the drift region 220; a gate structure 410, which covers a portion of the top surface of the well region 210 and extends to a portion of the top surface of the field plate dielectric 101; a crystallized layer 500, which is located on the source region and the drain region 240; a source region contact plug 520, a drain region contact plug 530 and a gate contact plug 540, which are respectively electrically connected to the source region, the drain region 240 and the gate structure 410.

[0054] In the related art, in order to improve the breakdown voltage of the LDMOS device, a field plate (electric field control plate) is usually manufactured on the field plate dielectric 101 above the drain liner PN junction termination region. For example, the portion of the gate structure 410 extending to the top surface of the field plate dielectric 101 can serve as a gate field plate. The field plate can effectively suppress the surface electric field and prevent surface breakdown, thereby increasing the drain breakdown voltage of the transistor in the device.

[0055] Here, the field plate can effectively suppress the surface electric field because a structure similar to a MOS (Metal Oxide Semiconductor) capacitor is formed at the field plate. This capacitor divides a part of the high voltage of the drain, thereby reducing the avalanche breakdown voltage of the silicon surface of the device, increasing the drain breakdown voltage, and effectively improving the voltage resistance of the device.

[0056] Specifically, a shallow trench can be filled with silicon dioxide to form an STI (Shallow Trench Isolation) structure as a field plate dielectric, and a gate field plate can be formed on the STI to increase the breakdown voltage. Compared with the method of using a LOCOS (Local Oxidation of Silicon) structure as a field plate dielectric and forming a metal field plate on the LOCOS, this method has the advantages of simple process and no need for additional masks.

[0057] However, in order to further increase the breakdown voltage and obtain an ultra-high voltage-resistant LDMOS device, the method of further increasing the length of the drift region or the depth of the shallow trench isolation structure is usually adopted to increase the on-resistance and thus increase the voltage-resistant performance of the device. However, this will sacrifice the area of ​​the active region of the device and the current conduction path, increase the current conduction path of the device, and thus greatly increase the on-resistance of the device (characteristic on-resistance).

[0058] Based on this, an embodiment of the present application provides a semiconductor device. Figure 2 This is a schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present application. Please refer to Figure 2 , semiconductor devices include:

[0059] Semiconductor material layer 100;

[0060] The well region 210 and the drift region 220 are located in the semiconductor material layer 100 and are adjacent to each other;

[0061] The source region 230 and the drain region 240 are respectively located in the well region 210 and the drift region 220;

[0062] at least one isolation trench T1 located in the drift region 220 and between the source region 230 and the drain region 240;

[0063] At least one field oxide layer 310, located in at least one isolation trench T1;

[0064] A plurality of field plate trenches T2 are located in the field oxide layer 310;

[0065] The field plates 320 are respectively located in the corresponding field plate trenches T2 ; wherein the field plates 320 are isolated from the drift region 220 by the field oxide layer 310 .

[0066] It can be understood that, by setting a plurality of field plates 320 in the field oxide layer 310 located in the drift region 220, the embodiment of the present application can introduce a plurality of electric field peaks in the three-dimensional directions of the drift region 220, i.e., the length direction, the width direction, and the thickness direction, thereby adjusting the surface electric field of the drift region 220, improving the surface electric field distribution of the drift region 220 in the three-dimensional direction, effectively reducing the surface peak electric field near the near-drain drift region 220, and improving the drain breakdown voltage. In this way, a semiconductor device with ultra-high withstand voltage can be obtained without increasing the on-resistance of the device.

[0067] In addition, the embodiment of the present application can also reduce the length of the drift region 220 while maintaining the maximum breakdown voltage of the semiconductor device provided by the related art, thereby reducing the on-resistance of the device and increasing the chip integration density.

[0068] In some embodiments, please refer to Figure 2 The semiconductor material layer 100 may include a substrate 110 and a buried layer 120 and an epitaxial layer 130 formed on the substrate 110. The buried layer 120 and the epitaxial layer 130 are sequentially stacked from bottom to top on the substrate 110. The semiconductor material layer 100 may also be referred to as a "wafer".

[0069] Specifically, the well region 210 , the drift region 220 , the source region 230 , the drain region 240 , the isolation trench T1 , the field oxide layer 310 , the field plate trench T2 , and the field plate 320 are all located in the epitaxial layer 130 .

[0070] It should be noted that the plane where the top and bottom surfaces of the semiconductor material layer 100 are located, or strictly speaking, the center plane in the thickness direction Z of the semiconductor material layer, is determined as the plane of the semiconductor material layer; the direction parallel to the plane of the semiconductor material layer is the direction along the plane of the semiconductor material layer. Two mutually perpendicular first directions X and second directions Y are defined in the plane direction of the semiconductor material layer. Here, the first direction X is parallel to the direction from the source region 230 to the drain region 240, and the second direction Y is a direction perpendicular to the first direction X in the plane direction of the semiconductor material layer.

[0071] The material of the substrate 110 may be a single-element semiconductor material (e.g., a silicon substrate, a germanium substrate, etc.), or a III-V compound semiconductor material (e.g., a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, an indium phosphide substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material or other semiconductor materials known in the art. In the embodiment of the present application, the substrate 110 may be a silicon substrate.

[0072] In some specific embodiments, please refer to Figure 2 , the buried layer 120 can be a first conductivity type buried layer, and the epitaxial layer 130 can be a second conductivity type epitaxial layer. It should be noted that the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type. Specifically, the N type impurity ions include phosphorus ions, arsenic ions, and antimony ions, and the P type impurity ions include boron ions, gallium ions, and indium ions. The buried layer 120 and the epitaxial layer 130 have opposite conductivity types, and the buried layer 120 and the epitaxial layer 130 can be adjusted according to the actual device formed.

[0073] In actual preparation, the buried layer 120 may be formed by implanting ions of the first conductivity type into the top surface layer of the substrate 110. The epitaxial layer 130 may be formed by an epitaxial growth process or other suitable methods.

[0074] In some embodiments, please refer to Figure 2, along the first direction X, the well region 210 and the drift region 220 are adjacent to each other, and there is a certain distance between the drift region 220 and the well region 210. A source region 230 is formed in the well region 210, and a drain region 240 is formed in the drift region 220. In addition, a well region contact region 250 is also formed in the well region 210, the well region contact region 250 is adjacent to the source region 230, and the well region contact region 250 is located on the side of the source region 230 away from the drift region 220.

[0075] The well region 210 may also be referred to as a “body region” or a “channel region”, and the well region contact region 250 may be referred to as a “channel lead-out implant region”.

[0076] In actual preparation, the ion implantation regions such as the well region 210, the source region 230, the drain region 240 and the drift region 220 can all be formed by ion implantation. The well region 210 can also be formed by implantation in a self-aligned manner.

[0077] In some specific embodiments, the drift region 220, the source region 230 and the drain region 240 may have the same conductivity type and the same conductivity type as the epitaxial layer 130. The well region 210 and the well region contact region 250 have the same conductivity type. The drift region 220 and the well region 210 have different conductivity types.

[0078] Specifically, the epitaxial layer 130 may be an N-type epitaxial layer, and the drift region 220 may be an N-type epitaxial layer. - Drift region, source region 230 may be N + The source region and the drain region 240 may be N + The well region 210 may be a P - The well region, the well region contact region 250 may be a P + Well region contact region: Here, the drift region 220 may be a lightly doped region, which is beneficial to improving the withstand voltage level of the device; the source region 230 and the drain region 240 may be heavily doped regions, which is beneficial to reducing the contact resistance.

[0079] It can be understood that the conductivity type of the drift region 220 is the same as the conductivity type of the epitaxial layer 130, so the drift region 220 and the buried layer 120 have opposite conductivity types. Here, by providing the buried layer 120 with the opposite conductivity type at the bottom of the drift region 220, it is beneficial to increase the impurity concentration at the bottom of the drift region 220, thereby improving the electric field distribution at the bottom of the drift region 220 and increasing the breakdown voltage of the device.

[0080] In some embodiments, please refer to Figure 2 The isolation trench T1 is located in the drift region 220, and along the thickness direction Z of the semiconductor material layer, the depth of the isolation trench T1 is less than the depth of the drift region 220. The isolation trench T1 can be formed in the drift region 220 by photolithography and etching.

[0081] In some specific embodiments, in the cross section perpendicular to the second direction Y, the cross section of the isolation trench T1 may be an inverted trapezoid, and the isolation trench T1 may be filled with a dielectric material to form a shallow trench isolation (STI) structure as the field oxide layer 310. The dielectric material includes but is not limited to silicon dioxide.

[0082] Specifically, the field oxide layer 310 completely fills the isolation trench T1, and the top surface of the field oxide layer 310 is flush with the top surface of the drift region 220, or in other words, the field oxide layer 310 extends from the top surface of the drift region 220 to the drift region 220, and along the thickness direction Z of the semiconductor material layer, the depth of the field oxide layer 310 is less than the depth of the drift region 220.

[0083] In some other embodiments, the field oxide layer 310 may be a silicon local oxidation isolation structure or a high temperature oxide layer.

[0084] It should be noted that the shallow trench isolation structure, the silicon local oxidation isolation structure and the high temperature oxide layer have different formation methods and thicknesses, which can be selected according to the device requirements. If the field oxide layer 310 is a shallow trench isolation structure, the shallow trench isolation structure can be formed by etching an isolation trench T1 in the drift region 220 and filling it; if the field oxide layer 310 is a silicon local oxidation isolation structure, the silicon local oxidation isolation structure can be formed by local oxidation; if the field oxide layer 310 is a high temperature oxide layer, the high temperature oxide layer can be formed by high temperature deposition. In this embodiment, the field oxide layer 310 is a shallow trench isolation structure, and the material of the field oxide layer 310 can be silicon oxide.

[0085] In some embodiments, please refer to Figure 2 , a plurality of field plate trenches T2 are located in the field oxide layer 310, and along the thickness direction Z of the semiconductor material layer, the depth of the field plate trenches T2 is less than the depth of the field oxide layer 310. The field plate trenches T2 can be formed in the field oxide layer 310 by processes such as photolithography and etching.

[0086] In some specific embodiments, in the cross section perpendicular to the second direction Y, the cross-sectional shape of the field plate trench T2 may be a rectangle, and the field plate trench T2 may be filled with a conductive material to form a field plate 320. The conductive material includes but is not limited to metal and polysilicon. In some other embodiments, the field plate 320 may also be a contact hole structure. In the cross section perpendicular to the second direction Y, the cross-sectional shape of the field plate 320 may be an inverted trapezoid.

[0087] Specifically, the field plate 320 completely fills the field plate trench T2, and the top surface of the field plate 320 is flush with the top surface of the field oxide layer 310, or the field plate 320 extends from the top surface of the field oxide layer 310 to the field oxide layer 310 (embedded in the field oxide layer 310). The field plate may also be called a "grooved field plate".

[0088] Along the thickness direction Z of the semiconductor material layer, the depth of the field plate 320 is less than the depth of the field oxide layer 310, and the depth of the field plate 320 is less than or equal to two-thirds of the depth of the field oxide layer 310. Therefore, in the thickness direction Z of the semiconductor material layer, the distance between the bottom of the field plate 320 and the bottom of the field oxide layer 310 is at least one-third of the depth of the field oxide layer 310, and an effective electric field control region can be formed between the field plate 320 and the field oxide layer 310, so that the electric field peak is dispersed to increase the breakdown voltage.

[0089] Exemplarily, the plurality of field plates 320 may be arranged in the field oxide layer 310 at equal intervals along the first direction X. Here, the plurality of field plates 320 may also be referred to as a “comb-shaped field plate structure”.

[0090] In some embodiments, the field plates 320 in the field oxide layer 310 may be arranged in multiple rows and columns along the first direction X and the second direction Y, and the field plates 320 are arranged at equal intervals along the first direction X and the second direction Y.

[0091] In some other embodiments, the field plates 320 may be arranged in multiple rows and columns along the first direction X and the third direction. Here, the third direction may be a direction that only intersects with the first direction X in the plane direction of the semiconductor material layer and is not perpendicular to each other.

[0092] It is understandable that, when the length of the drift region 220 is constant, the more the number of electric field peaks in the drift region 220, the smaller the electric field peak of the drain region 240. It can be seen that the number of electric field peaks in the drift region 220 is related to the breakdown voltage of the semiconductor device. Then, the more the number of field plates 320, the more the number of electric field peaks. And the smaller the width and spacing of the field plates 320, the more field plates 320 that can be set. Therefore, in some embodiments, the breakdown voltage of the semiconductor device can be adjusted by adjusting the number of field plates 320, the spacing between multiple field plates 320, and the width of the field plates 320.

[0093] Figure 3 A schematic diagram of a three-dimensional structure of a semiconductor device provided for a specific example of the present application; Figure 4 A schematic diagram of the layout of a semiconductor device provided in an embodiment of the present application.

[0094] In some embodiments, please refer to Figures 2 to 4, there are multiple isolation trenches T1, there are multiple field oxide layers 310, and the multiple field oxide layers 310 are respectively located in the corresponding multiple isolation trenches T1; the multiple field oxide layers 310 extend along the first direction X and are arranged at intervals along the second direction Y; the first direction X is parallel to the direction from the source region 230 to the drain region 240, and the second direction Y is a direction perpendicular to the first direction X in the plane direction of the semiconductor material layer 100; each field oxide layer 310 includes at least one field plate 320.

[0095] In some specific embodiments, please refer to Figure 4 and Figure 5 , setting two field plates 320 in each field oxygen layer 310 is an optional embodiment provided by the present application. In some other embodiments, when there are multiple field oxygen layers 310, multiple field plates 320 may be only located in a part of the field oxygen layers 310, and no field plates 320 may be set in another part of the field oxygen layers 310. The layout of multiple field plates 320 in multiple field oxygen layers 310 can be selected according to actual needs, and is not specifically limited here.

[0096] Specifically, the drift region 220 between two adjacent field oxide layers 310 is an active region (active region) through which current passes when it flows from the source region 230 to the drain region 240. Here, the additional active region is beneficial to reducing the on-resistance of the semiconductor device.

[0097] It should be noted that for LDMOS devices, the trade-off between breakdown voltage and on-resistance is the most important. Simply sacrificing on-resistance to obtain higher withstand voltage will limit the development of high density, high power and high withstand voltage of LDMOS devices to a certain extent, and limit the application and performance of LDMOS devices. In the embodiment of the present application, multiple field oxide layers 310 are arranged at intervals along the second direction Y, and at least one field plate 320 is provided in each of the multiple field oxide layers 310. While reducing the on-resistance of the device, it is possible to avoid the problem that the additional active area has no field plate to assist in improving the withstand voltage performance of the device, resulting in a reduced breakdown voltage of the device.

[0098] Specifically, please refer to Figure 5 , Figure 5 A schematic diagram of a three-dimensional structure of a semiconductor device provided for another specific example of the present application. When a plurality of field oxide layers 310 are arranged at intervals along the second direction Y, current can flow from the source region 230 to the drain region 240 (such as Figure 5The arrows in the figure indicate the current flow direction). It can be seen that by providing the field oxide layers 310 separated along the second direction Y, the drift region 220 between the adjacent field oxide layers 310 can be used as an active region. Such a structure greatly increases the effective width of the LDMOS device, can significantly increase the area of ​​the active region and reduce the conduction path of the current during forward conduction, and greatly reduces the on-resistance.

[0099] Here, the "effective width" of a device is the width of the conductive area of ​​the device. A larger effective width allows the device to carry a larger amount of current, while a smaller effective width restricts the device from carrying a smaller amount of current. A device with a larger effective width will also have a smaller on-resistance than a device with a smaller effective width.

[0100] For further information, please refer to Figure 6 and Figure 7 , Figure 6 A schematic top view of a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 7 for Figure 6 Schematic diagram of the distribution of equipotential lines of the corresponding semiconductor device. The newly added active area is set between adjacent field oxide layers 310. When voltage is applied to the device, the N region of the device is connected to a positive voltage (+V), the P region is grounded, and the PN junction depletion boundary of the active area (drift region 220) (the area between the two curves drawn in dotted form in the figure) has dense equipotential lines. At this time, the surface electric field of the active area is higher than the surface electric field of the field oxide layer 310. Due to the high surface electric field of the active area, the breakdown voltage there is small, which in turn reduces the withstand voltage performance of the device.

[0101] The field plate 320 and the field oxide layer 310 on the sidewall of the active region form a metal-oxide layer-semiconductor capacitor structure. Such a structure can provide an electric field on the surface and inside of the semiconductor material layer 100 in a direction perpendicular to the semiconductor material layer 100, which is equivalent to Figure 1 The portion of the middle gate structure 410 extending to the top surface of the field plate medium 101 can effectively suppress the surface electric field and adjust the internal electric field. Furthermore, by appropriately adjusting the width of the active area and the width and depth of the field plate 320, the electric field can be distributed more evenly, which can effectively improve the breakdown voltage of the device.

[0102] In addition, when the device is in a reverse bias state, the field plate 320 and the field oxide layer 310 can form a MOS capacitor structure on the sidewall, effectively assisting depletion and pinch-off, and making the electric field distribution more uniform, which can also improve the voltage resistance performance of the device to a certain extent.

[0103] In some embodiments, please refer to Figure 3Each field oxygen layer 310 includes a plurality of field plates 320 distributed at equal intervals along a first direction X; a distance between a plurality of field plates 320 in the same field oxygen layer 310 and a first side wall of the field oxygen layer 310 is equal to a distance between the plurality of field plates 320 and a second side wall of the field oxygen layer 310; and the first side wall and the second side wall are two side walls opposite to each other along a second direction Y.

[0104] Here, along the second direction Y, the line width of the plurality of field plates 320 in the same field oxide layer 310 is greater than or equal to half of the line width of the field oxide layer 310 .

[0105] It can be understood that the multiple field plates 320 are arranged at equal intervals along the first direction X, which is beneficial to the uniform distribution of the electric field and further improves the breakdown voltage of the device.

[0106] In some specific embodiments, the arrangement of the multiple field plates 320 in each field oxide layer 310 is distributed at equal intervals along the first direction X. Of course, in some other embodiments, the arrangement of the multiple field plates 320 in the same field oxide layer 310 can also be distributed in multiple rows and columns along the first direction X and the second direction Y, and the multiple field plates 320 are arranged at equal intervals along the first direction X and the second direction Y. For example, the number of field plates 320 in the same field oxide layer 310 is 4, and they are arranged in 2 rows and 2 columns.

[0107] Specifically, the number of the field plates 320 in each field oxygen layer 310 may be 2, 3, 5, 6, etc., and may be set according to actual needs, and is not specifically limited here.

[0108] In some embodiments, please refer to Figure 2 , the semiconductor device also includes:

[0109] The gate structure 410 is located on the semiconductor material layer 100 , covers the top surface of the well region 210 between the source region 230 and the drain region 240 , and extends to the top surface of the field oxide layer 310 .

[0110] It can be understood that the portion of the gate structure 410 extending along the first direction X to the top surface of the field oxide layer 310 can serve as a gate field plate, which is beneficial to further suppress the surface electric field of the device and prevent surface breakdown, thereby increasing the drain breakdown voltage of the transistor in the device and further improving the breakdown voltage of the semiconductor device.

[0111] In some specific embodiments, a gate dielectric layer 420 is disposed between the gate structure 410 and the well region 210. Gate spacers 430 are formed on two opposite sidewalls of the gate structure 410 along the first direction X.

[0112] Specifically, the material of the gate structure 410 includes but is not limited to polysilicon or metal materials, the material of the gate dielectric layer 420 includes but is not limited to oxide, and the material of the gate sidewall 430 includes but is not limited to silicon oxide and silicon oxynitride.

[0113] In some embodiments, please refer to Figure 2 The semiconductor device further includes a crystallization layer 500, which covers the top surface of the source region 230, the drain region 240, the well region contact region 250, and the gate structure 410. The material of the crystallization layer 500 includes but is not limited to metal silicide. The crystallization layer 500 can reduce the contact resistance between the source region 230, the drain region 240, the well region contact region 250, the gate structure 410 and other conductive structures.

[0114] In some specific embodiments, please refer to Figure 2 The semiconductor device further includes: a well region contact plug 510, a source region contact plug 520, a drain region contact plug 530 and a gate contact plug 540 (such as Figure 4 The above-mentioned contact plugs are all located on the crystallized layer 500 .

[0115] Specifically, the well region contact plug 510, the source region contact plug 520, the drain region contact plug 530 and the gate contact plug 540 are electrically connected to the well region contact region 250, the source region 230, the drain region 240 and the gate structure 410, respectively. The materials of the well region contact plug 510, the source region contact plug 520, the drain region contact plug 530 and the gate contact plug 540 may be the same or different. Specifically, the material of the above-mentioned contact plugs may be metal, such as tungsten, titanium, aluminum or copper, etc.

[0116] It should be noted that the source region contact plug 520 may also be referred to as a “source contact hole”, and the drain region contact plug 530 may also be referred to as a “drain contact hole”.

[0117] In some embodiments, please refer to Figure 2 , the semiconductor device further includes: a device isolation structure 610 and a deep well region 620. The device isolation structure 610 and the deep well region 620 are located in the epitaxial layer 130, and are located on the side of the drift region 220 away from the well region 210. The device isolation structure 610 extends from the top surface of the epitaxial layer 130 to the epitaxial layer 130, the deep well region 620 is located below the device isolation structure 610, and the top surface and bottom surface of the deep well region 620 are directly in contact with the bottom surface of the device isolation structure 610 and the bottom surface of the epitaxial layer 130, respectively.

[0118] Here, the device isolation structure 610 may be a shallow trench isolation structure, and the deep well region 620 may be a deep P-well region. The deep well region 620 and the device isolation structure 610 are used to isolate a plurality of LDMOS devices.

[0119] Based on this, an embodiment of the present application further provides a method for preparing a semiconductor device. Figure 8 This is a flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application. Please refer to Figure 8 , a method for preparing a semiconductor device comprises:

[0120] Step S101: providing a semiconductor material layer;

[0121] Step S102: forming a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates in the semiconductor material layer; wherein the well region and the drift region are located in the semiconductor material layer and are adjacent to each other; the source region and the drain region are located in the well region and the drift region, respectively; at least one isolation trench is located in the drift region and between the source region and the drain region, at least one field oxide layer is filled in at least one isolation trench; a plurality of field plate trenches are located in the field oxide layer, a plurality of field plates are filled in the corresponding plurality of field plate trenches, and the field plates are isolated from the drift region by the field oxide layer.

[0122] In some embodiments, there are multiple isolation trenches, and there are multiple field oxide layers, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches; the multiple field oxide layers extend along a first direction and are arranged at intervals along a second direction; the first direction is parallel to the direction from the source region to the drain region, and the second direction is a direction perpendicular to the first direction in the plane direction of the semiconductor material layer; each field oxide layer includes at least one field plate.

[0123] In some embodiments, each field oxygen layer includes multiple field plates distributed at equal intervals along a first direction X; the spacing between the multiple field plates in the same field oxygen layer and the first side wall of the field oxygen layer is equal to the spacing between the multiple field plates and the second side wall of the field oxygen layer; the first side wall and the second side wall are two side walls opposite to each other along a second direction Y.

[0124] In some embodiments, the depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.

[0125] In some embodiments, after forming a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, multiple field plate trenches and multiple field plates in a semiconductor material layer, the method for preparing a semiconductor device also includes: forming a gate structure on the semiconductor material layer, the gate structure covers the top surface of the well region between the source region and the drain region, and extends to the top surface of the field oxide layer.

[0126] In summary, the embodiment of the present application can introduce multiple electric field peaks in the three-dimensional directions of the drift region, i.e., the length direction, the width direction, and the thickness direction, by setting multiple field plates in the field oxide layer located in the drift region, thereby achieving the improvement of the surface electric field distribution in the three-dimensional direction of the drift region by using the field plates without significantly increasing the process, reducing the peak electric field in the drift region near the drain end (drain region), thereby increasing the drain breakdown voltage of the LDMOS device, and effectively improving the withstand voltage capability of the LDMOS device; at the same time, the on-resistance of the drift region can also be greatly reduced, and the integration density of the chip can be significantly improved. The semiconductor device provided by the embodiment of the present application has the characteristics of high density, high power, and high withstand voltage.

[0127] It should be noted that the semiconductor device embodiment provided in the present application and the semiconductor device preparation method embodiment belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the semiconductor device provided in the embodiment of the present application, the combination of its various technical features can already solve the technical problem to be solved by the present application; therefore, the semiconductor device provided in the embodiment of the present application may not be limited by the semiconductor device preparation method provided in the embodiment of the present application, and any semiconductor device prepared by the preparation method that can form the semiconductor device structure provided in the embodiment of the present application is within the scope of protection of the present application.

[0128] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a semiconductor material layer; A well region and a drift region are located in the semiconductor material layer and are adjacent to each other; A source region and a drain region, respectively located in the well region and the drift region; at least one isolation trench located in the drift region and between the source region and the drain region; at least one field oxide layer located in the at least one isolation trench; A plurality of field plate trenches are located in the field oxide layer; A plurality of field plates are respectively located in the corresponding plurality of field plate trenches; wherein the field plates are isolated from the drift region by the field oxide layer; There are multiple isolation trenches, there are multiple field oxide layers, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches; The plurality of field oxide layers extend along a first direction and are arranged at intervals along a second direction; the first direction is parallel to a direction from the source region to the drain region, and the second direction is a direction perpendicular to the first direction in a plane direction of the semiconductor material layer; Each of the field oxide layers includes at least one field plate; The drift region between adjacent field oxide layers serves as an active region.

2. The semiconductor device according to claim 1, wherein: Each of the field oxide layers includes a plurality of the field plates distributed at equal intervals along the first direction; The distance between the plurality of field plates in the same field oxide layer and the first side wall of the field oxide layer is equal to the distance between the plurality of field plates and the second side wall of the field oxide layer; the first side wall and the second side wall are two side walls opposite to each other along the second direction.

3. The semiconductor device according to claim 1 or 2, characterized in that: The depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.

4. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor device further comprises: The gate structure is located on the semiconductor material layer, covers the top surface of the well region between the source region and the drain region, and extends to the top surface of the field oxide layer.

5. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: providing a semiconductor material layer; A well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates are formed in the semiconductor material layer; wherein the well region and the drift region are located in the semiconductor material layer and are adjacent to each other; the source region and the drain region are located in the well region and the drift region, respectively; at least one isolation trench is located in the drift region and between the source region and the drain region, and at least one field oxide layer is filled in the at least one isolation trench; a plurality of field plate trenches are located in the field oxide layer, a plurality of field plates are filled in the corresponding plurality of field plate trenches, and the field plates are isolated from the drift region by the field oxide layer; There are multiple isolation trenches, there are multiple field oxide layers, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches; The plurality of field oxide layers extend along a first direction and are arranged at intervals along a second direction; the first direction is parallel to a direction from the source region to the drain region, and the second direction is a direction perpendicular to the first direction in a plane direction of the semiconductor material layer; Each of the field oxide layers includes at least one field plate; The drift region between adjacent field oxide layers serves as an active region.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: Each of the field oxide layers includes a plurality of the field plates distributed at equal intervals along the first direction; The distance between the plurality of field plates in the same field oxide layer and the first side wall of the field oxide layer is equal to the distance between the plurality of field plates and the second side wall of the field oxide layer; the first side wall and the second side wall are two side walls opposite to each other along the second direction.

7. The method for preparing a semiconductor device according to claim 5 or 6, characterized in that: The depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.

8. The method for preparing a semiconductor device according to claim 5 or 6, characterized in that: After forming a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates in the semiconductor material layer, the method for preparing the semiconductor device further comprises: A gate structure is formed on the semiconductor material layer, wherein the gate structure covers a top surface of the well region between the source region and the drain region and extends onto a top surface of the field oxide layer.

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