Semiconductor device, bipolar transistor and method for manufacturing the same

Abstract

The present invention provides a semiconductor device, a bipolar transistor and a method for manufacturing the same, wherein the bipolar transistor comprises: a substrate on which an epitaxial layer is provided; an emitter region provided in the epitaxial layer; a base region covering the emitter region along the periphery of the emitter region; a collector region covering the base region along the periphery of the base region; and a plurality of epitaxial regions provided in the collector region and in contact with the base region, wherein the doping concentration of the epitaxial region is less than the doping concentration of the collector region and the conductivity type thereof is the same as the conductivity type of the epitaxial layer. The present invention can conveniently adjust the amplification factor of the bipolar transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a bipolar transistor and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuits, in order to save area, multiple devices are often prepared on the same substrate at the same time. For example, in the BCD (Bipolar-CMOS-DMOS) process, high-voltage power devices such as bipolar transistors (Bipolar), complementary metal oxide semiconductors (CMOS) and diffused metal oxide semiconductors (DMOS) can be prepared on the same substrate. The BCD process has been widely used in mobile devices, home appliances, displays, automobiles, data centers and other fields.

[0003] When preparing semiconductor devices using the BCD process (BCD semiconductor devices), the doping concentration and doping depth of each layer of the above-mentioned transistors are different. If the transistors can share part of the doping process (ion implantation process) as much as possible, the process flow of the semiconductor device can be simplified and the cost can be reduced. Taking the bipolar transistor in the semiconductor device as an example, it is usually necessary to adjust the ion implantation process of the collector region and the base region to adjust the amplification factor (beta) of the bipolar transistor, making it difficult to easily integrate it into the ion implantation process of CMOS devices and DMOS devices. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device, a bipolar transistor and a method for manufacturing the same, which can conveniently adjust the amplification factor of the bipolar transistor.

[0005] In order to solve the above technical problems, the present invention provides a bipolar transistor, comprising:

[0006] a substrate having a first epitaxial layer disposed thereon;

[0007] an emitter region disposed in the first epitaxial layer;

[0008] A base region covering the emitting region along the periphery of the emitting region;

[0009] A collector region covering the base region along the periphery of the base region;

[0010] A plurality of epitaxial regions are arranged in the collector region and in contact with the base region, wherein the doping concentration of the epitaxial regions is less than the doping concentration of the collector region and the conductivity type thereof is the same as the conductivity type of the first epitaxial layer.

[0011] Optionally, a drift region and a buried layer are provided in the substrate under the first epitaxial layer in sequence from top to bottom, and the drift region is connected to the collector region and the buried layer.

[0012] Optionally, the epitaxial region is formed by the first epitaxial layer, one end of the epitaxial region close to the base region is in contact with the base region, and the other end of the epitaxial region is arranged at the bottom of the collector region and connected to the drift region.

[0013] Optionally, a plurality of trenches are provided in the collector region, the epitaxial region is formed of an epitaxial material filling the trenches, one end of the trench close to the base region is in contact with the base region, and the other end of the trench is provided in the collector region.

[0014] Optionally, one end of the epitaxial region away from the base region extends into the drift region.

[0015] Optionally, a projection of the epitaxial region on the substrate is located within a projection of the base region on the substrate.

[0016] According to another aspect of the present invention, a method for preparing a bipolar transistor is also provided, comprising:

[0017] Providing a substrate on which a first epitaxial layer is formed and a first region, a second region and a third region are sequentially embedded from large to small;

[0018] forming a first patterned mask layer on the first epitaxial layer, wherein the opening of the first patterned mask layer exposes the first region, and the first patterned mask layer also covers a portion of the second region;

[0019] Performing a first ion implantation to form a collector region and an epitaxial region in the first epitaxial layer, wherein the epitaxial region is the first epitaxial layer in the collector region that is not implanted with the first ions;

[0020] The first patterned mask layer is removed, and a base region is formed in the second region, and an emitter region is formed in the third region, wherein the collector region covers the base region along the periphery of the base region, and the base region covers the emitter region along the periphery of the emitter region.

[0021] Optionally, the substrate further includes a buried layer and a drift region, and the step of forming the first epitaxial layer includes:

[0022] Doping on the surface of the substrate to form the buried layer;

[0023] epitaxially forming a second epitaxial layer on the substrate and the buried layer;

[0024] Doping the surface of the second epitaxial layer to form the drift region;

[0025] The first epitaxial layer is epitaxially formed on the second epitaxial layer and the drift region.

[0026] Optionally, the step of forming the base region includes:

[0027] removing the first patterned mask layer;

[0028] forming a second patterned mask layer on the first epitaxial layer and the collector region, wherein the opening of the second patterned mask layer exposes the second region;

[0029] Performing a second ion implantation to form the base region in the collector region and the epitaxial region of the second region, wherein the implantation depth of the second ion implantation is less than the implantation depth of the first ion implantation;

[0030] The second patterned mask layer is removed.

[0031] According to another aspect of the present invention, a method for preparing a bipolar transistor is also provided, comprising:

[0032] Providing a substrate on which a first epitaxial layer is formed and a first region, a second region and a third region are sequentially embedded from large to small;

[0033] forming a first patterned mask layer on the first epitaxial layer, the opening of which exposes the first region, performing a first ion implantation, and forming a collector region in the first region of the first epitaxial layer;

[0034] removing the first patterned mask layer to form a second patterned mask layer, the opening of which exposes a portion of the second region, and performing an etching process to form a plurality of grooves in the collector region of the second region;

[0035] Filling the trench with an epitaxial material to form an epitaxial region, wherein the doping concentration of the epitaxial region is lower than the doping concentration of the collector region and the conductivity type of the epitaxial region is the same as the conductivity type of the first epitaxial layer;

[0036] The second patterned mask layer is removed, a base region is formed in the second region, and an emitter region is formed in the third region, the collector region covers the base region along the periphery of the base region, and the base region covers the emitter region along the periphery of the emitter region.

[0037] According to another aspect of the present invention, there is also provided a semiconductor device, comprising a bipolar transistor,

[0038] The bipolar transistor comprises:

[0039] a substrate having a first epitaxial layer disposed thereon;

[0040] an emitter region disposed in the first epitaxial layer;

[0041] A base region covering the emitting region along the periphery of the emitting region;

[0042] A collector region covering the base region along the periphery of the base region;

[0043] A plurality of epitaxial regions are arranged in the collector region and in contact with the base region, wherein the doping concentration of the epitaxial regions is less than the doping concentration of the collector region and the conductivity type thereof is the same as the conductivity type of the first epitaxial layer.

[0044] To sum up, the present invention sets up several epitaxial regions in the collector region of the bipolar transistor, the doping concentration of the epitaxial region is lower than the doping concentration of the collector region and its conductivity type is the same as the conductivity type of the first epitaxial layer. After ion implantation and heat treatment of the base region, the width of the base region can be increased and the time for carriers to transit the base region can be prolonged without completely changing the ion implantation process for forming the collector region and the base region, thereby reducing the amplification factor of the bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0046] Figure 1 A cross-sectional schematic diagram of a bipolar transistor provided in Example 1;

[0047] Figure 2 A schematic top view of a bipolar transistor provided in Example 1;

[0048] Figure 3a A schematic top view of an epitaxial region provided in Example 1;

[0049] Figure 3b A schematic top view of an epitaxial region provided in Example 1;

[0050] Figure 3c A schematic top view of an epitaxial region provided in Example 1;

[0051] Figure 4 A flow chart of a method for preparing a bipolar transistor provided in Example 1;

[0052] Figure 5a A schematic diagram of forming a buried layer in a substrate provided in Example 1;

[0053] Figure 5b A schematic diagram of forming a second epitaxial layer provided in Example 1;

[0054] Figure 5c A schematic diagram of forming a drift region in the second epitaxial layer provided in Embodiment 1;

[0055] Figure 5d A schematic diagram of forming a first epitaxial layer provided in Example 1;

[0056] Figure 5e A schematic diagram of forming a shallow trench isolation structure to define first to third regions provided in Embodiment 1;

[0057] Figure 5f A schematic diagram of forming a first patterned mask layer provided in Embodiment 1;

[0058] Figure 5g A schematic diagram of forming a collector region and an epitaxial region in a first epitaxial layer provided in Embodiment 1;

[0059] Figure 5h A schematic diagram of forming a base region in the second region provided in Example 1;

[0060] Figure 5i A schematic diagram of forming an emission region in the third region provided in Embodiment 1;

[0061] Figure 5j A schematic diagram of forming a base electrode and an epitaxial layer lead-out terminal provided in Embodiment 1;

[0062] Figure 6 A schematic cross-sectional view of a bipolar transistor provided in Embodiment 2;

[0063] Figure 7 A flow chart of a method for preparing a bipolar transistor provided in Example 2;

[0064] Figure 8a A schematic diagram of forming a buried layer in a substrate provided in Example 2;

[0065] Figure 8b A schematic diagram of forming a second epitaxial layer provided in Example 2;

[0066] Figure 8c A schematic diagram of forming a drift region in the second epitaxial layer provided in Embodiment 2;

[0067] Figure 8d A schematic diagram of forming a first epitaxial layer provided in Example 2;

[0068] Figure 8e A schematic diagram of forming a shallow trench isolation structure to define first to third regions provided in the second embodiment;

[0069] Figure 8f A schematic diagram of forming a collector region in the first region provided in Embodiment 2;

[0070] Figure 8g A schematic diagram of forming a groove in the second region provided in Embodiment 2;

[0071] Figure 8h A schematic diagram of forming an epitaxial region in a trench provided in Embodiment 2;

[0072] Figure 8i A schematic diagram of forming a base region in the second region provided in Embodiment 2;

[0073] Figure 8j A schematic diagram of forming an emission region in the third region provided in Embodiment 2.

[0074] In the accompanying drawings: 10-substrate; 11-second epitaxial layer; 12-first epitaxial layer; 13-buried layer; 14-drift region; 21-collector region; 22a-groove; 22-epitaxial region; 23-base region; 24-emitter region; 25-base; 26-collector; 27a-third annular isolation structure; 27b-second annular isolation structure; 27c-first annular isolation structure; 28-substrate lead-out terminal; 29a-first buffer layer; 29b-second buffer layer; 31-first patterned mask layer; 32-second patterned mask layer; 33-third patterned mask layer; 34-fourth patterned mask layer. DETAILED DESCRIPTION

[0075] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0076] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in other ways (rotated 90 degrees or other orientations) and the spatial descriptors used here are interpreted accordingly. The purpose of the terms used here is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used here, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "including" is used to determine the existence of features, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, steps, operations, elements, parts and / or groups. When used here, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] Embodiment 1

[0078] Embodiment 1 provides a bipolar transistor.

[0079] Figure 1 A cross-sectional schematic diagram of a bipolar transistor provided in Example 1; Figure 2 This is a schematic top view of a bipolar transistor provided in the first embodiment.

[0080] like Figure 1 and Figure 2As shown, the bipolar transistor provided in this embodiment includes a substrate 10, a first epitaxial layer 12, an emitter region 24, a base region 23, a collector region 21 and an epitaxial region 22. The first epitaxial layer 12 is disposed on the substrate 10. The emitter region 24 is disposed in the first epitaxial layer 12; the base region 23 covers the emitter region 24 along the periphery of the emitter region 24; the collector region 21 covers the base region 23 along the periphery of the base region 23; a plurality of epitaxial regions 22 are disposed in the collector region 21 and in contact with the base region 23, and the epitaxial regions 22 are formed by the first epitaxial layer 12.

[0081] The substrate 10 and the first epitaxial layer 12 on the substrate 10 of the present embodiment may be a semiconductor substrate of any material. The material of the substrate 10 may be, for example, silicon, silicon germanium, silicon carbide or silicon on insulator, and the material of the epitaxial layer may be, for example, silicon. In one example, in addition to the bipolar transistor provided on the first epitaxial layer 12 of the present embodiment, low-voltage devices (CMOS devices) and high-voltage devices (power devices) are also integrated at the same time, that is, the bipolar transistor of the present embodiment is part of the BCD (Bipolar_CMOS_DMOS) platform, therefore, the material of the substrate 10 and the first epitaxial layer 12 may both be silicon.

[0082] Please continue to refer to Figure 1 In this embodiment, two epitaxial layers, namely, the second epitaxial layer 11 and the first epitaxial layer 12, may be sequentially stacked on the substrate 10. A buried layer 13 is provided on the surface of the substrate 10, and the second epitaxial layer 11 is provided on the buried layer 13 and the surface of the substrate 10. A drift region 14 may be provided in the second epitaxial layer 11, and the bottom of the drift region 14 is in contact with the top of the buried layer 13. The conductivity type of the drift region 14 is the same as that of the buried layer 13, and the normal sizes of the two are basically the same. The first epitaxial layer 12 is provided on the surface of the drift region 14 and the second epitaxial layer 11, and the first epitaxial layer 12 is provided with structures such as the collector region 21, the base region 23 and the emitter region 24 of the bipolar transistor.

[0083] Please continue to refer to Figure 1 and Figure 2, the surface of the first epitaxial layer 12 may be provided with first to third annular isolation structures 27c~27a which are arranged in sequence from large to small, respectively used to define the collector region 21, the base region 23 and the emitter region 24 from large to small. Among them, the first to third annular isolation structures 27a may all be shallow trench isolation structures. Specifically, the emitter region 24 is defined by the smallest third annular isolation structure 27a, and its junction depth may be less than the depth of the third annular isolation structure 27a, which has the first conductivity type and is heavily doped. The base region 23 is defined by the second annular isolation structure 27b, and the emitter region 24 is covered along the periphery (edge) of the emitter region 24 (the emitter region 24 is arranged in the base region 23), that is, the junction depth of the base region 23 is greater than the junction depth of the emitter region 24 and the depth of the trench isolation structure, and the base region 23 has the second conductivity type (opposite to the first conductivity type) and the doping concentration is less than the doping concentration of the emitter region 24. The collector region 21 is defined by the first annular isolation structure 27c, and covers the base region 23 along the periphery (edge) of the base region 23 (the base region 23 is arranged in the collector region 21), that is, the junction depth of the collector region 21 is greater than the junction depth of the emitter region 23 and is in contact with the drift region 14 in the depth direction. The collector region 21 has a first conductivity type, and its doping concentration is greater than the doping concentration of the first epitaxial layer and less than the doping concentration of the base region 23. Of course, electrodes for electrically leading out of each region are also provided on the surface of the above-mentioned regions (collector region 21, base region 23 and emitter region 24), that is, a collector 26 for electrically leading out the collector region 21, a collector for electrically leading out the base region 23, and an emitter for electrically leading out the emitter region 24. Among them, the emitter region 24 and the emitter can also be integrated, and a first buffer region 29a can also be provided between the collector region 21 and the collector 26, and the conductivity type of the first buffer region 29a is the same as the above two and the ion concentration is between the two.

[0084] In particular, please continue to refer to Figure 1 In this embodiment, a plurality of epitaxial regions 22 are further provided in the collector region 21, and the amplification factor (or gain, beta) of the bipolar transistor is adjusted by adjusting the planar shape and number of the epitaxial regions 22. The epitaxial region 22 may be formed by the region of the first epitaxial layer 12 (collector region 21) that is not ion-implanted, and may have the conductivity type and doping concentration of the first epitaxial layer 12 (i.e., the conductivity type and doping concentration of the first epitaxial layer 12 are the same), and its doping concentration is lower than the doping concentration of the collector region 21. Taking the formation of an NPN bipolar transistor in this embodiment as an example, the first epitaxial layer 12 is in-situ doped with a relatively low concentration (for example, much lower than the collector region 21) of P-type, therefore, the epitaxial region 22 is also P-type and its doping concentration is lower than the doping concentration of the collector region 21.

[0085] The epitaxial region 22 is at least partially disposed below the base region 23 for partially connecting the base region 23 and the drift region 14, that is, the epitaxial region 22 disposed below the base region 23 contacts the base region 23 at one end in the depth direction (located at the top of the collector region 21), and contacts the drift region 14 at the other end (located at the bottom of the collector region 21). Since the ion concentration of the epitaxial region 22 is lower than that of the collector region 21 and the base region 23, the overall concentration of the collector region 21 below the base region 23 can be reduced, and after heat treatment, the width of the base region 23 can be increased without changing the ion implantation process for forming the collector region 21 and the base region 23, and the time for carriers to transit through the base region 23 can be prolonged, thereby reducing the gain factor of the bipolar transistor.

[0086] Specifically, the shape and number of the epitaxial regions 22 can be reasonably set based on simulation and combined with actual tests. The epitaxial region 22 can be in any suitable shape (viewed from above) such as a strip, ring, circle or rectangle, and the shapes of each epitaxial region 22 can also be different. In one example, the collector region 21 may include four evenly arranged epitaxial regions 22, each of which is a strip of the same width. When different widths and different spacings are set, the bipolar transistor has a simulation amplification factor as shown in Table 1 below.

[0087]

[0088] Table 1 shows the simulated amplification factor of bipolar transistors with different widths and spacings

[0089] As shown in Table 1 above, when the epitaxial region 22 is not set in the collector region 21, the amplification factor of the bipolar transistor is as high as 500, and by setting four epitaxial regions 22 in the collector region 21 under the base region 23, the amplification factor of the bipolar transistor can be reduced to the range of 84 to 134, and the amplification factor can be further fine-tuned by setting the width and spacing of the epitaxial regions 22.

[0090] In some other examples of this embodiment, the epitaxial region 22 in the collector region 21 may also be in a ring shape, and the plurality of ring-shaped epitaxial regions 22 may also be in a ring shape. Figure 3a Alternatively, the plurality of annular epitaxial regions 22 may be arranged in a nested manner as shown. Figure 3b In other examples, the epitaxial region 22 in the collector region 21 may also be circular or rectangular, and Figure 3c The array arrangement shown.

[0091] It is understandable that the epitaxial region 22 is usually located below the base region 23, that is, the projection of the epitaxial region 22 on the substrate 10 is located within the projection of the base region 23 on the substrate 10, so as to prevent the lateral diffusion of the base region 23 from affecting the area of ​​the collector region 21. In some examples, even if the epitaxial region 22 (horizontally) slightly exceeds the base region 23, the epitaxial region 22 does not exceed the range of the second annular isolation structure 27b.

[0092] This embodiment also provides a method for preparing a bipolar transistor.

[0093] Figure 4 This is a flow chart of a method for preparing a bipolar transistor provided in this embodiment.

[0094] like Figure 4 As shown, the method for preparing a bipolar transistor provided in this embodiment includes:

[0095] S01: providing a substrate on which a first epitaxial layer is formed and a first region, a second region and a third region are sequentially embedded from large to small;

[0096] S02: forming a first patterned mask layer on the first epitaxial layer, wherein an opening of the first patterned mask layer exposes the first region, and the first patterned mask layer also covers a portion of the second region;

[0097] S03: performing a first ion implantation to form a collector region and an epitaxial region in the first epitaxial layer, wherein the epitaxial region is the first epitaxial layer in the collector region that is not implanted with the first ions;

[0098] S04: removing the first patterned mask layer, and forming a base region in the second region and an emitter region in the third region, wherein the collector region covers the base region along the periphery of the base region, and the base region covers the emitter region along the periphery of the emitter region.

[0099] Figure 5a~Figure 5j The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the bipolar transistor provided in the first embodiment is shown below in combination with Figure 5a~Figure 5j The method for preparing the bipolar transistor provided in the first embodiment is described in detail.

[0100] First, step S01 is performed to provide a substrate 10 on which a first epitaxial layer 12 is formed and first to third regions are sequentially embedded from large to small.

[0101] For details, please refer to Figure 5a , a buried layer 13 is formed by doping (eg, ion implantation) on the surface of the substrate 10 .

[0102] Please refer to Figure 5b , a second epitaxial layer 11 is epitaxially formed on the substrate 10 and the buried layer 13.

[0103] Please refer to Figure 5c The drift region 14 is doped on the surface of the second epitaxial layer 11 . When the drift region 14 is formed by ion implantation, the implantation depth is greater than or equal to the thickness of the second epitaxial layer 11 , so that the drift region 14 is connected to the buried layer 13 .

[0104] Please refer to Figure 5d A first epitaxial layer 12 is epitaxially formed on the second epitaxial layer 11 and the drift region 14 , and when the first epitaxial layer 12 is epitaxially formed, it is doped in situ.

[0105] Please refer to Figure 5e , first to third annular isolation structures 27c~27a from large to small are formed on the surface of the first epitaxial layer 12, which are used to define the first to third regions corresponding to the collector region 21, the base region 23 and the emitter region 24, that is, the first annular isolation structure 27c (first region) defines the collector region 21, the second annular isolation structure 27b (second region) defines the base region 23, and the third annular isolation structure 27a (third region) defines the emitter region 24. The first to third annular isolation structures 27c~27a can all be shallow trench isolation structures.

[0106] Next, please refer to Figure 5f , step S02 is performed to form a first patterned mask layer 31 on the first epitaxial layer 12, wherein the opening of the first patterned mask layer 31 exposes the first region, and the first patterned mask layer 31 also covers a portion of the second region. The portion of the second region surface covered by the first patterned mask layer 31 is the region corresponding to the epitaxial region 22.

[0107] Next, please refer to Figure 5g , step S03 is performed to perform the first ion implantation to form a collector region 21 and an epitaxial region 22 in the first epitaxial layer 12, wherein the epitaxial region 22 is the portion of the collector region 21 that is not implanted with the first ions (the first epitaxial layer 12). The implantation depth of the first ion implantation may be greater than or equal to the thickness of the first epitaxial layer 12, so that the collector region 21 is connected to the drift region 14. It should be noted that the epitaxial region 22 is projected onto the second region, and at this time, the epitaxial region 22 penetrates the entire collector region 21 in the depth direction, that is, extends from the surface of the first epitaxial layer 12 in the depth direction to connect with the drift region 14.

[0108] Next, step S04 is performed to remove the first patterned mask layer 31 , and to form a base region 23 in the second region and an emitter region 24 in the third region.

[0109] For details, please refer to Figure 5h, remove the first patterned mask layer 31, form a second patterned mask layer 32, the opening of which exposes the second region, and perform a second ion implantation to form a base region 23 in the second region. Compared with the collector region 21 without the epitaxial region 22, since there is a part of the epitaxial region 22 with a lower concentration in the collector region 21 of the second region, after the second ion implantation and heat treatment, the ions implanted by the second ion implantation diffuse downward in the second region in a larger range (i.e., width), and the time for carriers to transit the base region 23 becomes longer, thereby reducing the amplification factor of the bipolar transistor. That is, the purpose of adjusting the second ion implantation process to change the base region 23 to reduce the amplification factor can be achieved without changing the process conditions of the second ion implantation at all.

[0110] Please refer to Figure 5i , remove the second patterned mask layer 32, form a third patterned mask layer, the opening of which exposes the third region, and perform a third ion implantation to form an emitter region 24 in the third region. Since the emitter region 24 is heavily doped and is integrated with the emitter, the opening of the third patterned mask layer can also expose a portion of the surface of the collector region 21, and simultaneously form a collector 26 after the third ion implantation.

[0111] Next, please refer to Figure 5j , the third patterned mask layer is removed to form a fourth patterned mask layer, the opening of which exposes a portion of the second region and a portion of the surface of the first epitaxial layer 12, and a fourth ion implantation is performed to form a heavily doped base 25 and an epitaxial layer (substrate 10) lead. Of course, it can be understood that before forming the above-mentioned substrate lead 28 and collector 26, a corresponding buffer layer (i.e., a first buffer layer 29a and a second buffer layer 29b) can also be formed.

[0112] Embodiment 2

[0113] Embodiment 2 provides a bipolar transistor.

[0114] Figure 6 This is a cross-sectional schematic diagram of a bipolar transistor provided in the second embodiment.

[0115] like Figure 6 As shown, the bipolar transistor provided in this embodiment includes a substrate 10, a first epitaxial layer 12, an emitter region 24, a base region 23, a collector region 21 and an epitaxial region 22. The first epitaxial layer 12 is disposed on the substrate 10. The emitter region 24 is disposed in the first epitaxial layer 12; the base region 23 covers the emitter region 24 along the periphery of the emitter region 24; the collector region 21 covers the base region 23 along the periphery of the base region 23; a plurality of epitaxial regions 22 are disposed in the collector region 21 and contact the base region 23, the doping concentration of the epitaxial region 22 is less than the doping concentration of the collector region 21 and the conductivity type of the epitaxial region 22 is the same as the conductivity type of the first epitaxial layer 12.

[0116] The substrate 10 and the first epitaxial layer 12 on the substrate 10 of the present embodiment may be semiconductor substrates of any material. The material of the substrate 10 may be, for example, silicon, silicon germanium, silicon carbide or silicon on insulator, and the material of the first epitaxial layer 12 may be, for example, silicon. In one example, in addition to the bipolar transistor provided on the first epitaxial layer 12 of the present embodiment, low-voltage devices (CMOS devices) and high-voltage devices (power devices) are also integrated at the same time, that is, the bipolar transistor of the present embodiment is part of the BCD (Bipolar_CMOS_DMOS) platform, therefore, the material of the substrate 10 and the first epitaxial layer 12 may both be silicon.

[0117] Please continue to refer to Figure 6 In this embodiment, two epitaxial layers, namely, the second epitaxial layer 11 and the first epitaxial layer 12, may be sequentially stacked on the substrate 10. A buried layer 13 is provided on the surface of the substrate 10, and the second epitaxial layer 11 is provided on the buried layer 13 and the surface of the substrate 10. A drift region 14 may be provided in the second epitaxial layer 11, and the bottom of the drift region 14 is in contact with the top of the buried layer 13. The conductivity type of the drift region 14 is the same as that of the buried layer 13, and the normal sizes of the two are basically the same. The first epitaxial layer 12 is provided on the surface of the drift region 14 and the second epitaxial layer 11, and the first epitaxial layer 12 is provided with structures such as the collector region 21, the base region 23 and the emitter region 24 of the bipolar transistor.

[0118] Please continue to refer to Figure 6 and Figure 2(The top view of the first embodiment is similar to that of the second embodiment), the first to third annular isolation structures 27c~27a which are arranged in sequence from large to small may be provided on the surface of the first epitaxial layer 12, and are used to define the collector region 21, the base region 23 and the emitter region 24 from large to small, respectively. Among them, the first to third annular isolation structures 27a may all be shallow trench isolation structures. Specifically, the emitter region 24 is defined by the smallest third annular isolation structure 27a, and its junction depth may be less than the depth of the third annular isolation structure 27a, which has the first conductivity type and is heavily doped. The base region 23 is defined by the second annular isolation structure 27b, and the emitter region 24 is covered along the periphery (edge) of the emitter region 24 (the emitter region 24 is provided in the base region 23), that is, the junction depth of the base region 23 is greater than the junction depth of the emitter region 24 and the depth of the trench isolation structure, and the base region 23 has the second conductivity type (opposite to the first conductivity type) and the doping concentration is less than the doping concentration of the emitter region 24. The collector region 21 is defined by the first annular isolation structure 27c, and covers the base region 23 along the periphery (edge) of the base region 23 (the base region 23 is arranged in the collector region 21), that is, the junction depth of the collector region 21 is greater than the junction depth of the emitter region 23 and is in contact with the drift region 14 in the depth direction. The collector region 21 has a first conductivity type, and its doping concentration is greater than the doping concentration of the first epitaxial layer and less than the doping concentration of the base region 23. Of course, electrodes for electrically leading out of each region are also provided on the surface of the above-mentioned regions (collector region 21, base region 23 and emitter region 24), that is, a collector 26 for electrically leading out the collector region 21, a collector for electrically leading out the base region 23, and an emitter for electrically leading out the emitter region 24. Among them, the emitter region 24 and the emitter can also be integrated, and a first buffer region 29a can also be provided between the collector region 21 and the collector 26, and the conductivity type of the first buffer region 29a is the same as the above two and the ion concentration is between the two.

[0119] In particular, please continue to refer to Figure 6 In this embodiment, a plurality of grooves are also provided in the collector region 21, and the grooves are filled with epitaxial materials to serve as the epitaxial region 22. The doping concentration of the epitaxial region 22 is lower than the doping concentration of the collector region 21, and the conductivity type of the epitaxial region 22 is the same as the conductivity type of the epitaxial layer, and the amplification factor (or gain, beta) of the bipolar transistor is adjusted by adjusting the shape, quantity and doping concentration of the epitaxial region 22. Since the ion concentration of the epitaxial region 22 is lower than the ion concentration of the collector region 21 and the base region 23, the overall concentration of the collector region 21 below the base region 23 can be reduced, and after heat treatment, the width of the base region 23 can be increased without changing the ion implantation process for forming the collector region 21 and the base region 23, and the time for carriers to transit the base region 23 can be prolonged, thereby reducing the amplification factor of the bipolar transistor. In a preferred example, the epitaxial material filled in the trench can be made to have the same doping concentration of the epitaxial region 22 as that of the first epitaxial layer 12 by using the epitaxial process for preparing the first epitaxial layer 12 to simplify the process and facilitate simulation calculations.

[0120] In addition, in addition to adjusting the amplification factor of the bipolar transistor by adjusting the planar shape and number of the epitaxial region 22 in the first embodiment, the present embodiment can also adjust the amplification factor of the bipolar transistor by adjusting the depth (trench depth) of the epitaxial region 22 and / or the in-situ doping concentration of the epitaxial region 22. Among them, the way of setting the planar shape and number of the epitaxial region 22 in the present embodiment can be specifically referred to the first embodiment, and will not be repeated here. In one example, the (upward) end of the epitaxial region 22 close to the base region 23 is in contact with the base region 23. Of course, the base region 23 is actually formed in the collector region 21 and the epitaxial region 22. The (downward) end of the epitaxial region 22 away from the base region 23 is located in the collector region 21, but does not extend to its bottom, that is, it does not directly contact the drift region 14. In another example, the (upward) end of the epitaxial region 22 close to the base region 23 is in contact with the base region 23, and the (downward) end of the epitaxial region 22 away from the base region 23 extends to the drift region 14. In other examples, the doping concentration of the epitaxial region 22 is greater than the doping concentration of the first epitaxial layer 12 , but less than the doping concentration of the collector region 21 .

[0121] This embodiment also provides a method for preparing a bipolar transistor.

[0122] Figure 7 This is a flow chart of a method for preparing a bipolar transistor provided in this embodiment.

[0123] like Figure 7 As shown, the method for preparing a bipolar transistor provided in this embodiment includes:

[0124] S01: providing a substrate on which a first epitaxial layer is formed and a first region, a second region and a third region are sequentially embedded from large to small;

[0125] S02: forming a first patterned mask layer on the first epitaxial layer, the opening of which exposes the first region, performing a first ion implantation, and forming a collector region in the first region of the first epitaxial layer;

[0126] S03: removing the first patterned mask layer to form a second patterned mask layer, the opening of which exposes a portion of the second region, and performing an etching process to form a plurality of grooves in the collector region of the second region;

[0127] S04: filling the trench with an epitaxial material to form an epitaxial region, wherein the doping concentration of the epitaxial region is lower than the doping concentration of the collector region and the conductivity type thereof is the same as the conductivity type of the first epitaxial layer;

[0128] S05: removing the second patterned mask layer, forming a base region in the second region, and forming an emitter region in the third region, wherein the collector region covers the base region along the periphery of the base region, and the base region covers the emitter region along the periphery of the emitter region.

[0129] Figure 8a~Figure 8j The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the bipolar transistor provided in the second embodiment will be combined with Figure 8a~Figure 8j The method for preparing the bipolar transistor provided in the second embodiment is described in detail.

[0130] First, step S01 is performed to provide a substrate 10 on which a first epitaxial layer 12 is formed and first to third regions are sequentially embedded from large to small.

[0131] For details, please refer to Figure 8a , a buried layer 13 is formed by doping (eg, ion implantation) on the surface of the substrate 10 .

[0132] Please refer to Figure 8b , a second epitaxial layer 11 is epitaxially formed on the substrate 10 and the buried layer 13.

[0133] Please refer to Figure 8c The drift region 14 is doped on the surface of the second epitaxial layer 11 . When the drift region 14 is formed by ion implantation, the implantation depth is greater than or equal to the thickness of the second epitaxial layer 11 , so that the drift region 14 is connected to the buried layer 13 .

[0134] Please refer to Figure 8d A first epitaxial layer 12 is epitaxially formed on the second epitaxial layer 11 and the drift region 14 , and when the first epitaxial layer 12 is epitaxially formed, it is doped in situ.

[0135] Please refer to Figure 8e , first to third annular isolation structures 27c~27a from large to small are formed on the surface of the first epitaxial layer 12, which are used to define the first to third regions corresponding to the collector region 21, the base region 23 and the emitter region 24, that is, the first annular isolation structure 27c (first region) defines the collector region 21, the second annular isolation structure 27b (second region) defines the base region 23, and the third annular isolation structure 27a (third region) defines the emitter region 24. The first to third annular isolation structures 27c~27a can all be shallow trench isolation structures.

[0136] Next, please refer to Figure 8f , perform step S02, form a first patterned mask layer 31 on the first epitaxial layer 12, the opening of which exposes the first region, perform a first ion implantation, and form a collector region 21 in the first region of the first epitaxial layer 12. The type of the first ion implantation, that is, the conductivity type of the collector region, can be determined according to the type of the bipolar transistor. In this embodiment, the bipolar transistor formed is an NPN type, the collector region 21 is an N type, the ion implantation depth is greater than or equal to the thickness of the first epitaxial layer 12, and the doping concentration is the smallest in the base region and the emitter region, but greater than the doping concentration of the first epitaxial layer 12.

[0137] Next, please refer to Figure 8g , perform step S03, remove the first patterned mask layer 31, form a second patterned mask layer 32, whose opening exposes part of the second region, and perform an etching process to form a plurality of grooves 22a in the collector region 21 of the second region. The second patterned mask layer 32 may include a stacked insulating dielectric layer and a photoresist layer, and the shape and number of its openings may refer to the planar shape and number of the epitaxial region in the first embodiment. After performing the etching process, the depth of the formed groove 22a is greater than the ion implantation depth (junction depth) of the subsequent base region, and the bottom of the groove 22a may be located in the collector region 21 or extend to the second epitaxial layer 11 (drift region), that is, the depth of the groove 22a is less than the sum of the thickness of the first epitaxial layer 12 and the second epitaxial layer 11.

[0138] Next, please refer to Figure 8h , executing step S04 , filling the trench 22 a with an epitaxial material to form an epitaxial region 22 , wherein the doping concentration of the epitaxial region 22 is less than the doping concentration of the collector region 21 and its conductivity type is the same as that of the first epitaxial layer 12 .

[0139] The photoresist layer on the second patterned mask layer 32 may be removed first, and the patterned insulating dielectric layer at the bottom thereof may be retained. The material of the epitaxial material filled by the epitaxial process is the same as that of the first epitaxial layer, and the epitaxial material is in-situ doped during the epitaxial process, and the doping concentration thereof is less than the doping concentration of the collector region 21. In a preferred example, the epitaxial process for forming the first epitaxial layer 12 may be used to form the epitaxial region 22 in the trench 22a.

[0140] Next, step S04 is performed to remove the second patterned mask layer 32 , and to form a base region 23 in the second region and an emitter region 24 in the third region.

[0141] For details, please refer to Figure 8i , remove the second patterned mask layer 32, form a third patterned mask layer 33, the opening of which exposes the second region, and perform a second ion implantation to form a base region 23 in the second region. Compared with the collector region 21 without the epitaxial region 22, since there is a part of the epitaxial region 22 with a lower concentration in the collector region 21 of the second region, after the second ion implantation and heat treatment, the ions implanted by the second ion implantation diffuse downward in the second region in a larger range (i.e., width), and the time for carriers to transit the base region 23 becomes longer, thereby reducing the amplification factor of the bipolar transistor. That is, the purpose of adjusting the second ion implantation process to change the base region 23 to reduce the amplification factor can be achieved without changing the process conditions of the second ion implantation at all.

[0142] Please refer to Figure 8j, remove the third patterned mask layer 33, form a fourth patterned mask layer, the opening of which exposes the third region, and perform a third ion implantation to form an emitter region 24 in the third region. Since the emitter region 24 is heavily doped and is integrated with the emitter, the opening of the fourth patterned mask layer 34 can also expose part of the surface of the collector region 21, and simultaneously form the collector 26 after the third ion implantation. Next, remove the fourth patterned mask layer, form a fifth patterned mask layer, the opening of which exposes part of the second region and part of the surface of the first epitaxial layer 12, and perform a fourth ion implantation to form a heavily doped base 25 and an epitaxial layer (substrate 10) lead. Of course, it can be understood that before forming the above-mentioned substrate lead 28 and the collector 26, a corresponding buffer layer (i.e., a first buffer layer 29a and a second buffer layer 29b) can also be formed.

[0143] Embodiment 3

[0144] Embodiment 3 provides a semiconductor device.

[0145] The semiconductor device provided in this embodiment includes a bipolar transistor, and the bipolar transistor includes a substrate, a first epitaxial layer, an emitter region, a base region, a collector region and an epitaxial region. The first epitaxial layer is arranged on the substrate. The emitter region is arranged in the first epitaxial layer; the base region covers the emitter region along the periphery of the emitter region; the collector region covers the base region along the periphery of the base region; a plurality of epitaxial regions are arranged in the collector region and contact the base region, the doping concentration of the epitaxial region is less than the doping concentration of the collector region and its conductivity type is the same as the conductivity type of the first epitaxial layer.

[0146] This embodiment also provides a method for preparing a semiconductor device, that is, the method for preparing the above-mentioned semiconductor device, and the method for preparing the semiconductor device includes the method for preparing a bipolar transistor as in the first or second embodiment. Specifically, in the semiconductor device of this embodiment, the bipolar transistor is similar to a parasitic transistor, that is, the bipolar transistor can be prepared synchronously in the process of preparing a CMOS device and / or a power device (such as a DMOS device), that is, by means of various ion implantation processes in the preparation of CMOS devices and / or power devices, and by changing the pattern of the graphical mask layer used for ion implantation to form the collector region, a number of epitaxial regions are formed in the collector region, and the width of the base region subsequently formed in the collector region and the epitaxial region is adjusted through the epitaxial region, so as to adjust the amplification factor of the bipolar transistor. Therefore, in the preparation process of the above-mentioned semiconductor device, a bipolar transistor with an adjustable amplification factor can be prepared synchronously under the premise of changing the ion implantation process. In particular, when the method of the first embodiment is adopted, a mask and a photolithography process may not be added.

[0147] To sum up, the present invention sets up several epitaxial regions in the collector region of the bipolar transistor, the doping concentration of the epitaxial region is lower than the doping concentration of the collector region and its conductivity type is the same as the conductivity type of the first epitaxial layer. After ion implantation and heat treatment of the base region, the width of the base region can be increased and the time for carriers to transit the base region can be prolonged without completely changing the ion implantation process for forming the collector region and the base region, thereby reducing the amplification factor of the bipolar transistor.

[0148] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A bipolar transistor, characterized in that: include: a substrate having a first epitaxial layer disposed thereon; an emitter region disposed in the first epitaxial layer; A base region covering the emitting region along the periphery of the emitting region; A collector region covering the base region along the periphery of the base region; A plurality of epitaxial regions are arranged in the collector region and in contact with the base region, wherein the doping concentration of the epitaxial regions is lower than the doping concentration of the collector region, and the conductivity type of the epitaxial regions is the same as the conductivity type of the first epitaxial layer and opposite to the conductivity type of the collector region.

2. The bipolar transistor according to claim 1, characterized in that: A drift region and a buried layer are sequentially arranged in the substrate under the first epitaxial layer from top to bottom, and the drift region is connected to the collector region and the buried layer.

3. The bipolar transistor according to claim 2, characterized in that: The epitaxial region is composed of the first epitaxial layer, one end of the epitaxial region close to the base region is in contact with the base region, and the other end of the epitaxial region is arranged at the bottom of the collector region and connected to the drift region.

4. The bipolar transistor according to claim 2, characterized in that: A plurality of grooves are arranged in the collector region, and the epitaxial region is composed of epitaxial materials filling the grooves. One end of the groove close to the base region contacts the base region, and the other end of the groove is arranged in the collector region.

5. The bipolar transistor according to claim 4, characterized in that: One end of the epitaxial region away from the base region extends into the drift region.

6. The bipolar transistor according to claim 1, characterized in that: The projection of the epitaxial region on the substrate is located within the projection of the base region on the substrate.

7. A method for preparing a bipolar transistor, characterized in that: include: Providing a substrate on which a first epitaxial layer is formed and a first region, a second region and a third region are sequentially embedded from large to small; forming a first patterned mask layer on the first epitaxial layer, wherein the opening of the first patterned mask layer exposes the first region, and the first patterned mask layer also covers a portion of the second region; Performing a first ion implantation to form a collector region and an epitaxial region in the first epitaxial layer, wherein the epitaxial region is the first epitaxial layer in the collector region that is not implanted with the first ions, the doping concentration of the epitaxial region is lower than the doping concentration of the collector region, and the conductivity type of the epitaxial region is the same as the conductivity type of the first epitaxial layer and opposite to the conductivity type of the collector region; The first patterned mask layer is removed, and a base region is formed in the second region, and an emitter region is formed in the third region, the collector region covers the base region along the periphery of the base region, the base region covers the emitter region along the periphery of the emitter region, and the base region is in contact with the epitaxial region.

8. The method for preparing a bipolar transistor according to claim 7, characterized in that: The substrate also includes a buried layer and a drift region, and the steps of forming the first epitaxial layer include: Doping on the surface of the substrate to form the buried layer; epitaxially forming a second epitaxial layer on the substrate and the buried layer; Doping the surface of the second epitaxial layer to form the drift region; The first epitaxial layer is epitaxially formed on the second epitaxial layer and the drift region.

9. The method for preparing a bipolar transistor according to claim 7, characterized in that: The step of forming the base region comprises: removing the first patterned mask layer; forming a second patterned mask layer on the first epitaxial layer and the collector region, wherein the opening of the second patterned mask layer exposes the second region; Performing a second ion implantation to form the base region in the collector region and the epitaxial region of the second region, wherein the implantation depth of the second ion implantation is less than the implantation depth of the first ion implantation; The second patterned mask layer is removed.

10. A method for preparing a bipolar transistor, characterized in that: include: Providing a substrate on which a first epitaxial layer is formed and a first region, a second region and a third region are sequentially embedded from large to small; forming a first patterned mask layer on the first epitaxial layer, the opening of which exposes the first region, performing a first ion implantation, and forming a collector region in the first region of the first epitaxial layer; removing the first patterned mask layer to form a second patterned mask layer, the opening of which exposes a portion of the second region, and performing an etching process to form a plurality of grooves in the collector region of the second region; Filling the trench with an epitaxial material to form an epitaxial region, wherein the doping concentration of the epitaxial region is lower than the doping concentration of the collector region, and the conductivity type of the epitaxial region is the same as the conductivity type of the first epitaxial layer and opposite to the conductivity type of the collector region; The second patterned mask layer is removed, a base region is formed in the second region, and an emitter region is formed in the third region, the collector region covers the base region along the periphery of the base region, the base region covers the emitter region along the periphery of the emitter region, and the base region is in contact with the epitaxial region.

11. A semiconductor device, characterized in that: Including bipolar transistors, The bipolar transistor comprises: a substrate having a first epitaxial layer disposed thereon; an emitter region disposed in the first epitaxial layer; A base region covering the emitting region along the periphery of the emitting region; A collector region covering the base region along the periphery of the base region; A plurality of epitaxial regions are arranged in the collector region and in contact with the base region, wherein the doping concentration of the epitaxial regions is lower than the doping concentration of the collector region, and the conductivity type of the epitaxial regions is the same as the conductivity type of the first epitaxial layer and opposite to the conductivity type of the collector region.

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