MOS device and manufacturing method thereof

Abstract

The present invention provides a MOS device and a manufacturing method thereof, wherein a buffer layer in a drift region of the MOS device covers the corner of a trench isolation structure, so that the ion doping concentration at the corner of the shallow trench isolation structure can be reduced, thereby reducing the generation of hot carriers at the corner, avoiding sudden changes in potential, reducing the possibility of device avalanche breakdown, and improving the range of the device's safe operating area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOS device and a manufacturing method thereof. Background Art

[0002] Transistor safe operating area (SOA) refers to the voltage and current at which power semiconductor devices can work normally as expected without causing damage. When the current and voltage exceed this range, the transistor may be damaged. Power semiconductor devices often suffer from "secondary breakdown" in applications, which is manifested as: the device voltage drops spontaneously and often suddenly, and the current inside the device suddenly accumulates. The voltage reduction and the sudden increase in current can cause circuit failure and local heating of the device, resulting in device degradation or even complete failure. Therefore, to ensure the working reliability of power semiconductor devices, it is necessary to study their maximum safe operating area range.

[0003] Currently, the commonly used semiconductor device isolation technology is STI (shallow trench) isolation. STI isolation technology has the advantages of small isolation area, no need for high temperature and long oxidation time. However, at the STI corners, the degree of collision ionization is high, and hot carriers are easily formed, causing avalanche breakdown, resulting in a narrow safe operating area of ​​the device.

[0004] In addition, in the high-voltage BCD (Bipolar_CMOS_DMOS) platform, in order to save chip costs, the injection layers of high-voltage power devices and logic IO devices are usually shared as much as possible. Taking DEMOS as an example, when a buffer layer is formed at its drain end by ion implantation, the implanted ions of its buffer layer are shared with the injection layer of the channel region of the low-voltage CMOS device. For CMOS devices, in order to prevent the punch-through effect in its channel region, the injection layer of its communication region needs to maintain a relatively high doping concentration. Therefore, the buffer layer of the DEMOS device also has a relatively high doping concentration. At the same time, since the shallow trench isolation structure at the drain end of the DEMOS limits the diffusion of ions, it will cause the corners of the shallow trench isolation structure to have a relatively high ion doping concentration after the thermal process. The high concentration will cause the on-state voltage of the device to be low, and avalanche breakdown is prone to occur. Summary of the invention

[0005] The object of the present invention is to provide a MOS device and a manufacturing method thereof to solve one or more problems in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a MOS device, comprising:

[0007] substrate;

[0008] The drift region and the channel region are respectively formed in the substrate;

[0009] A first shallow trench isolation structure and a second shallow trench isolation structure are formed in the drift region and the channel region, respectively;

[0010] A drain region and a source region are respectively formed in the drift region and the channel region, and the positions of the drain region and the source region are respectively defined by the first shallow trench isolation structure and the second shallow trench isolation structure; and a buffer layer is formed below the drain region and extends downward along the side wall of the first shallow trench isolation structure to cover the corner of the first shallow trench isolation structure, and the corner is located at the intersection of the side wall and the bottom wall of the first shallow trench isolation structure.

[0011] Optionally, in the MOS device, the buffer layer includes a plurality of sub-buffer layers, and the plurality of sub-buffer layers are sequentially spaced and arranged along an arrangement direction of the drain region.

[0012] Optionally, in the MOS device, an overlapping width between the buffer layer and the bottom wall of the first shallow trench isolation structure is L, and L is positively correlated with the ion doping concentration of the buffer layer.

[0013] Optionally, in the MOS device, two first shallow trench isolation structures are formed in the channel region, the drain region is located between the two first shallow trench isolation structures, and the buffer layer covers corners of the two first shallow trench isolation structures.

[0014] Optionally, in the MOS device, a first shallow trench isolation structure and two drain regions are formed in the channel region, the two drain regions are isolated by the first shallow trench isolation structure, a buffer layer is formed corresponding to each drain region, and the two buffer layers respectively cover the corners of the first shallow trench isolation structure.

[0015] Optionally, in the MOS device, the MOS device further includes: a gate, wherein the gate covers a portion of the drift region and a portion of the channel region.

[0016] The present invention also provides a method for manufacturing a MOS device, comprising:

[0017] Providing a substrate, forming a first shallow trench isolation structure in a first position region of the substrate, and forming a second shallow trench isolation structure in a second position region of the substrate;

[0018] Performing ion implantation in the first position region and the second position region respectively to form a drift region and a channel region respectively;

[0019] Performing ion implantation in the drift region to form a buffer layer, wherein the buffer layer extends downward from the surface of the substrate along the sidewall of the first shallow trench isolation structure to cover a corner of the first shallow trench isolation structure, wherein the corner is located at the intersection of the sidewall and the bottom wall of the first shallow trench isolation structure; and

[0020] Ion implantation is performed in the buffer layer and the channel region to form a drain region and a source region respectively.

[0021] Optionally, in the method for manufacturing the MOS device, when ion implantation is performed in the drift region to form the buffer layer, the implantation is performed downward at intervals along the arrangement direction of the drain region so that the formed buffer layer includes a plurality of sub-buffer layers, and the plurality of sub-buffer layers are arranged in sequence at intervals along the arrangement direction of the drain region.

[0022] Optionally, in the method for manufacturing the MOS device, the method further includes: adjusting the number of the sub-buffer layers according to the doping concentration of the ions injected into the buffer layer.

[0023] Optionally, in the method for manufacturing the MOS device, the method further includes: adjusting an overlapping width L between the buffer layer and the bottom wall of the first shallow trench isolation structure according to the doping concentration of ions injected into the buffer layer, wherein L is positively correlated with the ion doping concentration of the buffer layer.

[0024] In summary, in the MOS device and its manufacturing method provided by the present invention, the buffer layer in the drift region covers the corners of the trench isolation structure. In this way, the ion doping concentration at the corners of the shallow trench isolation structure can be reduced, thereby reducing the generation of hot carriers at the corners and avoiding sudden changes in electric potential, thereby reducing the possibility of device avalanche breakdown and improving the safe operating range of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart of the steps of the method for manufacturing a MOS device provided by the present embodiment;

[0026] Figure 2~Figure 8 for Figure 1 Schematic diagram of device structure corresponding to each step shown in;

[0027] Fig. 9 A schematic diagram of a layout for manufacturing a MOS device provided by an embodiment of the present invention;

[0028] Fig.10 A schematic diagram comparing the effects of different buffer layers on drain current and voltage;

[0029] Fig.11 The electric field distribution diagram under different overlapping widths L between the buffer layer and the first shallow trench isolation structure;

[0030] Fig.12 Surface ionization tangent line diagrams under different overlapping widths L between the buffer layer and the first shallow trench isolation structure;

[0031] The descriptions of the reference numerals are as follows:

[0032] 10 - substrate; 20 - first shallow trench isolation structure; 30 - second shallow trench isolation structure; 101 - drift region; 102 - channel region; 103 - buffer layer; 40 - gate; 104 - drain region; 105 - source region; 106 - body region. DETAILED DESCRIPTION

[0033] In order to make the purpose, advantages and features of the present invention clearer, the present invention is described in detail in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0034] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a MOS device, comprising the following steps:

[0035] S1, providing a substrate, forming a first shallow trench isolation structure in a first position region of the substrate, and forming a second shallow trench isolation structure in a second position region of the substrate;

[0036] S2, performing ion implantation in the first position region and the second position region respectively to form a drift region and a channel region respectively;

[0037] S3, performing ion implantation in the drift region to form a buffer layer, wherein the buffer layer extends downward from the surface of the substrate along the sidewall of the first shallow trench isolation structure to cover a corner of the first shallow trench isolation structure, wherein the corner is located at an intersection of the sidewall and the bottom wall of the first shallow trench isolation structure; and

[0038] S4, performing ion implantation in the buffer layer and the channel region to form a drain region and a source region respectively.

[0039] In the manufacturing method of the MOS device provided in an embodiment of the present invention, the buffer layer in the drift region covers the corner of the trench isolation structure. In this way, the ion doping concentration at the corner of the shallow trench isolation structure can be reduced, thereby reducing the generation of hot carriers at the corner, avoiding sudden changes in potential, reducing the possibility of device avalanche breakdown, and improving the range of the device's safe operating area.

[0040] The following combination Figure 2 to Figure 12 The method for manufacturing the MOS device provided in the embodiment of the present invention is further described in detail.

[0041] First, if Figure 2 As shown, a substrate 10 is provided, and a first shallow trench isolation structure 20 is formed in a first position region of the substrate 10 , and a second shallow trench isolation structure 30 is formed in a second position region of the substrate 10 .

[0042] Specifically, the base 10 includes a substrate and an epitaxial layer formed on the substrate, and the first position region and the second position region are both located in the epitaxial layer. For the convenience of description, the base 10 is not specifically distinguished in the following description.

[0043] The first shallow trench isolation structure 20 and the second shallow trench isolation structure 30 can be formed by the following process well known to those skilled in the art: depositing a silicon nitride layer on the substrate 10, and then patterning the silicon nitride layer to form a hard mask; then, etching the substrate 10 to form a shallow trench; finally, filling the shallow trench with oxide to form an isolation structure.

[0044] The first position region is a region where a drift region is formed later, and the second position region is a region where a channel region is formed later. A subsequent device gate is formed on the substrate 10 at the junction of the first position region and the second position region, covering part of the drift region and part of the channel region.

[0045] As an example, the MOS device formed in this embodiment is a DEMOS device, and two first shallow trench isolation structures 20 are formed in the first position area, and the area between the two first shallow trench isolation structures 20 is used to form a drain area. Figure 6 , the gate 40 and the drain region 104 are isolated by the first shallow trench isolation structure 20 , so that the drain can withstand a higher operating voltage.

[0046] Then, if Figure 3As shown, step S2 is performed to perform ion implantation in the first position region and the second position region respectively to form a drift region 101 and a channel region 102 respectively. Thus, the first shallow trench isolation structure 20 is located in the drift region 101, and the second shallow trench isolation structure 30 is located in the channel region 102. The first shallow trench isolation structure 20 located in the drift region 101 defines the position of the drain region, and the second shallow trench isolation structure 30 located in the channel region 102 defines the position of the source region.

[0047] Specifically, the drain region is located between the two first shallow trench isolation structures 20, and the source region is located between the second shallow trench isolation structure 30 and a gate formed subsequently, defined by the second shallow trench isolation structure 30.

[0048] As an example, the drift region 101 is an N-type drift region (NDW), and the channel region 102 is a P-type channel region (PW).

[0049] Then, if Figure 4 As shown, step S3 is performed to perform ion implantation in the drift region 101 to form a buffer layer 103 .

[0050] The buffer layer 103 extends downward from the surface of the substrate 10 along the sidewall of the first shallow trench isolation structure 20 to cover the corner of the first shallow trench isolation structure 20. That is, the buffer layer 103 not only fills between the two first shallow trench isolation structures 20, but also extends downward and on both sides to below the two first shallow trench isolation structures 20, overlapping with part of the bottom wall of the two first shallow trench isolation structures 20, so that the buffer layer 103 can cover the corner formed by the intersection of the sidewall and the bottom wall of the first shallow trench isolation structure 20, so that the doping ion concentration at the corner can be reduced, thereby reducing the generation of hot carriers at the corner, avoiding abrupt changes in potential, reducing the possibility of avalanche breakdown of the device, and improving the range of the device safe working area.

[0051] As an example, the buffer layer 103 is an N-type buffer layer (NW).

[0052] Better, such as Fig. 9 As shown, when ion implantation is performed in the drift region 101 to form the buffer layer 103, the ion implantation is performed downwardly at intervals along the arrangement direction of the drain region, so that the formed buffer layer 103 includes a plurality of sub-buffer layers 103, and the plurality of sub-buffer layers 103 are sequentially arranged at intervals along the arrangement direction of the drain region. Figure 8 As shown in the DEMOS device layout, it should be understood that the layout direction of the drain region 104 is Figure 8The length direction of the drain region 104 is shown in FIG.

[0053] As mentioned above, when DEMOS is formed, the implanted ions of the buffer layer 103 are usually shared with the implanted layer of the channel region of the CMOS device. However, in order to avoid the punch-through effect in the channel region of the CMOS device, the ion implantation in the channel region needs to use a relatively high concentration. The use of this ion implantation concentration in the DEMOS device buffer layer will result in a relatively high ion doping concentration at the corner of the shallow trench isolation structure at the drain end of the DEMOS device, which is prone to avalanche breakdown. In the embodiment of the present invention, the total concentration of the buffer layer 103 can be reduced by arranging multiple sub-buffer layers 103 at intervals, thereby achieving the purpose of reducing the ion doping concentration at the corner of the first shallow trench isolation structure 20, so that the possibility of avalanche breakdown of the device can be reduced.

[0054] Further preferably, when forming the buffer layer 103, the overlapping width L between the buffer layer 103 and the bottom wall of the first shallow trench isolation structure 20 is adjusted according to the doping concentration of the ions injected into the buffer layer 103, and L is positively correlated with the ion doping concentration of the buffer layer 103. Specifically, if the injected ion concentration of the buffer layer 103 is greater and the number of the sub-buffer layers 103 is greater, the overlapping width L can be increased accordingly, and if the injected ion concentration of the buffer layer 103 is smaller and the number of the sub-buffer layers 103 is relatively small, the overlapping width L can be reduced accordingly. If too many ions are injected into the buffer layer 103, the withstand voltage between the source and the drain will be reduced. By designing the overlapping width L to change with the change of the ion injection concentration, it is possible to avoid the withstand voltage between the source and the drain being reduced due to the excessively high injection ion concentration of the buffer layer 103.

[0055] As mentioned above, in general, the implanted ions of the buffer layer 103 are shared with the implanted ions of the channel region implanted layer of the CMOS device, and the ion implantation concentration is fixed. Therefore, the overlap width L can be adjusted only according to the number of the sub-buffer layers 103. The number of the sub-buffer layers 103 can be reduced by increasing the distance between two adjacent sub-buffer layers 103, and preferably, the distance between two adjacent sub-buffer layers 103 is equal, so that the implanted ions are evenly distributed.

[0056] As an example, when forming the buffer layer 103, the ion implantation concentration is 1.5E13 / cm 3, the overlap width with the bottom wall of each of the first shallow trench isolation structures 20 may be about 0.1-0.3 μm, specifically 0.1 μm, 0.2 μm, 0.25 μm, 0.3 μm, etc. As an example, if the depth of the first shallow trench isolation structure 20 is 0.3 μm, the ion implantation depth when forming the buffer layer 103 is about 0.4 μm, that is, the buffer layer 103 continues to extend downward from the bottom of the first shallow trench isolation structure 20 by about 0.1 μm.

[0057] like Figure 5 As shown, the step of forming a gate 40 on the substrate 10 can be performed after this step is performed. The gate 40 can be composed of a gate oxide layer, a gate polysilicon layer and a silicon nitride sidewall. The process of forming the gate 40 is well known to those skilled in the art and will not be described here. The gate 40 covers part of the drift region 101 and part of the channel region 102.

[0058] Then, if Figure 6 As shown, step S4 is performed to perform ion implantation in the buffer layer 103 and the channel region 102 to form a drain region 104 and a source region 105 respectively.

[0059] The position of the drain region 104 has been defined by the first shallow trench isolation structure 20 as being located between two first shallow trench isolation structures 20 ; the position of the source region 105 has been defined by the second shallow trench isolation structure 30 as being located between the gate 40 and the second shallow trench isolation structure 30 .

[0060] As an example, the drain region 104 is an N-type heavily doped drain region, referred to as an N+ drain region, and the source region 105 is an N-type heavily doped source region, referred to as an N+ source region.

[0061] After the drain region 104 is formed, the doping ion concentrations of the drain region 104, the buffer layer 103, and the drift region 101 decrease from top to bottom, forming a gradual junction, reducing the potential change, pushing the surface electric field peak into the device body, weakening the impact ionization intensity of the device surface, thereby reducing the probability of hot carrier generation and increasing the safe working area of ​​the device. If the doping ion concentration of the buffer layer 103 is too high, the device on-state voltage will be reduced. The manufacturing method provided by the present invention can improve the safe working area of ​​the device, and because it covers the corners of the shallow trench isolation structure, it will not cause avalanche breakdown, ensuring that the device passes the acceptance test (WAT).

[0062] Optional, such as Figure 7As shown, the manufacturing method provided by the present invention further includes: performing ion implantation in the logic to form a body region 106, wherein the body region 106 and the source region 105 are located on both sides of the second shallow trench isolation structure 30. Subsequently, by electrically connecting the body region 106 and the source region 105, the contact resistance of the source region 105 can be reduced.

[0063] As an example, the body region 106 is a P-type heavily doped body region, referred to as a P+ body region.

[0064] In other embodiments, Figure 8 As shown, in step S1, the drift region 101 is formed with a first shallow trench isolation structure 20, and the drift region 101 is isolated into two regions by the first shallow trench isolation structure 20. The two regions are implanted with N+ ions to form two drain regions 104 in step S4. And in step S3, when forming the buffer layer 103, N ions are implanted into the two regions isolated by the first shallow trench isolation structure 20, so that two buffer layers 103 are formed in the drift region 101, and the two buffer layers 103 extend downward along the two opposite side walls of the first shallow trench isolation structure 20 to cover the corners of the first shallow trench isolation structure 20.

[0065] Accordingly, an embodiment of the present invention further provides a MOS device. The MOS device provided by the embodiment of the present invention can be manufactured by the manufacturing method provided by the embodiment of the present invention. The MOS device provided by the embodiment of the present invention includes:

[0066] Base 10;

[0067] The drift region 101 and the channel region 102 are respectively formed in the substrate 10;

[0068] A first shallow trench isolation structure 20 and a second shallow trench isolation structure 30 are formed in the drift region 101 and the channel region 102 respectively;

[0069] A drain region 104 and a source region 105 are formed in the drift region 101 and the channel region 102, respectively, and the positions of the drain region 104 and the source region 105 are defined by the first shallow trench isolation structure 20 and the second shallow trench isolation structure 30, respectively; and,

[0070] The buffer layer 103 is formed below the drain region 104 and extends downward along the sidewall of the first shallow trench isolation structure 20 to cover the corner of the first shallow trench isolation structure 20 , where the corner is located at the intersection of the sidewall and the bottom wall of the first shallow trench isolation structure 20 .

[0071] The specific structure of the MOS device can be found in the above-mentioned manufacturing method section, which will not be described in detail here.

[0072] Fig.10 Schematic diagram comparing the effects of different buffer layers 103 on drain current and voltage. Fig.10 In the figure, DrainVoltage indicates drain voltage, Drain Current indicates drain current, Drain with NW indicates that the drain is provided with a buffer layer that does not cover the corner of the first shallow trench isolation structure 20, Drain with NW Slot indicates that the drain is provided with a buffer layer that covers the corner of the first shallow trench isolation structure 20, and Drain without NW indicates that the drain is not provided with a buffer layer. Fig.10 It can be seen from the figure that after the drain is designed with the buffer layer 103 covering the corner of the first shallow trench isolation structure 20, the drain potential can change more smoothly.

[0073] Fig.11 1 is an electric field distribution diagram under different overlapping widths L between the buffer layer 103 and the first shallow trench isolation structure 20 . Fig.11 The upper left figure shows that the buffer layer 103 and the first shallow trench isolation structure 20 do not overlap (WithoutWN). In the upper right figure, L=0.11μm, in the lower left figure, L=0.2μm, and in the lower right figure, L=0.3μm. By comparison, it can be seen that by designing the buffer layer 103 to cover the corners of the first shallow trench, as the overlap width L changes from 0 to 0.11μm, 0.2μm, and 0.3μm, the electric field is increasingly concentrated inside the device. This shows that, compared with the buffer layer that does not cover the corners of the shallow trench isolation structure in the prior art design, in this embodiment, the impact ionization intensity of the device surface is further improved by designing the buffer layer to cover the corners of the shallow trench isolation structure, thereby further reducing the possibility of device avalanche breakdown.

[0074] Fig.12 It is a surface ionization tangent diagram under different overlapping widths L between the buffer layer 103 and the first shallow trench isolation structure 20 . Fig.12 In the figure, the horizontal axis represents the overlap width L, and the vertical axis represents the peak electric field on the device surface. It can be seen from the figure that as the overlap width L changes from 0 to 0.11μm, 0.2μm, and 0.3μm, the peak electric field on the surface decreases successively. This shows that by designing the buffer layer 103 to cover the corner of the first shallow trench, the peak electric field on the device surface is pushed into the inside of the device. This shows that compared with the buffer layer in the prior art that does not cover the corner of the shallow trench isolation structure, in this embodiment, the impact ionization intensity on the device surface is further improved by designing the buffer layer to cover the corner of the shallow trench isolation structure, thereby further reducing the possibility of device avalanche breakdown.

[0075] To sum up, in the MOS device and its manufacturing method provided by the embodiments of the present invention, the buffer layer in the drift region extends downward along the side wall of the shallow trench structure and then covers the corner of the trench isolation structure. In this way, the ion doping concentration at the corner of the shallow trench isolation structure can be reduced, thereby reducing the generation of hot carriers at the corner, avoiding sudden changes in electric potential, reducing the possibility of device avalanche breakdown, and improving the range of the device's safe operating area.

[0076] It should be noted that although the DEMOS device is used as an example to describe the technical solution of the present invention in the embodiment of the present invention, it should be understood that the technical solution of the present invention is also applicable to other MOS devices, and any MOS device that requires a buffer layer in the drift region is within the protection scope of the present invention.

[0077] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A MOS device, characterized in that: include: substrate; The drift region and the channel region are respectively formed in the substrate; A first shallow trench isolation structure and a second shallow trench isolation structure are formed in the drift region and the channel region, respectively; A drain region and a source region are formed in the drift region and the channel region, respectively, and positions of the drain region and the source region are defined by the first shallow trench isolation structure and the second shallow trench isolation structure, respectively; as well as, A buffer layer is formed below the drain region and extends downward along the side wall of the first shallow trench isolation structure to cover the corner of the first shallow trench isolation structure, wherein the corner is located at the intersection of the side wall and the bottom wall of the first shallow trench isolation structure, and the overlapping width between the buffer layer and the bottom wall of the first shallow trench isolation structure is L, and L is positively correlated with the ion doping concentration of the buffer layer.

2. The MOS device according to claim 1, characterized in that: The buffer layer includes a plurality of sub-buffer layers, and the plurality of sub-buffer layers are sequentially arranged at intervals along an arrangement direction of the drain region.

3. The MOS device according to claim 1, wherein: Two first shallow trench isolation structures are formed in the channel region, the drain region is located between the two first shallow trench isolation structures, and the buffer layer covers the corners of the two first shallow trench isolation structures.

4. The MOS device according to claim 1, characterized in that: A first shallow trench isolation structure and two drain regions are formed in the channel region, the two drain regions are isolated by the first shallow trench isolation structure, a buffer layer is formed corresponding to each drain region, and the two buffer layers respectively cover the corners of the first shallow trench isolation structure.

5. The MOS device according to claim 1, wherein: The MOS device further includes a gate, wherein the gate covers a portion of the drift region and a portion of the channel region.

6. A method for manufacturing a MOS device, characterized in that: include: Providing a substrate, forming a first shallow trench isolation structure in a first position region of the substrate, and forming a second shallow trench isolation structure in a second position region of the substrate; Performing ion implantation in the first position region and the second position region respectively to form a drift region and a channel region respectively; Performing ion implantation in the drift region to form a buffer layer, the buffer layer extending downward from the surface of the substrate along the side wall of the first shallow trench isolation structure to cover the corner of the first shallow trench isolation structure, the corner being located at the intersection of the side wall and the bottom wall of the first shallow trench isolation structure, and when forming the buffer layer, adjusting the overlapping width L of the buffer layer and the bottom wall of the first shallow trench isolation structure according to the doping concentration of the ions implanted in the buffer layer, wherein L is positively correlated with the ion doping concentration of the buffer layer; and Ion implantation is performed in the buffer layer and the channel region to form a drain region and a source region respectively.

7. The method for manufacturing a MOS device according to claim 6, wherein: When ion implantation is performed in the drift region to form the buffer layer, the ion implantation is performed downward at intervals along the arrangement direction of the drain region, so that the formed buffer layer includes a plurality of sub-buffer layers, which are sequentially arranged at intervals along the arrangement direction of the drain region.

8. The method for manufacturing a MOS device according to claim 7, characterized in that: The method further includes: adjusting the number of the sub-buffer layers according to the doping concentration of the ions implanted into the buffer layer.

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