A method for preparing a TBC solar cell with a polished isolation region structure

Abstract

The present invention relates to the field of solar cells and discloses a method for preparing a TBC solar cell with a polished isolation region structure. First, the present invention improves the conventional isolation region structure with a pyramid velvet surface into a polished isolation region structure protruding from the back of the silicon wafer, which can increase the reflection of incident light in the silicon matrix, thereby improving the efficiency of the cell. I sc At the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF, Secondly, the present invention optimizes the process steps to achieve a TBC solar cell by depositing an intrinsic polycrystalline silicon layer in a single step, which can effectively improve the performance and yield of the product and significantly reduce the production cost at the same time.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a method for preparing a TBC solar cell with a polished isolation region structure. Background Art

[0002] IBC solar cells are cross-finger back contact cells, with no metal grid lines on the front of the cell, and the emitter and back field as well as the corresponding positive and negative metal electrodes are integrated in a cross-finger shape on the back of the cell; this structure can avoid the metal grid line electrode blocking the light, can make full use of the incident light, reduce optical losses, and have a higher short-circuit current, thereby effectively improving the photoelectric conversion efficiency of the cell. Among them, TBC solar cells are a type of IBC solar cells.

[0003] In order to avoid short circuit, an insulating isolation region is provided between the n region (phosphorus diffusion region) and the p region (boron diffusion region) on the back of the TBC solar cell. At present, the structure of the isolation region of the TBC solar cell is usually groove-shaped (that is, the height of the isolation region is lower than the phosphorus diffusion layer and the boron diffusion layer), and a pyramid velvet surface is usually provided on the silicon wafer surface of the isolation region, such as Fig. 9 The applicant found that the pyramid velvet surface formed on the surface of the isolation area on the back of the silicon wafer is not conducive to increasing the reflection of the incident light in the silicon matrix, thereby limiting the battery I sc .

[0004] In addition, the current preparation of TBC solar cells usually requires first depositing a layer of intrinsic polysilicon on the back of the silicon wafer, then converting it into a boron diffusion layer through a boron diffusion process, and then depositing another layer of intrinsic polysilicon, and then converting it into a phosphorus diffusion layer through a phosphorus diffusion process. The disadvantage of the above method is that during the two depositions of the intrinsic polysilicon layer, uneven thermal stress distribution is prone to occur, resulting in warping and fragmentation of the silicon wafer, which will significantly affect the performance and yield of the product. In addition, the two depositions of the intrinsic polysilicon layer will also greatly increase the use of special gases, thereby increasing costs.

[0005] In summary, further optimizing the structure of the battery isolation area can further improve the battery I sc ; At the same time, it is of great significance to simplify the battery preparation process to improve battery performance, increase yield rate and reduce cost. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a TBC solar cell with a polished isolation region structure. First, the present invention improves the conventional isolation region structure with a pyramid velvet surface into a polished isolation region structure protruding from the back of the silicon wafer, which can increase the reflection of incident light in the silicon matrix, thereby improving the cell. I scAt the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF ; Secondly, the present invention optimizes the process steps to achieve a TBC solar cell by depositing an intrinsic polycrystalline silicon layer in a single step, which can effectively improve the performance and yield of the product and significantly reduce the production cost at the same time.

[0007] The specific technical solution of the present invention is: the present invention provides a method for preparing a TBC solar cell with a polished isolation region structure, comprising the following steps:

[0008] S1, double-sided polishing of silicon wafer.

[0009] S2. A tunneling oxide layer, an intrinsic polysilicon layer, and a mask layer are formed on the back side.

[0010] The purpose of setting the intrinsic polysilicon layer is to provide a basis for subsequent boron diffusion and phosphorus diffusion, and the purpose of setting the mask layer is to block doping atoms from entering the intrinsic polysilicon layer at the bottom during the subsequent boron diffusion and phosphorus diffusion process.

[0011] S3, groove removal of the mask layer in the boron diffusion design area.

[0012] A groove is formed in the pre-designed boron diffusion region, and after the mask layer in the region is removed, the boron atoms can diffuse into the intrinsic polysilicon layer in the region in the subsequent boron diffusion process.

[0013] S4, removing the residual mask layer in the grooved area by alkaline cleaning to fully expose the intrinsic polysilicon layer in the area.

[0014] S5. Boron diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer in the boron diffusion design area are converted into a boron diffusion layer and a BSG layer respectively.

[0015] In the above boron diffusion process, the ungrooved area of ​​S3 can effectively block boron atoms from entering the intrinsic polysilicon layer due to the protection of the mask layer, and only the inner layer and the surface layer of the intrinsic polysilicon layer exposed in the boron diffusion area are converted into a boron diffusion layer and a BSG layer respectively.

[0016] S6. Retain the mask layer in the isolation area design region, and remove the mask layer in the phosphorus diffusion area design region by trenching.

[0017] The pre-designed phosphorus diffusion area is grooved and the mask layer of the area is removed. In the subsequent phosphorus diffusion process, phosphorus atoms can diffuse into the intrinsic polysilicon layer of the area, turning it into a phosphorus diffusion layer. The mask layer of the isolation area design area is retained to pave the way for the subsequent formation of a polished isolation area structure protruding from the back of the silicon wafer. In addition, the BSG layer formed by S5 boron diffusion can also effectively block phosphorus atoms from entering the bottom boron diffusion layer during the phosphorus diffusion process.

[0018] S7, alkaline cleaning removes the residual mask layer in the slotted area in S6 to fully expose the intrinsic polysilicon layer in the area. The deposited layer in the boron diffusion layer area and the bottom of the isolation area design area can be protected from being corroded by alkaline because the surface is protected by the BSG layer and the mask layer respectively.

[0019] S8. Phosphorus diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer in the phosphorus diffusion design area are converted into a phosphorus diffusion layer and a PSG layer respectively.

[0020] In the above phosphorus diffusion process, since the surfaces of the boron diffusion layer and the intrinsic polysilicon layer in the isolation area are protected by the BSG layer and the mask layer respectively, phosphorus atoms cannot diffuse in, and only the inner layer and the surface layer of the intrinsic polysilicon layer exposed in the phosphorus diffusion design area are converted into the phosphorus diffusion layer and the PSG layer respectively.

[0021] S9, remove the coating on the front and side surfaces of the silicon wafer.

[0022] S10, wet cleaning and front texturing, a pyramid texturing surface is formed on the front side of the silicon wafer, and the residual mask layer, PSG layer and BSG layer are removed by pickling to form a polishing isolation area protruding from the back side of the silicon wafer.

[0023] In the above S10 process, since the plating layer on the front side of the silicon wafer has been completely removed and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface) can be formed during the texturing process; and for the entire area on the back side of the silicon wafer, there are PSG layer / mask layer / BSG layer respectively, which can prevent alkali corrosion from being destroyed. After cleaning and texturing, the mask layer, PSG layer and BSG layer remaining on the back side of the silicon wafer are removed by acid pickling to form a boron diffusion layer and a phosphorus diffusion layer with a cross-contact structure, as well as a polished isolation area protruding from the back side of the silicon wafer. The polished isolation area is an untransformed intrinsic polysilicon layer located between the boron diffusion layer and the phosphorus diffusion layer, which plays an insulating role, and the surface of the isolation area is a polished plane. Compared with the isolation area of ​​the conventional pyramid velvet surface, it can increase the reflection of incident light in the silicon substrate and improve the battery. I sc At the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF .

[0024] S11, double-sided coating, after double-sided coating, a passivation anti-reflection layer is generated on the front and back sides of the silicon wafer.

[0025] S12, screen printing, sintering, and light injection to obtain a TBC solar cell.

[0026] In summary, firstly, the present invention improves the conventional isolation region structure with pyramid velvet surface into a polished isolation region structure protruding from the back of the silicon wafer, which can increase the reflection of incident light in the silicon matrix, thereby improving the efficiency of the battery. I sc .

[0027] Secondly, the present invention optimizes the process steps to achieve a TBC solar cell by depositing an intrinsic polysilicon layer only once, thereby avoiding problems such as uneven distribution of thermal stress caused by multiple depositions of the intrinsic polysilicon layer, which leads to reduced product performance and yield rate. In addition, the use of a single deposition of the intrinsic polysilicon layer can also significantly reduce the use of special gases and reduce production costs.

[0028] Preferably, in S2, the mask layer is formed by PECVD under the following conditions: the reaction gas is N 2 O、SiH 4 , reaction temperature 400~500℃, N 2 The flow rate of O is 9000~11000 sccm, SiH 4 The flow rate is 1000~5000 sccm, the power is 3000~20000 W, the deposition time is 100~3000 s, and the mask layer thickness is 30~300 nm.

[0029] Preferably, in S2, the mask layer may also be formed by ultraviolet laser oxidation treatment:

[0030] First, a mask layer prototype is generated under the conditions of an oxygen concentration of 20-40% and an ultraviolet laser wavelength of 300-400 nm;

[0031] Then, a denser mask layer is formed under the conditions of oxygen concentration of 50~90% and ultraviolet laser wavelength of 200~300 nm.

[0032] The present invention has found in previous experiments that the density of the mask layer obtained by conventional PECVD or conventional one-step ultraviolet laser oxidation process is not ideal, which will increase the risk of boron atoms and phosphorus atoms diffusing to the intrinsic polysilicon layer during subsequent boron diffusion and phosphorus diffusion, thereby causing battery leakage or performance degradation. To this end, the present invention has designed the above-mentioned special two-step differentiated ultraviolet laser oxidation process, the principle of which is: different laser wavelengths penetrate into the silicon interior at different depths. In the first step of the above process of the present invention, the wavelength is larger and the penetration depth is deeper, which can initially form a thicker mask layer prototype; the second step has a shorter wavelength and a shallower penetration depth, which can make the mask layer prototype denser in texture while the thickness remains almost unchanged; at the same time, with different oxygen concentration treatment environments, the formed mask layer can more effectively block the internal expansion of boron atoms and phosphorus atoms.

[0033] Further preferably, in S2, the conditions of the ultraviolet oxidation laser treatment are specifically:

[0034] First in O 2 The mask layer prototype is generated under the conditions of flow rate 10~100 sccm, ambient oxygen concentration 20~40%, UV laser wavelength 300~400 nm, power 10~500 W, and processing time 1~30 s;

[0035] Then in O 2 Under the conditions of a flow rate of 100-500 sccm, an ambient oxygen concentration of 50-90%, an ultraviolet laser wavelength of 200-300 nm, a power of 2-50 W, and a processing time of 1-30 s, a denser mask layer is formed; the thickness of the mask layer is 30-300 nm.

[0036] Preferably, in S2, the deposition conditions of the tunnel oxide layer are: 2 Flow rate is 10000~80000 sccm, reaction temperature is 400~800℃, time is 200~1000 s, and tunneling oxide layer thickness is 2~10 nm.

[0037] Preferably, in S2, the deposition conditions of the intrinsic polysilicon layer are: SiH 4 Flow rate 300~2000 sccm, reaction temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, intrinsic polysilicon layer thickness 100~300 nm.

[0038] Preferably, in S3, laser patterning is used to remove the mask layer in the boron diffusion design area.

[0039] Preferably, in S5, the boron diffusion conditions are: temperature 800-950°C, diffusion time 5-50 min, BCl 3 Flow rate 50~500 sccm, O 2 Flow rate 500~2000 sccm; oxidation advancement temperature 900~1050℃, O 2 The flow rate is 5000~30000 sccm, the advancement time is 30~80 min, and a BSG layer with a thickness of 30~70 nm is generated.

[0040] Preferably, in S6, laser patterning is used to remove the mask layer in the phosphorus diffusion design area.

[0041] Preferably, in S8, the phosphorus diffusion conditions are: temperature 750-850°C, diffusion time 5-30 min, POCl 3 The nitrogen gas is carried at a flow rate of 500~1200 sccm. 2 Flow rate 500~1000 sccm; oxidation advancement temperature 850~950℃, O2 Flow rate 1000~10000 sccm, push time 20~60 min, generate PSG layer with thickness of 30~70 nm

[0042] Compared with the prior art, the beneficial effects of the present invention are:

[0043] (1) The present invention improves the conventional isolation region structure with a pyramid velvet surface into a polished isolation region structure protruding from the back of the silicon wafer, which can increase the reflection of incident light in the silicon substrate, thereby improving the battery I sc At the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF .

[0044] (2) The present invention optimizes the process steps to achieve a TBC solar cell by depositing an intrinsic polycrystalline silicon layer in a single step, which can effectively improve the performance and yield of the product and significantly reduce the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of the structure of the silicon wafer after double-sided polishing.

[0046] Figure 2 Schematic diagram of the structure after the tunnel oxide layer / intrinsic polysilicon layer / mask layer are deposited on the silicon wafer.

[0047] Figure 3 This is a schematic diagram of the structure after the silicon wafer laser one-time patterning groove mask layer + cleaning.

[0048] Figure 4 Schematic diagram of the structure after boron diffusion of silicon wafer.

[0049] Figure 5 This is a schematic diagram of the structure of the silicon wafer laser secondary patterning slot mask layer + after cleaning.

[0050] Figure 6 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0051] Figure 7 This is a schematic diagram of the structure of the silicon wafer after cleaning and texturing.

[0052] Figure 8 Schematic diagram of the structure of TBC solar cell.

[0053] Fig. 9 This is a schematic diagram of the structure of the solar cell prepared in Comparative Example 1.

[0054] The reference numerals are: N-type single crystal silicon wafer 1; tunnel oxide layer 2; intrinsic polysilicon layer 3; mask layer 4; boron diffusion layer 5; BSG layer 6; phosphorus diffusion layer 7; PSG layer 8; pyramid velvet surface 9; passivation anti-reflection layer 10; electrode layer 11. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the embodiments.

[0056] A method for preparing a TBC solar cell with a polished isolation region structure comprises the following steps:

[0057] S1, double-sided polishing of silicon wafer.

[0058] In some specific implementation cases, an N-type single crystal silicon wafer 1 after diamond wire cutting is selected, with a thickness of ~150 μm and a size of 182.2 mm×186.7 mm. The silicon wafer is placed in an alkaline polishing tank, the temperature is maintained at 75~85°C, and the time is 6~8 min for double-sided polishing, the polishing thickness is 3~7 μm, and the thinning amount is 0.35~0.45 g. Figure 1 shown.

[0059] S2, forming a tunnel oxide layer 2 (using LPCVD), an intrinsic polysilicon layer 3 (using LPCVD), and a mask layer 4 on the back of the silicon wafer in sequence, such as Figure 2 shown.

[0060] In some specific implementation cases, the deposition conditions of the tunnel oxide layer are: 2 Flow rate 10000~80000sccm, reaction temperature 400~800℃, time 200~1000 s, tunneling oxide layer thickness 2~10 nm.

[0061] In some specific implementation cases, the deposition conditions of the intrinsic polysilicon layer are: SiH 4 Flow rate 300~2000sccm, reaction temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, intrinsic polysilicon layer thickness 100~300 nm.

[0062] In some specific implementation cases, the mask layer is formed by PECVD under the following conditions: the reaction gas is N 2 O、SiH 4 , reaction temperature 400~500℃, N 2 The flow rate of O is 9000~11000 sccm, SiH 4 The flow rate is 1000~5000sccm, the power is 3000~20000 W, the deposition time is 100~3000 s, and the mask layer thickness is 30~300 nm.

[0063] In some more preferred implementation cases, the mask layer can also be formed by ultraviolet oxidation laser treatment: first, a mask layer prototype is generated under the conditions of an oxygen concentration of 20~40% and an ultraviolet laser wavelength of 300~400 nm; and then a denser mask layer is formed under the conditions of an oxygen concentration of 50~90% and an ultraviolet laser wavelength of 200~300 nm.

[0064] More preferably, in S2, the conditions of the ultraviolet oxidation laser treatment are as follows: firstly 2 The mask layer prototype is generated under the conditions of flow rate 10~100sccm, ambient oxygen concentration 20~40%, UV laser wavelength 300~400nm, power 10~500W, and processing time 1~30s; then 2 Under the conditions of flow rate of 100-500 sccm, ambient oxygen concentration of 50-90%, ultraviolet laser wavelength of 200-300 nm, power of 2-50 W, and processing time of 1-30 s, a denser mask layer is formed; the thickness of the mask layer is 30-300 nm.

[0065] S3, laser one-time patterning groove removal of the mask layer of the boron diffusion design area. The pre-designed boron diffusion area is grooved, and after the mask layer of the area is removed, the boron atoms can diffuse into the intrinsic polysilicon layer of the area in the subsequent boron diffusion process.

[0066] In some specific implementation cases, a picosecond laser is used for patterning grooving, and the conditions are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

[0067] S4, alkaline cleaning to remove the residual mask layer in the groove area so that the intrinsic polysilicon layer in the area is fully exposed, such as Figure 3 shown.

[0068] In some specific implementation cases, the silicon wafer is placed in an alkaline solution for cleaning at a temperature of 75~85°C. During the experiment, by adjusting different parameters such as cleaning time and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the grooved area can be accurately removed to prevent excessive removal of the bottom intrinsic polysilicon layer during the alkaline cleaning process.

[0069] S5, boron diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the boron diffusion design area are respectively converted into the boron diffusion layer 5 and the BSG layer 6. In the above boron diffusion process, the S3 ungrooved area can effectively block the boron atoms from entering the intrinsic polysilicon layer 3 due to the protection of the mask layer 4, and only the inner layer and the surface layer of the intrinsic polysilicon layer 3 exposed in the boron diffusion area are respectively converted into the boron diffusion layer 5 and the BSG layer 6. Figure 4 shown.

[0070] In some specific implementation cases, the boron diffusion conditions are: temperature 800-950°C, diffusion time 5-50 min, BCl 3 Flow rate 50~500 sccm, O 2 Flow rate 500~2000 sccm; oxidation advancement temperature 900~1050℃, O 2 The flow rate is 5000-30000 sccm, the advancement time is 30-80 min, and the thickness of the BSG layer is 30-70 nm.

[0071] S6, retain the mask layer of the isolation area design area, and laser secondary patterning groove to remove the mask layer of the phosphorus diffusion design area. The pre-designed phosphorus diffusion area is grooved. After removing the mask layer of the area, the phosphorus atoms can diffuse into the intrinsic polysilicon layer of the area during the subsequent phosphorus diffusion process, turning it into a phosphorus diffusion layer. The purpose of retaining the mask layer of the isolation area design area is to pave the way for the subsequent formation of a polished isolation area structure protruding from the back of the silicon wafer. In addition, the BSG layer formed by boron diffusion in S5 can also effectively block phosphorus atoms from entering the bottom boron diffusion layer during the phosphorus diffusion process.

[0072] In some specific implementation cases, picosecond laser is used for secondary patterning grooving, and the conditions are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

[0073] S7, alkaline cleaning removes the residual mask layer 4 in the slotted area in S6 to fully expose the intrinsic polysilicon layer 3 in the area. The deposited layers in the boron diffusion layer area and the bottom of the isolation area design area can be protected from being damaged by alkaline corrosion because the surfaces are protected by the BSG layer 6 and the mask layer 4 respectively. Figure 5 shown.

[0074] S8, phosphorus diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the phosphorus diffusion design area are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8. In the above phosphorus diffusion process, since the boron diffusion layer 5 and the surface of the intrinsic polysilicon layer 3 in the isolation area are protected by the BSG layer 6 and the mask layer 4 respectively, phosphorus atoms cannot diffuse into, and only the inner layer and the surface layer of the intrinsic polysilicon layer 3 exposed in the phosphorus diffusion design area are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8, as shown in FIG. Figure 6 shown.

[0075] In some specific implementation cases, the phosphorus diffusion conditions are: temperature 750-850°C, diffusion time 5-30 min, POCl 3 The nitrogen gas is carried at a flow rate of 500~1200 sccm.2 Flow rate 500~1000 sccm; oxidation advancement temperature 850~950℃, O 2 The flow rate is 1000-10000 sccm, the advancement time is 20-60 min. The thickness of the PSG layer is 30-70 nm.

[0076] S9, remove the coating on the front and side surfaces of the silicon wafer.

[0077] In some specific implementation cases, a chain machine (acid etching) is used to remove the boron diffusion layer and phosphorus diffusion layer and other coating layers on the front and side surfaces of the silicon wafer.

[0078] S10, wet cleaning and front texturing, a pyramid texturing surface 9 is formed on the front of the silicon wafer, and the residual mask layer 4, PSG layer 8 and BSG layer 6 are removed by pickling to form a polishing isolation area protruding from the back of the silicon wafer, such as Figure 7 shown.

[0079] In the above S10 process, since the plating layer on the front side of the silicon wafer has been completely removed and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface) can be formed during the texturing process; and for the entire area on the back side of the silicon wafer, there are PSG layer / mask layer / BSG layer respectively, which can prevent alkali corrosion from being destroyed. After cleaning and texturing, the mask layer, PSG layer and BSG layer remaining on the back side of the silicon wafer are removed by acid pickling to form a boron diffusion layer and a phosphorus diffusion layer with a cross-contact structure, as well as a polished isolation area protruding from the back side of the silicon wafer. The polished isolation area is an untransformed intrinsic polysilicon layer located between the boron diffusion layer and the phosphorus diffusion layer, which plays an insulating role, and the surface of the isolation area is a polished plane. Compared with the isolation area of ​​the conventional pyramid velvet surface, it can increase the reflection of incident light in the silicon substrate and improve the battery. I sc At the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF .

[0080] In some specific implementation cases, the silicon wafer after de-plating is placed in an alkaline texturing tank for wet cleaning and texturing integrated treatment, wherein the temperature is maintained at 75-85°C for 6-12 minutes.

[0081] S11, double-sided coating: after double-sided coating, a passivation anti-reflection layer 10 is generated on the front and back sides of the silicon wafer.

[0082] S12, screen printing, sintering to form electrode layer 11, light injection, to obtain TBC solar cell, such as Figure 8 Shown

[0083] Specific examples and comparative examples.

[0084] Example 1

[0085] A method for preparing a TBC solar cell with a polished isolation region structure comprises the following steps:

[0086] S1. Double-sided polishing of silicon wafer: Select N-type single crystal silicon wafer 1 cut by diamond wire, with a thickness of 150 μm and a size of 182.2 mm × 186.7 mm. Put the silicon wafer into the alkaline polishing tank, maintain the temperature at 75°C, and perform double-sided polishing for 6 min. The polishing thickness is 4 μm and the thinning amount is 0.42 g. Figure 1 shown.

[0087] S2, forming a tunnel oxide layer 2 (using LPCVD), an intrinsic polysilicon layer 3 (using LPCVD), and a mask layer 4 (using PECVD) on the back of the silicon wafer in sequence, such as Figure 2 As shown. Among them:

[0088] The deposition conditions of the tunnel oxide layer are: 2 The flow rate is 40000 sccm, the reaction temperature is 600℃, the time is 600 s, and the thickness of the tunneling oxide layer is about 3 nm.

[0089] The deposition conditions of the intrinsic polysilicon layer are: SiH 4 The flow rate was 920 sccm, the reaction temperature was 550°C, the reaction time was 3.3 h, the working pressure was 300 mTorr, and the thickness of the intrinsic polysilicon layer was about 290 nm.

[0090] The PECVD deposition conditions of the mask layer are: the reaction gas is N 2 O、SiH 4 , reaction temperature 440℃, N 2 The flow rate of O is 9500 sccm, and the flow rate of SiH 4 The flow rate is 2700 sccm, the power is 7000 W, the deposition time is 650 s, and the thickness of the mask layer is about 52 nm.

[0091] S3, laser one-time patterning grooving to remove the mask layer in the designed area of ​​the boron diffusion layer, the conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 25W, processing time 2.7s.

[0092] S4, alkaline cleaning to remove the residual mask layer 4 in the groove area so that the intrinsic polysilicon layer 3 in the area is fully exposed, such as Figure 3The specific steps are as follows: put the silicon wafer into an alkaline solution for cleaning at a temperature of 75°C. During the experiment, by adjusting different parameters such as cleaning time, and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the slotted area can be accurately removed, so that the bottom intrinsic polysilicon layer will not be removed too much during the alkaline cleaning process.

[0093] S5, boron diffusion, so that the inner layer and surface layer of the exposed intrinsic polysilicon layer are converted into a boron diffusion layer and a BSG layer respectively. The conditions for boron diffusion are: temperature 850℃, diffusion time 10 min, BCl 3 Flow rate 200 sccm, O 2 Flow rate 1200 sccm; oxidation advance temperature 950℃, O 2 The flow rate is 7000 sccm and the driving time is 30 min. The thickness of the BSG layer is about 45 nm. In the above boron diffusion process, the ungrooved area of ​​S3 can effectively block the boron atoms from entering the intrinsic polysilicon layer 3 due to the protection of the mask layer 4, and only the inner layer and the surface layer of the exposed intrinsic polysilicon layer 3 are converted into the boron diffusion layer 5 and the BSG layer 6, respectively. Figure 4 shown.

[0094] S6. The mask layer in the isolation area design area is retained, and the mask layer in the phosphorus diffusion area design area is removed by laser secondary patterning and grooving. The conditions are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0095] S7, alkaline cleaning removes the residual mask layer 4 in the slotted area in S6 to fully expose the intrinsic polysilicon layer 3 in the area. The deposited layers in the boron diffusion layer area and the bottom of the isolation area design area can be protected from being damaged by alkaline corrosion because the surfaces are protected by the BSG layer 6 and the mask layer 4 respectively. Figure 5 The specific steps are as follows: put the silicon wafer into an alkaline solution for cleaning at a temperature of 75°C. During the experiment, by adjusting different parameters such as cleaning time, and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the slotted area can be accurately removed, so that the bottom intrinsic polysilicon layer will not be removed too much during the alkaline cleaning process.

[0096] S8, phosphorus diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the phosphorus diffusion design area are converted into a phosphorus diffusion layer 7 and a PSG layer 8 respectively. The phosphorus diffusion conditions are: temperature 790℃, diffusion time 20 min, POCl 3 The nitrogen gas was carried at a flow rate of 1100 sccm. 2 Flow rate 700 sccm; oxidation advance temperature 890℃, O 2The flow rate is 3000 sccm and the advancement time is 40 min. The thickness of the PSG layer is about 42 nm. In the phosphorus diffusion process, since the boron diffusion layer 5 and the surface of the intrinsic polysilicon layer 3 in the isolation region are protected by the BSG layer 6 and the mask layer 4 respectively, phosphorus atoms cannot diffuse into them, and only the inner layer and the surface layer of the intrinsic polysilicon layer 3 exposed in the phosphorus diffusion design area are converted into the phosphorus diffusion layer 7 and the PSG layer 8 respectively. Figure 6 shown.

[0097] S9. Removal of coatings on the front and side surfaces of silicon wafers: Use a chain machine (acid etching) to remove coatings such as the boron diffusion layer and the phosphorus diffusion layer on the front and side surfaces of the silicon wafers.

[0098] S10, wet cleaning and front texturing, the silicon wafer is wet cleaned and front texturing is performed in alkaline, the temperature is maintained at 82°C, and the time is 7 minutes. A pyramid texture surface 9 is formed on the front side of the silicon wafer, and the residual mask layer 4, PSG layer 8 and BSG layer 6 are removed by pickling to form a polished isolation area protruding from the back side of the silicon wafer, such as Figure 7 shown.

[0099] In the above S10 process, since the plating layer on the front side of the silicon wafer has been completely removed and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface 9) can be formed during the texturing process; and for the entire area on the back side of the silicon wafer, there are PSG layer / mask layer / BSG layer respectively, which can prevent alkali corrosion from being destroyed. After cleaning and texturing, the mask layer, PSG layer and BSG layer remaining on the back side of the silicon wafer are removed by pickling to form a boron diffusion layer and a phosphorus diffusion layer with a cross-contact structure, as well as a polished isolation area protruding from the back side of the silicon wafer. The polished isolation area is an untransformed intrinsic polysilicon layer located between the boron diffusion layer and the phosphorus diffusion layer, which plays an insulating role, and the surface of the isolation area is a polished plane. Compared with the conventional isolation area with a pyramid velvet surface, it can increase the reflection of incident light in the silicon substrate and improve the battery. I sc At the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF .

[0100] S11, double-sided coating: after double-sided coating, a passivation anti-reflection layer 10 is generated on the front and back sides of the silicon wafer. Specifically, the following steps are used: firstly, AlO is deposited on the front and back sides of the processed silicon wafer by atomic layer deposition (ALD) method. x The film is composed of Al(CH 3 ) 3 It reacts with water vapor to form a layer with a thickness of 8 nm. The process temperature is controlled at 250°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x Film, front SiNx The thickness of the film is about 82 nm, and the refractive index is 2.1; the back SiN x The thickness of the film is about 90 nm, and the refractive index is 2.0; the reaction gas in the tubular cavity is SiH 4 NH 3 , operating pressure 1600 mTorr, power 12000 W, temperature 440°C, SiH 4 The gas flow rate was 980 sccm, NH 3 The gas flow rate was 8000 sccm, the silicon to nitrogen ratio was 1:5, and the deposition time was 10 min.

[0101] S12, screen printing the coated silicon wafer on the back to form a metal contact, then sintering at 770°C to form an Ag-Si ohmic contact (electrode layer 11), and finally performing light injection repair to obtain a TBC solar cell, such as Figure 8 shown.

[0102] Example 2

[0103] The difference between Example 2 and Example 1 is that the mask layer in S2 is formed by a one-step ultraviolet laser oxidation process: first, 2 A mask layer with a thickness of about 52 nm was generated under the conditions of a flow rate of 50 sccm, an ambient oxygen concentration of 26% (volume concentration), an ultraviolet laser wavelength of 355 nm, a power of 12 W, and a processing time of 10 s.

[0104] Example 3

[0105] The difference between Example 3 and Example 1 is that the mask layer in S2 is formed by two-step ultraviolet laser oxidation treatment:

[0106] First in O 2 A mask layer prototype with a thickness of about 52 nm was generated under the conditions of a flow rate of 50 sccm, an ambient oxygen concentration of 26% (volume concentration), a UV laser wavelength of 355 nm, a power of 12 W, and a processing time of 10 s.

[0107] Then in O 2 Under the conditions of flow rate 200 sccm, ambient oxygen concentration 60% (volume concentration), UV laser wavelength 266 nm, power 3W, and processing time 18 s, a denser mask layer is formed.

[0108] Comparative Example 1

[0109] Comparative Example 1 is compared with Example 1, except that in S6, the mask layer of the isolation region is removed together with the mask layer of the phosphorus diffusion design region by laser secondary patterning and grooving, and the isolation region surface of the TBC solar cell finally obtained has a pyramid velvet structure, such as Fig. 9 shown.

[0110] The preparation method of Comparative Example 1 specifically includes:

[0111] S1-S5 are the same as in Example 1.

[0112] S6. Laser secondary patterning and grooving to remove the mask layer in the phosphorus diffusion design area and the isolation area design area. The conditions are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0113] S7-S8 are the same as in Example 1.

[0114] S9, laser three-time patterning groove removal of the BSG layer and PSG layer at the junction of the boron diffusion layer and the phosphorus diffusion layer (i.e., the isolation area), and loosening the bottom deposition layers. The conditions are: laser wavelength of 532 nm, frequency of 600 KHz, marking speed of 45000 mm / s, power of 50 W, and processing time of 3 s.

[0115] S10 is the same as in Example 1.

[0116] S11. Place the silicon wafer that has been de-plated into an alkaline texturing tank for wet cleaning and integrated texturing of the laser slotted area on the back side. Maintain the temperature at 82°C for 7 minutes, lose 0.36 g in weight, and perform cleaning and texturing. Since the de-plating layer on the front side of the silicon wafer has been removed and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface) can be formed during the texturing process. In the isolation area on the back side of the silicon wafer, the alkaline solution can effectively corrode the bottom deposition layer, thereby exposing the back side of the silicon wafer in this area and forming a pyramid velvet surface during the texturing process. The subsequent acid cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer of the silicon wafer, such as Fig. 9 shown.

[0117] S12-S13 are the same as in Example 1.

[0118] Comparative Example 2 (using two intrinsic polysilicon layer deposition processes)

[0119] S1. Select N-type single crystal silicon wafers cut with diamond wire, with a thickness of 150 μm and a size of 182.2 mm×186.7 mm. Put the cut silicon wafers into an alkaline polishing tank, maintain the temperature at 75°C, and perform double-sided polishing for 6 min. The polishing thickness is 4 μm and the thinning amount is 0.42 g.

[0120] S2, then the tunnel oxide layer is first grown on the back surface of the polished silicon wafer by LPCVD. 2The gas flow rate is 40000 sccm, the temperature is 600℃, and the time is 600 s. The thickness of the grown tunnel oxide layer is about 3 nm. Then, an intrinsic polysilicon layer is grown again on the basis of the tunnel oxide layer, in which SiH 4 The gas flow rate is 920 sccm, the temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 290 nm.

[0121] S3, then the inner layer and the surface layer of the intrinsic polysilicon layer are transformed into a boron diffusion layer and a BSG layer respectively by a high-temperature boron diffusion method. The boron diffusion temperature is 850°C, the diffusion time is 10 min, and the BCl 3 The gas flow rate was 200 sccm, O 2 The gas flow rate is 1200 sccm, the oxidation push temperature is 950℃, and O 2 The flow rate was 7000 sccm, the push time was 30 min, and the thickness of the BSG layer was about 45 nm.

[0122] S4. Use picosecond laser to perform a patterned grooving of the BSG layer. The laser wavelength used is 532 nm, the frequency is 600 KHZ, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0123] S5. The silicon wafer after laser patterning and slotting is placed in an alkaline solution for cleaning at a temperature of 75°C for 360 s and a corrosion depth of 1.7 μm.

[0124] S6, then a tunnel oxide layer is grown on the back surface of the silicon wafer by LPCVD. 2 The gas flow rate is 30000 sccm, the temperature is 600℃, the time is 450 s, and the thickness of the grown tunnel oxide layer is about 2.5 nm. Then, an intrinsic polysilicon layer is grown again on the basis of the tunnel oxide layer, in which SiH 4 The gas flow rate is 920 sccm, the temperature is 550℃, the time is 1.5 h, the working pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 180 nm.

[0125] S7, the inner layer and the surface layer of the intrinsic polysilicon layer are transformed into a phosphorus diffusion layer and a PSG layer respectively by phosphorus diffusion method, the phosphorus diffusion temperature is 790℃, the diffusion time is 15 min, POCl 3 The nitrogen gas was carried at a flow rate of 1000 sccm. 2 The flow rate was 650 sccm, the oxidation push temperature was 890°C, and O 2 The flow rate was 3000 sccm, the push time was 20 min, and the thickness of the PSG layer was about 39 nm.

[0126] S8. Then, a picosecond laser is used to perform secondary patterning and grooving of the PSG layer to loosen the PSG layer corresponding to the bottom of the boron diffusion layer and the PSG layer at the junction of the p-region and the n-region. The laser wavelength is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 25 W, and the processing time is 2.7 s.

[0127] S9. Use a chain machine to remove the boron diffusion layer and phosphorus diffusion layer plated on the front and side surfaces of the silicon wafer.

[0128] S10, put the silicon wafer that has been deplated into the alkaline texturing tank for wet cleaning and texturing of the laser slotted area on the back side, maintain the temperature at 82°C for 7 minutes, lose 0.36 g, and perform cleaning and texturing. Since the silicon wafer has been deplated and there is no oxidation area on the front side, an effective light-trapping velvet surface can be formed during the texturing process; and in the laser patterning area on the back side, the alkaline solution can effectively corrode the bottom deposition layer to form an isolated insulating structure. The subsequent acid cleaning tank of the texturing tank can further remove the PSG layer and BSG layer remaining on the silicon wafer.

[0129] S11, using ALD deposition method to deposit AlO on the front and back sides of the processed silicon wafer x The film is composed of Al(CH 3 ) 3 It reacts with water vapor to form a layer with a thickness of 8 nm. The process temperature is controlled at 250°C. Then, SiN is deposited on both sides using a tubular PECVD device. x Film, front SiN x The thickness of the film is about 82 nm, and the refractive index is 2.1; the back SiN x The thickness of the film is about 90 nm, and the refractive index is 2.0; the reaction gas in the tubular cavity is SiH 4 NH 3 , operating pressure 1600 mTorr, power 12000 W, temperature 440°C, SiH 4 The gas flow rate was 980 sccm, NH 3 The gas flow rate was 8000 sccm, the silicon to nitrogen ratio was 1:5, and the deposition time was 10 min.

[0130] S12. The coated sheet is screen-printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact. Finally, the final TBC finished battery is obtained through light injection repair.

[0131] Performance comparison

[0132] Table 1: Electrical performance data of different batteries

[0133]

[0134] From the data in Table 1, we can see that:

[0135] (1) Since the TBC solar cells prepared in Examples 1-3 all have a polished isolation region structure, compared with the TBC solar cell finally obtained in Comparative Example 1 having a pyramid velvet structure on the isolation region surface, the reflection of the incident light in the silicon substrate can be increased, thereby improving the cell performance. I sc At the same time, since the initial isolation area is protected by the mask layer and is not damaged by subsequent wet etching, the height difference between the isolation area and the boron / phosphorus diffusion layer can be reduced, which is beneficial to the lateral transmission of carriers inside the silicon substrate and improves FF .

[0136] (2) Since Examples 1-3 all adopt a one-step deposition process for the intrinsic polysilicon layer, while Comparative Example 2 adopts a conventional two-step deposition process for the intrinsic polysilicon layer, the poly-Si parasitic absorption of the cell is lower because it has a higher short-circuit current density ( J sc ).

[0137] (3) The difference between Examples 1-3 is that the preparation methods of the mask layer are different. Specifically: Example 1 adopts the more traditional PECVD process, Example 2 adopts a one-step ultraviolet laser oxidation process, and Example 3 adopts a two-step differentiated ultraviolet laser oxidation process. The results show that the performance of the final product obtained by preparing the mask layer using the PECVD process is not as good as that of the ultraviolet laser oxidation process. At the same time, the oxidation barrier layer formed by the one-step ultraviolet laser oxidation process in Example 2 is often not as dense as expected, which easily increases the risk of boron atoms and phosphorus atoms diffusing into the bottom intrinsic polysilicon layer during subsequent boron diffusion and phosphorus diffusion, thereby causing battery performance degradation or leakage. Example 3 adopts a two-step differentiated ultraviolet laser oxidation process, which can make the oxidation barrier layer denser with almost no increase in thickness, so it can more effectively block the subsequent inward expansion of boron and phosphorus atoms, thereby improving battery performance.

[0138] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0139] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a TBC solar cell having a polished isolation region structure, characterized in that include: S1, double-sided polishing of silicon wafer; S2, forming a tunnel oxide layer, an intrinsic polysilicon layer, and a mask layer in sequence on the back side from one side of the silicon wafer; S3, groove removal of the mask layer in the boron diffusion design area; S4, alkali cleaning; S5, boron diffusion, so that the intrinsic polysilicon layer in the boron diffusion design area is transformed into a boron diffusion layer and a BSG layer in sequence from the tunnel oxide layer side; S6, retaining the mask layer in the isolation area design region, and removing the mask layer in the phosphorus diffusion area design region by groove removal; S7, alkali cleaning; S8, phosphorus diffusion, so that the intrinsic polysilicon layer in the phosphorus diffusion design area is transformed into a phosphorus diffusion layer and a PSG layer in sequence from the tunnel oxide layer side; S9, removing the coating; S10, wet cleaning and front texturing, acid washing to remove the residual mask layer, PSG layer and BSG layer, and form a polishing isolation area protruding from the back of the silicon wafer; S11, double-sided coating; S12, screen printing, sintering, light injection.

2. The preparation method according to claim 1, characterized in that: In S2, the mask layer is formed by PECVD, and the conditions are: the reaction gases are N2O and SiH4, the reaction temperature is 400~500°C, the flow rate of N2O is 9000~11000 sccm, the flow rate of SiH4 is 1000~5000 sccm, the power is 3000~20000 W, the deposition time is 100~3000 s, and the thickness of the mask layer is 30~300 nm.

3. The preparation method according to claim 1, characterized in that: In S2, the mask layer is formed by ultraviolet laser oxidation treatment: First, a mask layer prototype is generated under the conditions of an oxygen concentration of 20-40% and an ultraviolet laser wavelength of 300-400 nm; Then, a denser mask layer is formed under the conditions of oxygen concentration of 50~90% and ultraviolet laser wavelength of 200~300 nm.

4. The preparation method according to claim 3, characterized in that: In S2, the conditions of the ultraviolet oxidation laser treatment are specifically: First, a mask layer prototype is generated under the conditions of an O2 flow rate of 10-100 sccm, an ambient oxygen concentration of 20-40%, an ultraviolet laser wavelength of 300-400 nm, a power of 10-500 W, and a processing time of 1-30 s; Then, under the conditions of O2 flow rate of 100-500 sccm, ambient oxygen concentration of 50-90%, ultraviolet laser wavelength of 200-300 nm, power of 2-50 W, and processing time of 1-30 s, a denser mask layer is formed; the thickness of the mask layer is 30-300 nm.

5. The preparation method according to claim 1, characterized in that: In S2, the deposition conditions of the tunnel oxide layer are: O2 flow rate 10000~80000 sccm, reaction temperature 400~800°C, time 200~1000 s, and tunnel oxide layer thickness 2~10 nm.

6. The preparation method according to claim 1, characterized in that: In S2, the deposition conditions of the intrinsic polysilicon layer are: SiH4 flow rate 300~2000 sccm, reaction temperature 500~700°C, time 2~4 h, working gas pressure 100~500 mTorr, and intrinsic polysilicon layer thickness 100~300 nm.

7. The preparation method according to claim 1, characterized in that: In S3, laser patterning is used to remove the mask layer in the boron diffusion design area.

8. The preparation method according to claim 1, characterized in that: In S5, the boron diffusion conditions are: temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min, generating a BSG layer with a thickness of 30-70 nm.

9. The preparation method according to claim 1, characterized in that: In S6, laser patterning is used to remove the mask layer in the phosphorus diffusion design area.

10. The preparation method according to claim 1, characterized in that: In S8, the conditions for phosphorus diffusion are: temperature 750-850°C, diffusion time 5-30 min, POCl3 is carried by nitrogen with a flow rate of 500-1200 sccm, and O2 flow rate 500-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 1000-10000 sccm, advancement time 20-60 min, generating a PSG layer with a thickness of 30-70 nm.

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