Computer system, signal processing method, device, medium and product

Abstract

The present invention provides a computer system, a signal processing method, a device, a medium and a product, and relates to the field of computer technology. The system includes a target main control board, a pull-up circuit, a first logic controller, an image processing module and a switching module; the pull-up circuit is connected to a target general input / output port in the target main control board, and the pull-up circuit is used to generate a corresponding port signal according to the port state of the target general input / output port; the first logic controller is connected to the target main control board, the pull-up circuit, the image processing module and the switching module, and the first logic controller is used to obtain the platform type corresponding to the target main control board according to the port signal transmitted by the pull-up circuit, and perform corresponding reset control operations on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board. The present invention realizes the compatibility requirements of different chip combinations while reducing development costs.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a computer system, a signal processing method, a device, a medium and a product. Background Art

[0002] With the rapid development of cloud computing, big data and artificial intelligence technologies, computer systems, as the core supporting platform of these technologies, have increasing requirements for performance, stability and compatibility. When building computer systems, users often choose central processing units (CPUs), high-speed serial computer expansion bus switches (PCIE Switches) and graphics processing units (GPUs) from different manufacturers to flexibly match them based on diverse application scenarios and cost-effectiveness considerations to achieve efficient signal processing.

[0003] However, different CPU manufacturers, PCIE Switch chip manufacturers and GPU manufacturers have design differences in the initialization efficiency, initialization process and global reset function of the PCIE controller on the basis of following the high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) protocol specifications. When these chips or components from different manufacturers are combined together, compatibility issues may occur.

[0004] For downstream computer system manufacturers, this compatibility issue increases the complexity and uncertainty of product development. In order to solve these problems, some manufacturers have to use multiple sets of system logic control boards or customized firmware to meet the compatibility requirements of different chip combinations. However, this one-to-one development and configuration for chips or components from different manufacturers increases development costs. Summary of the invention

[0005] The present invention provides a computer system, a signal processing method, a device, a medium and a product, which are used to solve the defect in the prior art that multiple system boards or customized firmware are configured to meet the compatibility requirements of different chip combinations, resulting in increased development costs, and achieve the compatibility requirements of different chip combinations while reducing development costs.

[0006] The present invention provides a computer system, comprising:

[0007] Target main control board;

[0008] A pull-up circuit, the pull-up circuit being connected to a target general input / output port in the target main control board, the pull-up circuit being used to generate a corresponding port signal according to a port state of the target general input / output port;

[0009] A first logic controller, an image processing module and a switching module, wherein the first logic controller is connected to the target main control board, the pull-up circuit, the image processing module and the switching module, and the first logic controller is used to receive the port signal transmitted by the pull-up circuit, obtain the platform type corresponding to the target main control board according to the port signal, and perform corresponding reset control operations on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board.

[0010] According to the computer system provided by the present invention, the first logic controller is also used for:

[0011] Determining whether the platform type is a first platform type;

[0012] When the platform type is the first platform type, acquiring a current reset task to be executed by the first logic controller according to level change information of the target reset signal;

[0013] According to the timing signal change information of the current reset task, corresponding reset control operations are performed on the image processing module and the switching module.

[0014] According to the computer system provided by the present invention, the first logic controller is also used for:

[0015] Determine whether a falling edge of the target reset signal is detected according to the level change information of the target reset signal, and obtain a first determination result;

[0016] According to the first judgment result, a current reset task that the first logic controller needs to execute is obtained.

[0017] According to the computer system provided by the present invention, the first logic controller is also used for:

[0018] In a case where it is known according to the first judgment result that a falling edge of the target reset signal is detected, determining that the current reset task is a cold reset task or a hot reset task;

[0019] When it is known according to the first judgment result that the falling edge of the target reset signal is not detected, it is determined that the current reset task is an AC / DC power cycle task.

[0020] According to the computer system provided by the present invention, the first logic controller is also used for:

[0021] When it is known that the current reset task is a cold reset task or a hot reset task, acquiring a first target delay time according to the timing signal change information of the cold reset task or the hot reset task;

[0022] After delaying for the first target delay time, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, and the image processing module and the switching module are released from reset according to the reset signal after the pull-up process.

[0023] According to the computer system provided by the present invention, the first logic controller is also used for:

[0024] In the case where it is known that the current reset task is an AC / DC power cycle task, determining whether a target indication signal of the last power supply is detected to obtain a second determination result; the target indication signal is used to indicate that the power supply is in a normal operating state;

[0025] According to the second judgment result and the timing signal change information of the AC / DC power cycle task, corresponding reset control operations are performed on the image processing module and the switching module.

[0026] According to the computer system provided by the present invention, the first logic controller is also used for:

[0027] If it is determined according to the second determination result that the target indication signal of the last power source is not detected, the process returns to the step of determining whether the target indication signal of the last power source is detected until it is determined that the target indication signal of the last power source is detected.

[0028] According to the computer system provided by the present invention, the first logic controller is also used for:

[0029] When it is known according to the second judgment result that the target indication signal of the last power source is detected, obtaining the second target delay time according to the timing signal change information of the AC / DC power cycle task;

[0030] After delaying for the second target delay time, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, and the image processing module and the switching module are released from the reset operation according to the reset signal after the pull-up processing.

[0031] According to the computer system provided by the present invention, the switching module is connected to the central processing unit in the target main control board and the image processing module;

[0032] The switching module is used to perform high-speed serial computer expansion bus link training with the central processing unit in the target main control board and the image processing module when the corresponding reset operations of the image processing module and the switching module are completed.

[0033] According to the computer system provided by the present invention, the first logic controller is also used for:

[0034] When it is determined that the high-speed serial computer expansion bus link training between the switching module and the central processing unit in the target main control board and the image processing module is completed, return to the step of determining whether the platform type is the first platform type and execute the next reset task.

[0035] According to the computer system provided by the present invention, the first logic controller is further used for:

[0036] Matching the level corresponding to the port signal with the preset level corresponding to the universal input and output port in the main control board of each preset platform type;

[0037] According to the matching result, a preset level matching the level corresponding to the port signal is obtained;

[0038] According to the preset platform type corresponding to the matched preset electrical level, the platform type corresponding to the target main control board is obtained.

[0039] According to the computer system provided by the present invention, the pull-up circuit includes a pull-up resistor and a pull-up power supply;

[0040] A first end of the pull-up resistor is connected to the pull-up power supply, a second end of the pull-up resistor is connected to the target general input / output port, and a third end of the pull-up resistor is connected to the first logic controller.

[0041] According to the computer system provided by the present invention, when the target main control board is of the first platform type, the target main control board includes a plurality of central processing units and a second logic controller;

[0042] The plurality of central processing units are connected via an interconnection interface;

[0043] At least one of the central processing units is connected to the second logic controller, and the second logic controller is connected to the first logic controller.

[0044] According to the computer system provided by the present invention, when the platform type is the first platform type, the target reset signal is a global reset signal issued by at least one central processing unit of the target main control board through the second logic controller of the target main control board.

[0045] According to the computer system provided by the present invention, when the target main control board is of the second platform type, the target main control board includes a plurality of central processing units, a south bridge chip and a second logic controller;

[0046] The plurality of central processing units are connected via an interconnection interface;

[0047] At least one of the central processing units is connected to the south bridge chip, the south bridge chip is connected to the second logic controller, and the second logic controller is connected to the first logic controller.

[0048] According to the computer system provided by the present invention, when the platform type is the second platform type, the target reset signal is a global reset signal issued by at least one central processing unit of the target main control board through the south bridge chip and the second logic controller in sequence.

[0049] The present invention further provides a signal processing method, which is applied to any of the above-mentioned computer systems, and comprises:

[0050] According to the port signal transmitted by the pull-up circuit, the platform type corresponding to the target main control board is obtained; the port signal is generated by the pull-up circuit according to the port state of the target general input and output port in the target main control board;

[0051] According to the platform type and the target reset signal transmitted by the target main control board, corresponding reset control operations are performed on the image processing module and the switching module.

[0052] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned signal processing methods when executing the program.

[0053] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and the computer program, when executed by a processor, implements any of the signal processing methods described above.

[0054] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the signal processing method described above is implemented.

[0055] The computer system, signal processing method, device, medium and product provided by the present invention integrate a pull-up circuit with a first logic controller, an image processing module and a switching module, and use the pull-up circuit to monitor the port status of the universal input and output port of the target main control board in real time, generate and transmit the corresponding port signal to the first logic controller, so that the first logic controller can quickly identify the platform type of the target main control board according to the signal, and flexibly adjust the reset control operation of the image processing module and the switching module in combination with the target reset signal from the target main control board, thereby achieving the compatibility requirements of the main control board combination of multiple platform types through a set of general architecture, so as to eliminate the PCIE compatibility problem of CPUs of different platforms with PCIE Switch chips of different platforms and GPU modules of different manufacturers, which not only simplifies the compatibility processing process for diversified chip combinations, avoids the high development cost of traditional multiple system logic control boards or customized firmware, but also significantly improves the stability and reliability of the computer system under different hardware combinations, thereby effectively reducing the complexity and uncertainty of product development, and providing downstream computer system manufacturers with a more efficient and economical solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0057] Figure 1 It is one of the structural schematic diagrams of the computer system provided by the present invention.

[0058] Figure 2 This is the second structural diagram of the computer system provided by the present invention.

[0059] Figure 3 This is the third structural diagram of the computer system provided by the present invention.

[0060] Figure 4 It is a timing signal variation diagram corresponding to the AC / DC power supply cycle task provided by the present invention.

[0061] Figure 5 This is a timing signal change diagram corresponding to the hot reset task provided by the present invention.

[0062] Figure 6 This is a timing signal change diagram corresponding to the cold reset task provided by the present invention.

[0063] Figure 7 It is a flow chart of the signal processing steps provided by the present invention.

[0064] Figure 8 It is a flowchart of the signal processing method provided by the present invention.

[0065] Fig. 9 It is a structural schematic diagram of the electronic device provided by the present invention.

[0066] Reference numerals:

[0067] 10: switch board; 11: first logic controller; 12: image processing module; 13: switch module; 20: pull-up circuit; 30: target main control board. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] The computer system provided in the embodiment of the present application may be an artificial intelligence server, a data center device, etc. This embodiment does not specifically limit this. The following description will be given using the computer system being an artificial intelligence server as an example.

[0070] In recent years, as an important hardware foundation for the development of artificial intelligence technology, artificial intelligence (AI) servers have the following development trends: 1. Market demand growth: With the widespread application of artificial intelligence technology, especially in the fields of natural language processing, image recognition, and autonomous driving, the market demand for AI servers continues to grow. Since AI servers have powerful computing and storage capabilities, they can process massive data and complex algorithms. In addition, AI servers use efficient heat dissipation design and energy-saving technology, which can effectively ensure stable operation under high load and reduce energy consumption. In addition, AI servers also support a variety of AI frameworks and algorithm libraries, which facilitates users to quickly build AI applications. Therefore, the market size of AI servers continues to expand, with a high annual compound growth rate. 2. Technological progress: AI servers need to process massive data and complex algorithms, so they have high requirements for computing power, storage capacity, and energy efficiency. With the advancement of chip technology, heterogeneous computing and other technologies, the performance of AI servers has been continuously improved. 3. Industrial chain development: The upstream of the AI ​​server industry industrial chain includes chips, printed circuit boards (PCBs), etc., the midstream includes server brands and original equipment manufacturers (OEMs) or original design manufacturers (ODMs), and the downstream includes Internet manufacturers, cloud service providers, etc. The improvement and development of the industrial chain will promote the maturity of the AI ​​server market. 4. Application expansion: The application scenarios of AI servers have expanded from centralized AI services to edge AI services, and the development of terminal devices such as AI personal computers (PCs) driven by AI servers will bring new growth points to the AI ​​server market. 5. In terms of market participant competition, there are many AI server design manufacturers and equipment manufacturers, which have significant advantages in market share and technological innovation. They can promote the development of the market by continuously launching high-performance AI chips and system integration solutions. 6. Green computing: With the popularization of the concept of sustainable development, AI servers pay more and more attention to energy efficiency in design. By optimizing algorithms and hardware design, energy consumption can be reduced and resource utilization efficiency can be improved, thereby promoting the development of green computing.

[0071] Based on the above market background and development trend, when building a computer system, users often choose CPUs from different manufacturers with PCIE Switch chips from different manufacturers based on diverse application scenarios and cost-effectiveness considerations, and then mount GPU configurations from different manufacturers under the PCIE Switch chips. For example, choose CPUs from Intel / AMD / NVDIA with PCIE Switch chips from Broadcom / Microchip and other suppliers, and then mount GPU configurations from NVDIA and other platforms under the PCIE Switch chips.

[0072] However, different CPU manufacturers or PCIE Switch chip manufacturers or GPU manufacturers, under the premise of following the PCIE protocol specifications, have different PCIE Switch chips from different manufacturers running under different PCIE design topologies, combined with the differences in the characteristics of the PCIE controllers of different upstream CPU platforms and the time differences of the global Reset issued by different CPU platforms or the differences in the CPU's own initialization process. As a result, the initialization efficiency, initialization process, and global reset (or Reset) functions of the PCIE controllers of different chip manufacturers may differ.

[0073] Therefore, when chips or components from different manufacturers are paired together, there will be compatibility issues such as card loss, loss of PCIeSwitch key components, and PCIE bus bandwidth reduction. This problem poses certain challenges to downstream server system solution manufacturers. Furthermore, in order to solve these problems, some manufacturers have to adopt multiple sets of system logic control boards, such as complex programmable logic devices (CPLD), etc., or customized firmware (Firmware, FW), such as basic input and output system firmware (BIOS) FW, etc., to meet the compatibility requirements of different chip combinations. However, this one-to-one development and configuration method for chips or components from different manufacturers increases development costs. For example, in order to solve compatibility issues such as card loss, switch loss, and PCIE bus bandwidth reduction caused by two different platform CPUs paired with the same manufacturer's PCIE Switch and GPU, two sets of PCIE switch boards are needed to adapt to different platform CPUs, so as to adopt differentiated processing methods for the global reset sent by different platform CPUs, thereby increasing the development and design costs of the server.

[0074] In this regard, in order to solve the compatibility problems and high development and design costs existing in the relevant technologies, the embodiments of the present application provide a computer system that supports homologous and non-homologous sources. The system only needs to use a set of general architecture designs combined with corresponding logic code designs to eliminate the compatibility issues of different CPU platforms with different PCIE Switch chips and GPU components. In this way, compatibility issues such as card loss, Switch loss, and PCIE bus bandwidth reduction can be solved at low cost through a simple and flexible architecture.

[0075] Figure 1 It is one of the structural diagrams of the computer system provided by the present invention; Figure 1 As shown, the system includes: a pull-up circuit 20, a first logic controller 11, an image processing module 12, a switching module 13 and a target main control board 30. Among them, the first logic controller 11, the image processing module 12, and the switching module 13 can be configured in a switching board 10, and the switching board 10 can be a PCIE switching board (or PCIE Switch board).

[0076] Among them, the pull-up circuit 20 can be implemented by selecting a low-power logic gate circuit or a dedicated interface chip, which is used to output different port signals according to the port status of the target universal input and output ports of the main control boards of different platform types, so as to subsequently identify the platform type information of different main control boards.

[0077] The first logic controller here is a controller that can be used to implement various logic controls, such as a field programmable gate array (FPGA), etc. This embodiment does not specifically limit this, and the following description is made by taking the first logic controller as an FPGA as an example.

[0078] The image processing module 12 here includes a plurality of image processors, for example, may include a total of 10 image processors including GPU0 to GPU9.

[0079] The switching module 13 here includes multiple PCIE switching chips (or called switching chips, or called PCIE Switch chips), such as including PCIE switching chip A (or called PCIE Switch chip A) and PCIE switching chip B (or called PCIE Switch chip B).

[0080] The pull-up circuit is connected to the target general input / output port in the target main control board, and the pull-up circuit is used to generate a corresponding port signal according to the port state of the target general input / output port.

[0081] Optionally, the input end of the pull-up circuit 20 is connected to the target general input / output port of the target CPU (such as CPU0) in the target main control board 30, and the output end of the pull-up circuit 20 is connected to the first logic controller 11. The specific connection method can be adaptively determined according to the topological structure of the pull-up circuit.

[0082] Exemplarily, in some embodiments, the pull-up circuit 20 includes a pull-up resistor and a pull-up power supply; a first end of the pull-up resistor is connected to the pull-up power supply, a second end of the pull-up resistor is connected to the target general input / output port, and a third end of the pull-up resistor is connected to the first logic controller.

[0083] like Figure 1 As shown, the pull-up circuit includes a pull-up resistor and a pull-up power supply (or Resistor); in some embodiments, the pull-up power supply here can be a 3.3 volt power supply (or P3V3_STBY). Among them, the first end of the pull-up resistor is connected to the pull-up power supply, the second end of the pull-up resistor is connected to the target general-purpose input / output port of the target CPU (such as CPU0) in the target main control board, and the third end of the pull-up resistor is connected to the input pin of the first logic controller to provide a stable reference voltage for the first logic controller, which helps to ensure the integrity and reliability of the signal. And when the first logic controller receives the port status information from the target general-purpose input / output port (General-Purpose Input / Output, GPIO) through the pull-up resistor and outputs the corresponding port signal, the first logic controller can accurately identify the platform type of the target main control board according to the resistor voltage division principle, so as to provide a basis for the subsequent execution of different signal processing logics for different platforms.

[0084] The default port state of the target GPIO in the target main control board here is different from the default port state of the GPIO in the main control board of other platform types. For example, the default port state of the GPIO in the CPU of the main control board of a certain platform type is a pull-down state, and the default port state of the GPIO in the CPU of the main control board of another platform type is a pull-up state or a floating state.

[0085] Optionally, the pull-up circuit can obtain the port status of the target GPIO of the target main control board, and generate a corresponding port signal (or CPU_Detect signal) based on the port status of the target GPIO, and transmit the generated port signal to the first logic controller via the connection path between the pull-up circuit and the first logic controller, so that the first logic controller can identify the platform type to which the target main control board belongs based on the corresponding port signal, and call the logic code corresponding to the platform type to implement the corresponding logic signal processing, thereby achieving a set of universal architecture to eliminate the compatibility issues of different CPU platforms with different PCIE Switch chips and GPU components, thereby reducing development costs.

[0086] The first logic controller is connected to the target main control board, the pull-up circuit, the image processing module and the switching module. The first logic controller is used to receive the port signal transmitted by the pull-up circuit, obtain the platform type corresponding to the target main control board according to the port signal, and perform corresponding reset control operations on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board.

[0087] Optionally, the target main control board may include multiple CPUs, such as CPU0 and CPU1.

[0088] The first logic controller is respectively connected to multiple image processors in the image processing module and at least one switching chip in the switching module; each image processor is correspondingly connected to each switching chip; each switching chip is correspondingly connected to each central processing unit in the target main control board.

[0089] For example, Figure 1As shown, the first logic controller is FPGA1. When the image processing module includes GPU0~GPU9, the switching module includes PCIE switching chip A and PCIE switching chip B, and the target main control board includes CPU0 and CPU1, FPGA1 can be connected to GPU0~GPU9, a total of 10 image processors, respectively, and FPGA1 can be connected to control port S6 in PCIE switching chip A; GPU0 can be connected to control port S1 in PCIE switching chip A through a PCIE link, GPU1 can be connected to control port S2 in PCIE switching chip A through a PCIE link, GPU2 can be connected to control port S5 in PCIE switching chip A through a PCIE link, and GPU3 can be connected to control port S7 in PCIE switching chip A through a PCIE link. GPU4 can be connected to the control port S8 in PCIE switch chip A through a PCIE link, GPU5 can be connected to the control port S1 in PCIE switch chip B through a PCIE link, GPU6 can be connected to the control port S5 in PCIE switch chip B through a PCIE link, GPU7 can be connected to the control port S6 in PCIE switch chip B through a PCIE link, GPU8 can be connected to the control port S7 in PCIE switch chip B through a PCIE link, GPU9 can be connected to the control port S8 in PCIE switch chip B through a PCIE link, control port S0 in PCIE switch chip A can be connected to CPU0 correspondingly through a PCIE link, and control port S0 in PCIE switch chip B can be connected to CPU1 correspondingly through a PCIE link.

[0090] It should be noted that, due to different requirements of customers for chassis size and the number of GPUs, the number of PCIE switching chips in the switching module can be set according to specific requirements, such as 2 PCIE switching chips or 4 PCIE switching chips; similarly, the number of GPUs in the image processing module can also be set according to specific requirements, such as 10 GPUs, which is also a larger number of GPUs; in addition, due to the difference in chassis size, the shape of the PCIE switching chip will be different. Due to the requirements of PCIE routing and signal integrity (SI) parameters during PCB design, the resource allocation of S0 / S1 / S5 / S6 / S7 / S8 of each PCIE switching chip, that is, the design topology may be different. For example, the control port S0 of PCIE switching chip A is connected to CPU0, and the control port S0 of PCIE switching chip B may be connected to CPU1, that is, the design topology of 2 or 4 PCIE switching chips on the same PCIE switching board may be inconsistent. In order to reduce manufacturing costs, the FW of 2 or 4 PCIE switching chips on the same PCIE switching board can be configured in the same way.

[0091] Optionally, during the signal processing, when the first logic controller receives the port signal transmitted by the pull-up circuit, it may identify the corresponding platform type of the target main control board connected to the uplink of the switching board according to the port signal.

[0092] The corresponding platform type of the target main control board here can be realized by the first logic controller performing logical judgment according to the port signal, or it can be identified by inputting the port signal into a recognition model that has been pre-trained with a sample port signal as a sample and a sample platform category label as a label. This embodiment does not make any specific limitations on this.

[0093] For example, in some embodiments, the first logic controller may specifically perform the following steps to identify the platform type:

[0094] Matching the level corresponding to the port signal with the preset level corresponding to the universal input and output port in the main control board of each preset platform type;

[0095] According to the matching result, a preset level matching the level corresponding to the port signal is obtained;

[0096] According to the preset platform type corresponding to the matched preset electrical level, the platform type corresponding to the target main control board is obtained.

[0097] Optionally, the first logic controller may perform the following steps to identify the platform type corresponding to the target main control board:

[0098] The first logic controller can read the port signal sent by the pull-up circuit and determine the level corresponding to the port signal. Then, the correspondence table of preset levels corresponding to the general input and output ports in the main control boards of different platform types is traversed, and the level corresponding to the port signal is compared with the preset level corresponding to the general input and output ports in the main control boards of each preset platform type in the correspondence table to find a match. Once a matching level is found, the platform type of the target main control board can be determined according to the preset platform type corresponding to the matching level, thereby efficiently and accurately identifying the platform type of the target main control board connected to the uplink of the switching board, thereby facilitating the improvement of the compatibility and flexible configuration of the main control boards of different platform types, so as to further improve the scalability and ease of use of the computer system.

[0099] For example, it is assumed that the preset level level corresponding to the universal input / output port in the main control board of the first platform type is the first level level (such as a high level), and the preset level level corresponding to the universal input / output port in the main control board of the second platform type is the second level level (such as a low level). Therefore, when the CPU_Detect signal obtained from the pull-up circuit is a high level signal (or H signal), it is determined that the target main control board connected to the upstream of the switching board is the first platform type, and when the CPU_Detect signal obtained from the pull-up circuit is a low level signal (or L signal), it is determined that the target main control board connected to the upstream of the switching board is the second platform type, so that when the switching board is connected to the main control boards of different platform types, the high and low levels of the CPU_Detect transmitted by the pull-up circuit are different, and the platform type of the main control board connected to the upstream of the sensing switching board can be accurately identified.

[0100] Optionally, after acquiring the corresponding platform type of the target main control board connected upstream to the switch board, the first logic controller may acquire the target reset signal transmitted by the target main control board in real time.

[0101] The target reset signal here is transmitted from the target main control board to the first logic controller according to the transmission path corresponding to the topological structure of its platform type.

[0102] Figure 2 This is the second structural diagram of the computer system provided by the present invention.

[0103] For example, Figure 2As shown, in the case where the target main control board is of the first platform type, the target main control board includes multiple central processing units and a second logic controller; the multiple central processing units are connected through an interconnection interface; at least one of the central processing units is connected to the second logic controller, and the second logic controller is connected to the first logic controller; the target general input and output port in at least one of the central processing units is connected to the pull-up circuit. For example, assuming that under the first platform type, the CPUs included in the target main control board are CPU0 and CPU1, and the second logic controller included in the target main control board is FPGA0; wherein CPU0 and CPU1 are interconnected through an interconnection interface, such as a 10 Gigabit Media Independent Interface (XGMII), to meet the data interaction requirements between two different CPUs. CPU0 is connected to the second logic controller (i.e., FPGA0). The second logic controller is connected to the first logic controller. Correspondingly, in the case where the platform type is the first platform type, the target reset signal is a global reset signal issued by at least one of the central processing units of the target main control board through the second logic controller of the target main control board, that is, in the reset task processing flow, the target main control board under the first platform type first sends a global reset signal to the second logic controller through the target central processing unit (such as CPU0), and then the second logic controller sends the global reset signal to the first logic controller, thereby realizing the transmission of the target reset signal.

[0104] Figure 3 This is the third structural diagram of the computer system provided by the present invention.

[0105] For example, Figure 3As shown, in the case where the target main control board is of the second platform type, the target main control board includes multiple central processing units, a south bridge chip and a second logic controller; the multiple central processing units are connected through an interconnection interface; at least one central processing unit is connected to the south bridge chip, the south bridge chip is connected to the second logic controller, and the second logic controller is connected to the first logic controller; the target general input and output port in at least one central processing unit is connected to the pull-up circuit. For example, assuming that under the second platform type, the CPUs included in the target main control board are CPU0 and CPU1, and the second logic controller included in the target main control board is FPGA0, wherein CPU0 and CPU1 are interconnected through an interconnection interface, such as a high-speed bus of Ultra Path Interconnect (UPI), to meet the data interaction requirements between two different CPUs. CPU0 is connected to the south bridge chip, such as the platform path controller (Platform Controller Hub, PCH) through the direct media interface (Direct Media Interface, DMI) bus; the south bridge chip is connected to the second logic controller (i.e., FPGA0), and the second logic controller is connected to the first logic controller. Correspondingly, in the case where the platform type is the second platform type, the target reset signal is a global reset signal issued by at least one of the central processing units of the target main control board through the south bridge chip and the second logic controller in sequence, that is, in the reset task processing flow, the target main control board under the second platform type first sends a global reset signal to the south bridge chip through the target central processing unit (such as CPU0), and the south bridge chip then sends the global reset signal to the second logic controller, and then the second logic controller sends the global reset signal to the first logic controller, thereby realizing the transmission of the target reset signal.

[0106] Optionally, after acquiring the target reset signal transmitted by the target main control board, the first logic controller can call the corresponding signal processing logic according to the target reset signal transmitted by the target main control board and the platform type to perform corresponding reset control operations on the image processing module and the switching module.

[0107] The system provided in this embodiment integrates a pull-up circuit with a first logic controller, an image processing module and a switching module, and uses the pull-up circuit to monitor the port status of the universal input and output port of the target main control board in real time, and generates and transmits a corresponding port signal to the first logic controller, so that the first logic controller can quickly identify the platform type of the target main control board according to the signal, and flexibly adjust the reset control operation of the image processing module and the switching module in combination with the target reset signal from the target main control board, thereby achieving the compatibility requirements of the main control board combination of multiple platform types through a set of general architecture, so as to eliminate the PCIE compatibility problem of CPUs of different platforms with PCIE Switch chips of different platforms and GPU modules of different manufacturers, which not only simplifies the compatibility processing process for diversified chip combinations, avoids the high development cost of traditional multiple system logic control boards or customized firmware, but also significantly improves the stability and reliability of computer systems under different hardware combinations, thereby effectively reducing the complexity and uncertainty of product development, and providing downstream computer system manufacturers with a more efficient and economical solution.

[0108] In order to more clearly describe the processing logic of the interactive board when executing different reset tasks below, the timing signal change diagram corresponding to different reset tasks is expanded here.

[0109] Figure 4 is a timing signal change diagram corresponding to the AC / DC power cycle task provided by the present invention; Figure 4 As shown, for the AC / DC power cycle task (or AC / DC Cycle task), after the power supply (or Power) is powered on (that is, the power signal has a rising edge), a 100Mhz clock will appear next. After the 100Mhz clock is stable, the reset signal (or Reset signal) is pulled high, that is, from the rising edge of the power signal to the rising edge of the Reset signal is the power-on action performed by the hardware when the AC / DC Cycle task is executed for the first time; then the shutdown action is executed, that is, starting from the falling edge of the Reset signal, then the 100Mhz clock is pulled low and has no effect, and then the falling edge of the power signal appears; after a period of time, the rising edge of the power signal appears, and from the rising edge of the power signal to the rising edge of the Reset signal is the hardware performing the power-on action again, that is, the cold restart action, and thus a cycle of the AC / DC power reset task is completed.

[0110] Figure 5 This is a timing signal change diagram corresponding to the hot reset task provided by the present invention. Figure 5 As shown in the figure, for the hot reset task (also called Warm Reset task), it is the same as Figure 4The comparison of the timing signal change diagram of the AC Cycle task shown in the figure shows that the difference is that the power signal will not have a falling edge when executing the Warm Reset task, and the 100Mhz clock will continue to be output during the execution of the Warm Reset task and will not be invalid.

[0111] Figure 6 This is a timing signal change diagram corresponding to the cold reset task provided by the present invention. Figure 6 As shown in the figure, for the cold reset task (also called Cold Reset task), Figure 5 Compared with the Warm Reset task shown in the figure, when executing the Cold Reset task, the 100Mhz Clock will have a process of being pulled down to invalid and then outputting a valid clock.

[0112] In some embodiments, the first logic controller is further configured to:

[0113] Determining whether the platform type is a first platform type;

[0114] When the platform type is the first platform type, acquiring a current reset task to be executed by the first logic controller according to level change information of the target reset signal;

[0115] According to the timing signal change information of the current reset task, corresponding reset control operations are performed on the image processing module and the switching module.

[0116] Optionally, the first logic controller may perform the following steps to implement reset control:

[0117] The first logic controller first identifies and determines whether the platform type of the target main control board is the first platform type according to the port signal generated by the pull-up circuit according to the port state of the target general input and output port of the target main control board. In some embodiments, the first platform type here can be an AMD platform type.

[0118] When it is determined that the platform type of the target main control board is not the first platform type, but the second platform type, it indicates that the target main control board matched with the switch board is equipped with a CPU of the second platform type. At this time, the reset control strategy can be dynamically adjusted according to the signal processing logic corresponding to the second platform type to ensure that the system under different chip combinations can be initialized smoothly and run stably. Among them, the signal processing logic corresponding to the second platform type is as follows:

[0119] The first logic controller executes the hardware power-on action according to the normal timing process. This timing process can be the power-on action corresponding to the AC / DC Cycle task, the power-on action corresponding to the Warm Reset task, or the power-on action corresponding to the Cold Reset task. After the power-on process is completed, each switching chip in the switching module (such as PCIE switching chip A and PCIE switching chip B) respectively performs high-speed serial computer expansion bus link training (or PCIE Link Training) with each CPU (such as CPU0 and CPU1) in the target main control board, and each GPU (such as GPU0~GPU9) in the image processing module. After the training is completed, the power-on action corresponding to the next AC / DC Cycle task, the power-on action corresponding to the Warm Reset task, the power-on action corresponding to the Cold Reset task can be executed, or the signal processing process can be directly terminated.

[0120] When it is determined that the platform type of the target main control board is the first platform type, it indicates that the target main control board matched with the switch board is equipped with a CPU of the first platform type. At this time, the reset control strategy can be dynamically adjusted according to the signal processing logic corresponding to the first platform type to ensure that the system under different chip combinations can be initialized smoothly and run stably. Among them, the signal processing logic corresponding to the first platform type is as follows:

[0121] The first logic controller turns on the power of the switching board according to the power-on sequence, and uses the level change information of the received target reset signal to identify and obtain the reset task that the first logic controller currently needs to execute, that is, the current reset task. Among them, different reset tasks correspond to different level change information. Specifically, the corresponding relationship between different reset tasks and different level change information can be determined according to the timing signal change information corresponding to each of the different reset tasks.

[0122] Next, the first logic controller performs corresponding reset control operations on each GPU in the image processing module and each PCIE switching chip in the switching module according to the timing signal change information of the current reset task, thereby fully considering the differences in initialization efficiency, process and global reset function among different chips or components, and dynamically adjusting the timing and parameters of the reset operation to ensure that all components can complete the initialization process in the correct order and state, thereby avoiding system abnormalities due to compatibility issues.

[0123] The timing signal change information here includes but is not limited to power signal timing change information, clock signal timing change information and reset signal timing change information, which is not specifically limited in this embodiment.

[0124] In some embodiments, the reset control operation can be implemented by performing multiple logical judgments on the multi-dimensional timing signal change information of the current reset task, or performing model prediction to obtain the corresponding reset control strategy, thereby executing the corresponding reset control process for the image processing module and the switching module at the corresponding reset operation trigger time based on the corresponding reset control strategy, thereby implementing the reset control operation of the image processing module and the switching module. The reset control strategy here includes but is not limited to the reset operation process and the reset operation trigger time, which are not specifically limited in this embodiment.

[0125] The system provided in this embodiment integrates a first logic controller to intelligently determine the platform type and dynamically adjusts the reset control strategy according to the platform characteristics, so as to effectively solve the compatibility problems caused by design differences among different CPU, PCIE Switch chip and GPU manufacturers by configuring a set of general architecture and corresponding logic controller processing logic, thereby reducing development costs, improving product versatility and stability, and avoiding the complexity and uncertainty brought about by traditional multiple system logic control boards or customized firmware.

[0126] In some embodiments, the first logic controller is further configured to:

[0127] Determine whether a falling edge of the target reset signal is detected according to the level change information of the target reset signal, and obtain a first determination result;

[0128] According to the first judgment result, a current reset task that the first logic controller needs to execute is obtained.

[0129] Optionally, the first logic controller can implement the identification of the current reset task by executing the following steps:

[0130] The first logic controller can determine whether the falling edge of the target reset signal is currently detected based on the level change information of the target reset signal, so as to identify the current reset task that the first logic controller needs to execute based on the corresponding judgment result. Therefore, by monitoring the falling edge of the target reset signal, the required current reset task can be accurately identified and triggered, thereby achieving precise control and timely response of the reset operation, and improving the stability and efficiency of the system.

[0131] In some embodiments, the first logic controller is further configured to:

[0132] In a case where it is known according to the first judgment result that a falling edge of the target reset signal is detected, determining that the current reset task is a cold reset task or a hot reset task;

[0133] When it is known according to the first judgment result that the falling edge of the target reset signal is not detected, it is determined that the current reset task is an AC / DC power cycle task.

[0134] In some embodiments, the first logic controller is further configured to:

[0135] When it is known that the current reset task is a cold reset task or a hot reset task, acquiring a first target delay time according to the timing signal change information of the cold reset task or the hot reset task;

[0136] After delaying for the first target delay time, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, and the image processing module and the switching module are released from reset according to the reset signal after the pull-up process.

[0137] Optionally, the first logic controller may further implement signal processing by executing the following steps:

[0138] The first logic controller determines that the current reset task is a cold reset task or a hot reset task when it is known according to the first judgment result that the falling edge of the target reset signal is currently detected. At this time, the first target delay time can be obtained according to the timing signal change information of the cold reset task or the hot reset task, so that after the falling edge of the target reset signal is detected and the first target delay time is delayed, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, so that the image processing module and the switching module are de-reset according to the reset signal after the pull-up processing. In addition, after the de-reset of the image processing module and the switching module is completed, the switching module can perform PCIE Link Training with the CPU in the target main control board and each GPU in the image processing module respectively, and enter the operating system (OS) of the server after the PCIE Link Training is completed, so as to iteratively execute the next Warm Reset task or Cold Reset task or other tasks.

[0139] It should be noted that the first target delay time here is an uncertain value, which can be obtained by measuring with an oscilloscope based on the timing signal change information of the cold reset task or the hot reset task; specifically, different reset tasks require different measurement methods, and the measured values ​​may be different, such as a 2s delay time or other delay time, which is not specifically limited in this embodiment. In the process of obtaining the first target delay time, it is necessary to ensure that after the reset signal at the input end of the image processing module and the switching module is released after 2s or other measured delay time, the power-on timing of the image processing module and the switching module meets the following requirements: Figure 5 The timing signal changes of the warm reset task as shown in Figure 6 The timing signal changes of the cold reset task are shown.

[0140] In summary, the system provided in this embodiment optimizes the reset operation and PCIE Link Training of the image processing module and the switching module by intelligently identifying the reset task type and accurately controlling the delay time according to different reset task types, thereby effectively improving the operating stability and energy efficiency of the server.

[0141] In some embodiments, the first logic controller is further configured to:

[0142] In the case that it is known according to the first judgment result that the falling edge of the target reset signal is not detected, determining that the current reset task is an AC / DC power cycle task;

[0143] In the case where it is known that the current reset task is an AC / DC power cycle task, determining whether a target indication signal of the last power supply is detected to obtain a second determination result; the target indication signal is used to indicate that the power supply is in a normal operating state;

[0144] According to the second judgment result and the timing signal change information of the AC / DC power cycle task, corresponding reset control operations are performed on the image processing module and the switching module.

[0145] Optionally, the first logic controller may further implement signal processing by executing the following steps:

[0146] The first logic controller determines that the current reset task is an AC / DC power cycle task when it is known according to the first judgment result that the falling edge of the target reset signal is not detected. At this time, it can be further determined whether the target indication signal (or Power Good signal) of the last power supply for indicating that the power supply is in a normal operating state is currently detected to obtain a second judgment result.

[0147] Subsequently, the first logic controller performs multiple logic judgments or model predictions based on the second judgment result and the timing signal change information of the AC / DC power cycle task to obtain a corresponding reset control strategy, thereby performing corresponding reset control operations on the image processing module and the switching module based on the corresponding reset control strategy.

[0148] For example, in some embodiments, the first logic controller may implement the reset control operation through the following logic judgment:

[0149] When it is known according to the second judgment result that the target indication signal of the last power source is detected, obtaining the second target delay time according to the timing signal change information of the AC / DC power cycle task;

[0150] After delaying for the second target delay time, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, and the image processing module and the switching module are released from the reset operation according to the reset signal after the pull-up processing.

[0151] Optionally, when the first logic controller learns from the second judgment result that the target indication signal of the last power supply of the switching board is currently detected, the first logic controller obtains the second target delay time based on the timing signal change information of the AC / DC power cycle task, so as to pull up the reset signal of the input end of the image processing module and the reset signal of the input end of the switching module after delaying for the second target delay time, so as to reset the image processing module and the switching module according to the reset signal after being pulled up.

[0152] It should be noted that the second target delay time here is an uncertain value, which can be obtained by measuring with an oscilloscope based on the timing signal change information of the AC / DC power cycle task; different tasks require different measurement methods, and the measured values ​​may be different, such as a 200ms delay time or other delay times, which is not specifically limited in this embodiment. However, in the process of obtaining the second target delay time, it is necessary to ensure that after the reset signal at the input end of the image processing module and the switching module is released after 200ms or other measured delay time, the power-on timing of the image processing module and the switching module meets the following requirements: Figure 4 The timing signal changes of the AC and DC power cycling tasks are shown.

[0153] For example, in some embodiments, the first logic controller may implement the reset control operation through the following logic judgment:

[0154] The first logic controller, when it is determined according to the second determination result that the target indication signal of the last power source is not detected, returns to the step of determining whether the target indication signal of the last power source is detected until it is determined that the target indication signal of the last power source is detected.

[0155] Optionally, when the first logic controller learns from the second judgment result that the target indication signal of the last power supply has not been detected, the first logic controller returns to the step of determining whether the target indication signal of the last power supply has been detected, and continues to monitor the power supply of the switching board until it is determined that the target indication signal of the last power supply has been detected. Then, based on the timing signal change information of the AC / DC power cycle task, the second target delay time is obtained, so that after delaying for the second target delay time, the reset signal of the input end of the image processing module and the reset signal of the input end of the switching module are pulled high, so that the image processing module and the switching module are released to be reset according to the reset signal after the pull-up process.

[0156] In the system provided in this embodiment, the first logic controller dynamically adjusts the reset control strategy by detecting the falling edge of the target reset signal, the target indication signal, and combining the task timing signal change information, thereby realizing efficient and accurate reset control of the image processing module and the switching module.

[0157] In some embodiments, the switching module is connected to the central processing unit in the target main control board and the image processing module;

[0158] The switching module is used to perform high-speed serial computer expansion bus link training with the central processing unit in the target main control board and the image processing module when the corresponding reset operations of the image processing module and the switching module are completed.

[0159] Among them, the switching module is connected to the central processing unit and the image processing module in the target main control board, and the specific connection method can be set according to actual needs. For example, assuming that the switching module includes PCIE switching chip A and PCIE switching chip B, the target main control board includes CPU0 and CPU1, and the image processing module includes GPU0~GPU9, PCIE switching chip A can be connected to GPU0~GPU4 through a PCIE link, and can be connected to CPU0 through a PCIE link; PCIE switching chip B can be connected to GPU5~GPU9 through a PCIE link, and can be connected to CPU1 through a PCIE link.

[0160] Optionally, when it is determined that the de-reset operations corresponding to the image processing module and the switching module have been completed, each switching chip in the switching module can perform PCIE Link Training with the corresponding CPU and GPU respectively. Thus, after it is determined that the de-reset operations of the image processing module and the switching module have been completed, each switching chip in the switching module can quickly perform efficient PCIE Link Training with the connected CPU and GPU, thereby significantly improving the stability and efficiency of system data transmission.

[0161] In some embodiments, the first logic controller is further configured to:

[0162] When it is determined that the high-speed serial computer expansion bus link training between the switching module and the central processing unit in the target main control board and the image processing module is completed, return to the step of determining whether the platform type is the first platform type and execute the next reset task.

[0163] Optionally, the first logic controller, when determining that the training of the high-speed serial computer expansion bus link between the switching module and the central processing unit and the image processing module in the target main control board is completed, can return to the step of determining whether the platform type is the first platform type, so as to iteratively execute the next reset task, such as the power-on action corresponding to the AC / DC Cycle task, the power-on action corresponding to the Warm Reset task, the power-on action corresponding to the Cold Reset task, or directly end the signal processing process. This achieves automation and flexibility of the system reset process by iteratively determining the platform type and executing the corresponding reset task after the high-speed serial computer expansion bus link training is completed, thereby ensuring the stability and efficiency of the computer system.

[0164] The following uses the example that the first logic controller is FPGA1 and the second logic controller is FPGA0 to specifically describe the signal processing steps performed by the computer system provided in the embodiment of the present application.

[0165] Figure 7 is a flow chart of the signal processing steps provided by the present invention; Figure 7 As shown, the signal processing logic of the firmware in the first logic controller is as follows:

[0166] After the server is powered on, FPGA1 loads code from the internal Configuration Flash Memory (CFM) module to run. After the code is loaded, FPGA1 senses the high and low level states of the port signal of CPU0 transmitted by the pull-up circuit to determine the platform type of the target main control board currently installed in the server from the high and low level states of the port signal of CPU0.

[0167] When it is determined that the target main control board currently carried by the server is of the second platform type (such as the Intel platform type), FPGA1 performs a hardware power-on action according to the target reset signal transmitted by the target main control board in accordance with the normal timing process; the timing process here can be a hardware power-on action corresponding to the AC / DC Cycle task, a hardware power-on action corresponding to the Warm Reset task, and a hardware power-on action corresponding to the Cold Reset task; in addition, after the power-on process is completed, the switching chip in the switching module (such as switching chip A and switching chip B) respectively performs PCIE LinkTraining with the CPU (such as CPU0 and CPU1) in the main control board under the second platform type, and each image processor (such as GPU0~GPU9) in the image processing module. After the end, the hardware power-on action corresponding to the next AC / DC Cycle task, the hardware power-on action corresponding to the Warm Reset task, the hardware power-on action corresponding to the Cold Reset task can be executed or it can be ended directly.

[0168] When it is determined that the target main control board currently installed on the server is of the first platform type (such as the AMD platform type), the FPGA1 of the switch board pushes up the power supply (or Power) of the switch board according to the power-on sequence, and FPGA1 determines whether the falling edge of the target reset signal sent by the CPU (such as CPU0) of the target main control board of the first platform type is detected.

[0169] If FPGA1 does not detect the falling edge of the target reset signal, it means that the server is currently executing the ACCycle task; next, FPGA1 determines whether the Power Good signal of the last Power of the switch board is currently detected. If it is detected, the reset signal (or Reset signal) of the switch chip (such as switch chip A and switch chip B) in the switch module and each image processor (such as GPU0~GPU9) in the image processing module is pulled high to perform the reset action after delaying the second delay time (such as 200ms). If the Power Good signal of the last Power of the switch board is not detected, FPGA1 returns to the step of determining whether the Power Good signal of the last Power of the switch board is currently detected, and continuously monitors until the Power Good signal of the last Power of the switch board is detected, and then the reset signal of the switch chip (such as switch chip A and switch chip B) in the switch module and each image processor (such as GPU0~GPU9) in the image processing module is pulled high to perform the reset action after delaying the second delay time. After the reset action is completed, the switching chips in the switching module (such as switching chip A and switching chip B) can perform PCIE LinkTraining with the CPUs (such as CPU0 and CPU1) of the target main control board under the first platform type and the image processors (such as GPU0~GPU9) in the image processing module respectively, and after the PCIE Link Training is completed, execute the hardware power-on action or other actions corresponding to the next Warm Reset task or Cold Reset task.

[0170] If FPGA1 currently detects the falling edge of the target reset signal, it means that the server is currently performing the WarmReset task and the Cold Reset task. Next, after the first target delay time (such as 2s) after the falling edge of the target reset signal is detected, the reset signal (or Reset signal) of the switching chip (such as switching chip A and switching chip B) in the switching module and each image processor (such as GPU0~GPU9) in the image processing module is pulled high to perform the reset action. After the corresponding reset of the image processing module and the switching module is completed, the switching chip (such as switching chip A and switching chip B) in the switching module can perform PCIE Link Training with each CPU (such as CPU0 and CPU1) of the target main control board under the first platform type and each image processor (such as GPU0~GPU9) in the image processing module, and after the PCIE LinkTraining is completed, the server enters the OS and executes the hardware startup action or other actions corresponding to the next Warm / Cold Reset task.

[0171] It should be noted that the logic of the FW of FPGA1 can be implemented based on other languages ​​such as Verilog language, and this embodiment does not specifically limit this.

[0172] In summary, the computer system provided in this embodiment can not only solve the compatibility issues of CPUs, PCIE switching chips and GPUs on different platforms through universal architecture design, but also reduce development costs and improve universality. The specific effects are as follows:

[0173] First, it can eliminate the differences in initialization efficiency, initialization process, and global reset functions under the PCIE controller between different CPU manufacturers, PCIE Switch chip manufacturers, or GPU manufacturers, and solve compatibility issues such as card loss, switch loss, and PCIE bus bandwidth reduction when chips or component manufacturers with different functions are combined together, thereby completely eliminating the PCIE compatibility issues of CPUs of different platforms with PCIE Switch chips of different platforms and GPU modules of different manufacturers.

[0174] Second, by adding pull-up circuits and optimizing the firmware processing logic of the logic controller, the PCIE compatibility issues of CPUs of different platforms with PCIE Switch chips of different platforms and GPU modules of different manufacturers can be eliminated. The hardware architecture is simple, with low maintenance and repair costs, low development costs, and high reliability. It effectively avoids the high cost of developing multiple system boards or multiple CPLD / BIOS FWs in traditional solutions, and effectively reduces the development cost of the entire system.

[0175] Third, it has strong versatility and can be used to be compatible with CPUs of various platforms and various PCIE Switch manufacturers and GPU manufacturers, so it has a high market value.

[0176] The signal processing method provided by the present invention is described below. The signal processing method described below and the computer system described above can be referenced to each other.

[0177] Figure 8 is a flow chart of the signal processing method provided by the present invention; Figure 8 As shown, the method is implemented by the first logic controller in the computer system provided by the above embodiments, and the method includes step 810 and step 820.

[0178] Step 810, obtaining a platform type corresponding to a target main control board according to a port signal transmitted by a pull-up circuit; the port signal is generated by the pull-up circuit according to a port state of a target general input / output port in the target main control board;

[0179] Step 820: Perform corresponding reset control operations on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board.

[0180] Optionally, the pull-up circuit can obtain the port status of the target GPIO of the target main control board, and generate a corresponding port signal (or CPU_Detect signal) based on the port status of the target GPIO, and transmit the generated port signal to the first logic controller via the connection path between the pull-up circuit and the first logic controller, so that the first logic controller can identify the platform type to which the target main control board belongs based on the corresponding port signal, and call the logic code corresponding to the platform type to implement the corresponding logic signal processing, thereby achieving a set of universal architecture to eliminate the compatibility issues of different CPU platforms with different PCIE Switch chips and GPU components, thereby reducing development costs.

[0181] Optionally, during the signal processing, when the first logic controller receives the port signal transmitted by the pull-up circuit, it may identify the corresponding platform type of the target main control board connected to the uplink of the switching board according to the port signal.

[0182] Exemplarily, the first logic controller may perform the following steps to identify the platform type corresponding to the target main control board:

[0183] The first logic controller can read the port signal sent by the pull-up circuit and determine the level corresponding to the port signal. Then, the correspondence table of preset levels corresponding to the general input and output ports in the main control boards of different platform types is traversed, and the level corresponding to the port signal is compared with the preset level corresponding to the general input and output ports in the main control boards of each preset platform type in the correspondence table to find a match. Once a matching level is found, the platform type of the target main control board can be determined according to the preset platform type corresponding to the matching level, thereby efficiently and accurately identifying the platform type of the target main control board connected to the uplink of the switching board, thereby facilitating the improvement of the compatibility and flexible configuration of the main control boards of different platform types, so as to further improve the scalability and ease of use of the computer system.

[0184] Optionally, after acquiring the corresponding platform type of the target main control board connected upstream to the switch board, the first logic controller may acquire the target reset signal transmitted by the target main control board in real time.

[0185] After acquiring the target reset signal transmitted by the target main control board, the first logic controller can call the corresponding signal processing logic according to the target reset signal transmitted by the target main control board and the platform type to perform corresponding reset control operations on the image processing module and the switching module.

[0186] The method provided in this embodiment integrates a pull-up circuit with a first logic controller, an image processing module and a switching module, and uses the pull-up circuit to monitor the port status of the universal input and output port of the target main control board in real time, and generates and transmits a corresponding port signal to the first logic controller, so that the first logic controller can quickly identify the platform type of the target main control board according to the signal, and flexibly adjust the reset control operation of the image processing module and the switching module in combination with the target reset signal from the target main control board, thereby achieving the compatibility requirements of the main control board combination of multiple platform types through a set of general architecture, so as to eliminate the PCIE compatibility problem of CPUs of different platforms with PCIE Switch chips of different platforms and GPU modules of different manufacturers, which not only simplifies the compatibility processing process for diversified chip combinations, avoids the high development cost of traditional multiple system logic control boards or customized firmware, but also significantly improves the stability and reliability of computer systems under different hardware combinations, thereby effectively reducing the complexity and uncertainty of product development, and providing downstream computer system manufacturers with a more efficient and economical solution.

[0187] The computer system provided by the present invention is used to execute the above-mentioned method embodiments. Please refer to the above-mentioned embodiments for the specific processes and detailed contents, which will not be repeated here.

[0188] Fig. 9 An example of a physical structure diagram of an electronic device is shown in FIG. Fig. 9 As shown, the electronic device may include: a processor 910, a communication interface 920, a memory 930 and a communication bus 940, wherein the processor 910, the communication interface 920 and the memory 930 communicate with each other through the communication bus 940. The processor 910 may call the logic instructions in the memory 930 to execute the signal processing method, which includes: obtaining the platform type corresponding to the target main control board according to the port signal transmitted by the pull-up circuit; the port signal is generated by the pull-up circuit according to the port state of the target general input and output port in the target main control board; according to the platform type and the target reset signal transmitted by the target main control board, performing corresponding reset control operations on the image processing module and the switching module.

[0189] In addition, the logic instructions in the above-mentioned memory 930 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0190] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the signal processing method provided by the above-mentioned methods, which includes: obtaining the platform type corresponding to the target main control board according to the port signal transmitted by the pull-up circuit; the port signal is generated by the pull-up circuit according to the port status of the target general input and output port in the target main control board; and performing corresponding reset control operations on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board.

[0191] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the signal processing method provided by the above-mentioned methods, the method comprising: obtaining a platform type corresponding to a target main control board according to a port signal transmitted by a pull-up circuit; the port signal is generated by the pull-up circuit according to the port status of a target general input / output port in the target main control board; and performing corresponding reset control operations on an image processing module and a switching module according to the platform type and a target reset signal transmitted by the target main control board.

[0192] The system embodiment described above is merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0193] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A computer system, characterized in that: include: Target main control board; A pull-up circuit, the pull-up circuit being connected to a target general input / output port in the target main control board, the pull-up circuit being used to generate a corresponding port signal according to a port state of the target general input / output port; A first logic controller, an image processing module and a switching module, wherein the first logic controller is connected to the target main control board, the pull-up circuit, the image processing module and the switching module, and the first logic controller is used to receive the port signal transmitted by the pull-up circuit, obtain the platform type corresponding to the target main control board according to the port signal, and perform corresponding reset control operations on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board; The first logic controller is also used for: Determining whether the platform type is a first platform type; In the case where the platform type is the first platform type, the current reset task to be executed by the first logic controller is obtained according to the level change information of the target reset signal; wherein different reset tasks correspond to different level change information, and the correspondence between different reset tasks and different level change information is determined according to the timing signal change information corresponding to the different reset tasks; the timing signal change information includes power signal timing change information, clock signal timing change information and reset signal timing change information; According to the timing signal change information of the current reset task, performing corresponding reset control operations on the image processing module and the switching module; The performing corresponding reset control operations on the image processing module and the switching module according to the timing signal change information of the current reset task includes: Perform multiple logical judgments or model predictions on the timing signal change information of the current reset task to obtain a corresponding reset control strategy, and based on the corresponding reset control strategy, execute a corresponding reset control process on the image processing module and the switching module at the corresponding reset operation trigger time; the reset control strategy includes a reset operation process and a reset operation trigger time.

2. The computer system according to claim 1, characterized in that The first logic controller is also used for: Determine whether a falling edge of the target reset signal is detected according to the level change information of the target reset signal, and obtain a first determination result; According to the first judgment result, a current reset task that the first logic controller needs to execute is obtained.

3. The computer system according to claim 2, characterized in that: The first logic controller is also used for: In a case where it is known according to the first judgment result that a falling edge of the target reset signal is detected, determining that the current reset task is a cold reset task or a hot reset task; When it is known according to the first judgment result that the falling edge of the target reset signal is not detected, it is determined that the current reset task is an AC / DC power cycle task.

4. The computer system according to claim 3, characterized in that: The first logic controller is also used for: When it is known that the current reset task is a cold reset task or a hot reset task, acquiring a first target delay time according to the timing signal change information of the cold reset task or the hot reset task; After delaying for the first target delay time, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, and the image processing module and the switching module are released from reset according to the reset signal after the pull-up process.

5. The computer system according to claim 3, characterized in that: The first logic controller is also used for: In the case where it is known that the current reset task is an AC / DC power cycle task, determining whether a target indication signal of the last power supply is detected to obtain a second determination result; the target indication signal is used to indicate that the power supply is in a normal operating state; According to the second judgment result and the timing signal change information of the AC / DC power cycle task, corresponding reset control operations are performed on the image processing module and the switching module.

6. The computer system according to claim 5, characterized in that: The first logic controller is also used for: If it is determined according to the second determination result that the target indication signal of the last power source is not detected, the process returns to the step of determining whether the target indication signal of the last power source is detected until it is determined that the target indication signal of the last power source is detected.

7. The computer system according to claim 5, characterized in that: The first logic controller is also used for: When it is known according to the second judgment result that the target indication signal of the last power source is detected, obtaining the second target delay time according to the timing signal change information of the AC / DC power cycle task; After delaying for the second target delay time, the reset signal at the input end of the image processing module and the reset signal at the input end of the switching module are pulled high, and the image processing module and the switching module are released from the reset operation according to the reset signal after the pull-up processing.

8. The computer system according to claim 7, characterized in that: The switching module is connected to the central processing unit in the target main control board and the image processing module; The switching module is used to perform high-speed serial computer expansion bus link training with the central processing unit in the target main control board and the image processing module when the corresponding reset operations of the image processing module and the switching module are completed.

9. The computer system according to claim 8, characterized in that: The first logic controller is also used for: When it is determined that the high-speed serial computer expansion bus link training between the switching module and the central processing unit in the target main control board and the image processing module is completed, return to the step of determining whether the platform type is the first platform type and execute the next reset task.

10. The computer system according to any one of claims 1 to 9, characterized in that: The first logic controller is further used for: Matching the level corresponding to the port signal with the preset level corresponding to the universal input and output port in the main control board of each preset platform type; According to the matching result, a preset level matching the level corresponding to the port signal is obtained; According to the preset platform type corresponding to the matched preset electrical level, the platform type corresponding to the target main control board is obtained.

11. The computer system according to any one of claims 1 to 9, characterized in that: The pull-up circuit includes a pull-up resistor and a pull-up power supply; A first end of the pull-up resistor is connected to the pull-up power supply, a second end of the pull-up resistor is connected to the target general input / output port, and a third end of the pull-up resistor is connected to the first logic controller.

12. The computer system according to any one of claims 1 to 9, characterized in that: In the case where the target main control board is of the first platform type, the target main control board includes a plurality of central processing units and a second logic controller; The plurality of central processing units are connected via an interconnection interface; At least one of the central processing units is connected to the second logic controller, and the second logic controller is connected to the first logic controller.

13. The computer system according to claim 12, characterized in that: In the case where the platform type is the first platform type, the target reset signal is a global reset signal sent by at least one central processing unit of the target main control board through the second logic controller of the target main control board.

14. The computer system according to any one of claims 1 to 9, characterized in that: In the case where the target main control board is of the second platform type, the target main control board includes a plurality of central processing units, a south bridge chip and a second logic controller; The plurality of central processing units are connected via an interconnection interface; At least one of the central processing units is connected to the south bridge chip, the south bridge chip is connected to the second logic controller, and the second logic controller is connected to the first logic controller.

15. The computer system according to claim 14, characterized in that: In the case where the platform type is the second platform type, the target reset signal is a global reset signal sent by at least one central processing unit of the target main control board through the south bridge chip and the second logic controller in sequence.

16. A signal processing method, characterized in that: The method is applied to the computer system according to any one of claims 1 to 15, and the method comprises: According to the port signal transmitted by the pull-up circuit, the platform type corresponding to the target main control board is obtained; the port signal is generated by the pull-up circuit according to the port state of the target general input and output port in the target main control board; According to the platform type and the target reset signal transmitted by the target main control board, corresponding reset control operations are performed on the image processing module and the switching module.

17. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the signal processing method according to claim 16 is implemented.

18. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the signal processing method according to claim 16 is implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the signal processing method according to claim 16 is implemented.

Images