Logic synthesis circuit area prediction method based on GNN-Transformer

Abstract

The present invention discloses a logic synthesis circuit area prediction method based on GNN-Transformer, the method comprising: constructing a logic synthesis circuit area prediction data set, the data set RTL verilog describes the circuit, and an optimization sequence composed of a series of optimization operators provided by a logic synthesis tool, and the area of ​​the circuit after synthesis as a label; constructing a logic synthesis circuit area prediction model based on GNN-Transformer. The present invention can make more accurate predictions for circuits of different scales by utilizing the spatiotemporal information from the circuit and the optimization sequence, and considering the impact of the large span of data labels of circuits of different scales on model training.

Description

Technical Field

[0001] The present invention belongs to the field of electronic design automation, and specifically is a method for predicting the area of ​​a logic synthesis circuit based on GNN-Transformer. Background Art

[0002] The design complexity of modern VLSI continues to soar, and the main challenge hindering the progress of hardware design is the long delay in obtaining feedback on certain indicators because the electronic design automation (EDA) process for hardware implementation is very time-consuming.

[0003] One way to solve the above problems is to develop various models to perform agile analysis and predict the quality of results (QoR) without starting the EDA process. As a result, designers can obtain QoR, such as area, in a shorter time and explore the design space more effectively. The current single-task prediction method for area uses regression models such as MLP for the final prediction. However, the span of the actual area values ​​of circuits of different sizes is very large, which makes model training difficult and the prediction accuracy is not high. Summary of the invention

[0004] The purpose of the present invention is to address the deficiencies in the prior art and provide a logic synthesis circuit area prediction method based on GNN-Transformer to solve the problem that the traditional area prediction method has low prediction accuracy for circuits of different sizes.

[0005] To solve the above problems, in a first aspect, the present invention provides a method for predicting the area of ​​a logic synthesis circuit based on GNN-Transformer, comprising:

[0006] Step S1: construct a logic synthesis circuit area prediction data set, and divide the data set into a training set, a validation set, and a test set;

[0007] The data set includes input data and label data; the input data includes a circuit described by RTL Verilog and an optimization sequence composed of multiple optimization operators provided by a logic synthesis tool, and the label data uses the area after the circuit logic synthesis;

[0008] Step S2: preprocessing the input data and label data;

[0009] Step S3: construct a logic synthesis circuit area prediction model based on GNN-Transformer, and use the preprocessed data set for training, verification and testing;

[0010] The GNN-Transformer-based logic synthesis circuit area prediction model includes an enhanced GNN module, a Transformer module and a classifier;

[0011] The enhanced GNN module is used to learn the structural characteristics of the circuit;

[0012] The Transformer module is used to learn the time characteristics of the optimization sequence;

[0013] The classifier is used to combine the structural features of the circuit and the time features of the optimized sequence, and then perform classification prediction;

[0014] Step S4: Use the trained, verified and tested GNN-Transformer-based logic synthesis area prediction model to perform logic synthesis area prediction of the circuit.

[0015] Preferably, step S2 comprises the following steps:

[0016] S201: Convert the circuit described in RTL Verilog into AIG format circuit; construct a directed graph based on the AIG format circuit ;in is a collection of nodes, including logic AND gate nodes and logic NOT gate nodes; is a set of edges, which represent the connection relationship between nodes;

[0017] Obtain graph features according to AIG format circuit;

[0018] According to the directed graph Obtaining node features; the node features include node type, node logical level, node in-degree, and node out-degree;

[0019] S202: Mapping multiple optimization operators to a unique digital index respectively to obtain a digitally encoded optimization sequence;

[0020] S203: normalizing the area of ​​the circuit after logic synthesis.

[0021] Preferably, the graph features include the number of main inputs, the number of main outputs, the number of AND nodes, the number of edges, the number of reverse edges and the depth of the graph.

[0022] Preferably, the node type is 0 or 1, 0 represents an AND node and 1 represents a NOT node; the logical level of the node refers to the number of nodes on the longest path from any main input to the node; the in-degree of the node is the number of edges pointing to the node; the out-degree of the node is the number of edges departing from the node.

[0023] Preferably, in the logic synthesis circuit area prediction model based on GNN-Transformer, the enhanced GNN module includes a graph embedding learning stage and a feature fusion stage;

[0024] The input of the graph embedding learning stage is the node features, specifically including the first SAGEConv layer, the first BatchNorm layer, the ReLU layer, the second SAGEConv layer, the second BatchNorm layer, and the add_pool layer;

[0025] The feature fusion stage aggregates the graph features through MLP, and then performs Hadamard product with the graph embedding outputted by the graph embedding learning stage to obtain the structural features of the circuit.

[0026] Preferably, the first SAGEConv layer and the second SAGEConv layer have the same structure, and both update their own node features by aggregating neighbor node features; the mathematical description of the aggregation is as follows:

[0027]

[0028]

[0029] in It is Layer Node The embedding representation of the first SAGEConv layer is The embedding representation uses node features, and the initial node of the second SAGEConv layer The embedding of represents the output result of the ReLU layer; The average aggregation function is used Aggregation Layer Node Embedding representation of all neighbor nodes The aggregation result obtained; W is the weight; is the activation function.

[0030] Preferably, in the logic synthesis circuit area prediction model based on GNN-Transformer, the Transformer module comprises an embedding layer, a position encoding layer, a first Transformer encoder layer, a second Transformer encoder layer and a linear layer;

[0031] The embedding layer converts the preprocessed optimized sequence into an embedding vector of fixed dimension, and then the position encoding layer adds the embedding vector output by the embedding layer to the corresponding position encoding to obtain a vector with position encoding added.

[0032] The first Transformer encoder layer and the second Transformer encoder layer extract temporal features twice from the vector with position encoding added in turn.

[0033] Preferably, in the logic synthesis circuit area prediction model based on GNN-Transformer, the classifier includes a splicing layer, a selector and a plurality of parallel MLPs; the plurality of parallel MLPs are respectively responsible for circuits with different node number ranges;

[0034] The splicing layer splices the structural features of the circuit and the time features of the optimization sequence; the splicing results of the splicing layer are respectively sent to multiple parallel MLPs and selectors, and the selectors are used according to the directed graph. The number of nodes selected corresponds to the aggregation result of the MLP as the logic synthesis circuit area prediction result.

[0035] In a second aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the method.

[0036] In a third aspect, the present invention provides a machine-readable storage medium, characterized in that the machine-readable storage medium stores machine-executable instructions, and when the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method.

[0037] The present invention uses SAGEConv to update node features in the GNN circuit structure feature learning stage, obtains graph embedding by aggregating updated node features through additive pooling, aggregates AIG graph features through MLP, and then performs feature fusion with graph embedding, thereby improving the robustness of the model to the circuit structure; in the prediction stage, multiple parallel MLPs are set, each MLP predicts a range of circuit scales, and a selector controls the output of the corresponding MLP value as the prediction result, thereby reducing the impact of the large span of true values ​​of circuits of different scales on training difficulties, thereby improving the prediction accuracy of the model for circuits of different scales. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a flow chart of the logic synthesis circuit area prediction method based on GNN-Transformer provided by the present invention.

[0039] Figure 2 This is a diagram of the GNN network structure provided by the present invention.

[0040] Figure 3 This is a diagram of the Transformer network structure provided by the present invention.

[0041] Figure 4 This is a diagram of the classifier network structure provided by the present invention. DETAILED DESCRIPTION

[0042] The following is a further detailed description of the principles and features of the logic synthesis circuit area prediction method based on GNN-Transformer proposed in the present invention in conjunction with the accompanying drawings. The examples given are only used to explain the present invention, not to limit the scope of the present invention. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0043] The present invention provides a logic synthesis circuit area prediction method based on GNN-Transformer, and its solution flow chart is as follows: Figure 1 As shown, first, a logic synthesis circuit area prediction data set is constructed, and the data set is divided into a training set, a validation set, and a test set. The data set includes input data and label data, the input data includes a circuit described by RTL verilog, and an optimization sequence composed of a series of optimization operators provided by a logic synthesis tool, and the label data is the area of ​​the circuit after synthesis; the input data and the label data are preprocessed; according to the input data, a logic synthesis circuit area prediction model based on GNN-Transformer is constructed, a loss function is constructed, and the model is trained and verified based on the training set and the validation set using the Adam optimization algorithm; the test set is input into the trained model, the logic synthesis area is predicted, and the model is evaluated with evaluation indicators.

[0044] Therefore, a logic synthesis circuit area prediction method based on GNN-Transformer specifically includes:

[0045] S1: construct a logic synthesis circuit area prediction data set, and divide the data set into a training set, a validation set and a test set; the data set includes input data and label data; the input data includes a circuit described by RTL verilog, and an optimization sequence composed of a series of optimization operators provided by a logic synthesis tool, and the label data is the area of ​​the circuit after synthesis; the optimization operators of the optimization sequence include refactor, refactor -z, rewrite, rewrite -z, resub, resub -z and balance; specifically, the following sub-steps are included:

[0046] S101: Load OpenABC-D, select the circuit described by RTL Verilog and the corresponding optimization sequence of the circuit as input data, and the area after circuit synthesis as label data;

[0047] Among them, OpenABC-D is an open source large-scale dataset for machine learning to guide integrated circuit synthesis.

[0048] S102: Randomly select 80% of the optimized sequences of each circuit for training, and the remaining 20% ​​of the optimized sequences for testing, of which 20% of the training data is used for verification.

[0049] S2: Preprocess the input data and label data; specifically, it includes the following steps:

[0050] S201: Convert the circuit described in RTL Verilog into AIG (And-Inverter-Graph) format circuit; construct a directed graph based on the AIG format circuit express, is a collection of nodes, is a set of edges; where nodes Including logical AND gate nodes and logical NOT gate nodes; edge Indicates the connection relationship between nodes;

[0051] Graph features are obtained according to the AIG format circuit; wherein the graph features include the number of primary inputs (PrimaryInputs), the number of primary outputs (Primary outputs), the number of AND nodes (Nodes), the number of edges (Edges), the number of inverted edges (Inverted edges) and the depth of the graph (Netlist Depth).

[0052] According to the directed graph Get the node type, the node's logical level, the node's in-degree and the node's out-degree, and then construct the node features with the node type, the node's logical level, the node's in-degree and the node's out-degree; where the node type is 0 or 1, 0 represents an AND node, and 1 represents a NOT node. The node's logical level refers to the number of nodes on the longest path from any main input to the relevant node, the node's in-degree is the number of edges pointing to the relevant node, and the node's out-degree is the number of edges starting from the relevant node.

[0053] S202: Mapping multiple optimization operators to a unique digital index respectively to obtain a digitally encoded optimization sequence;

[0054] S203: Perform Min-Max normalization processing on the area after the circuit logic synthesis. The Min-Max normalization calculation formula is:

[0055]

[0056] in is the original data value, is the maximum value in the data, is the minimum value in the data, is the normalized data value.

[0057] S3: Build a GNN-Transformer-based logic synthesis circuit area prediction model and use the preprocessed dataset for training, verification, and testing;

[0058] The GNN-Transformer-based logic synthesis circuit area prediction model includes an enhanced GNN module, a Transformer module and a classifier;

[0059] The enhanced GNN module is used to learn the structural features of the circuit, which includes a graph embedding learning stage and a feature fusion stage:

[0060] Figure 2 To enhance the network structure diagram of the GNN module to extract circuit structure features, the node features of the initial input Embed as initial node Through two SAGEConv layers, each node can learn node embedding from its neighboring nodes. Each SAGEConv layer is followed by batch normalization (BatchNorm), which helps to improve the training speed and accuracy of the model. The activation function ReLU is used to increase the nonlinear characteristics of the network, and the node embedding is additively aggregated to obtain the graph embedding; MLP is used to aggregate the AIG features, and then the HadaMard product is performed with the graph embedding to obtain the AIG Embedding.

[0061] (1) The graph embedding learning stage includes a first SAGEConv layer, a first BatchNorm layer, a ReLU layer, a second SAGEConv layer, a second BatchNorm layer, and an add_pool layer; its input is node features;

[0062] Among them, the first SAGEConv layer and the first BatchNorm layer have the same structure, and are both updated through the neighbor nodes of the aggregation node. The mathematical description of aggregation is as follows:

[0063]

[0064]

[0065] in It is Layer Node The embedding representation of the first SAGEConv layer is The embedding representation uses node features, and the initial node of the second SAGEConv layer The embedding of represents the output result of the ReLU layer; It is Updated nodes in the layer The embedding representation is represented by the average aggregation function. Aggregation Layer Node The embedding representation of all neighbor nodes is the aggregation result , and then the node The embedding representation of With the aggregation results Splicing, linear transformation and activation function Get new node embedding .

[0066] Among them, the first BatchNorm layer and the first BatchNorm layer are used to improve the training speed and accuracy of the model, the ReLU layer is used to increase the nonlinear characteristics of the network, and the add_pool layer is used to perform additive aggregation on the node embedding to obtain the graph embedding. The mathematical description is as follows:

[0067]

[0068] in represents graph embedding, Represents node embedding;

[0069] The Transformer module is used to learn the temporal features of the optimization sequence, and includes an embedding layer, a position encoding layer, a first Transformer encoder layer, a second Transformer encoder layer, and a linear layer;

[0070] Figure 3 The figure is a Transformer network structure diagram. The digitally encoded optimized sequence is converted into an embedded vector of fixed dimension through an embedding layer by using the digital index corresponding to each word. In order to capture the position information of the word in the sequence, these embedded vectors are added with the corresponding position codes. The added vector is used as the input of the first transformer encoder block. Through the stacked first transformer encoder layer and the second transformer encoder layer, the high-order semantic features of the input optimized sequence are gradually extracted and used for downstream QoR prediction. Finally, the output of the second transformer encoder layer is dimensionally scaled through a linear layer to obtain the time features of the final optimized sequence.

[0071] The embedding layer converts the digitally encoded optimized sequence into an embedding vector of fixed dimension, and then the position encoding layer adds the embedding vector to the corresponding position encoding to introduce the information of each position in the sequence. The mathematical description is as follows:

[0072]

[0073]

[0074] in is the position index, is the dimension index, is the embedding dimension, is the position index In the The encoded value on the dimension, is the position index In the Encoded values ​​on the dimensions;

[0075] The first Transformer encoder layer and the second Transformer encoder layer extract temporal features twice from the vector with position encoding added;

[0076] The first Transformer encoder layer and the second Transformer encoder layer have the same structure. The core of both is the multi-head attention mechanism, which is mathematically described as follows:

[0077]

[0078] in , , are the inputs to the multi-head attention mechanism, called query, key, and value, is the output linear transformation parameter of multi-head attention, Indicates the number of heads, Output of a single zoom-click attention , the mathematical description is as follows:

[0079]

[0080]

[0081] in , , It is The linear transformation parameters of the heads, is the dimension of the key, used to scale the dot product to stabilize the gradient.

[0082] The classifier is used to splice the structural features of the circuit and the time features of the optimized sequence, and then perform classification prediction; the classifier includes a splicing layer, a selector and multiple parallel MLPs;

[0083] The splicing layer splices the structural features of the circuit and the time features of the optimized sequence;

[0084] The concatenation results of the concatenation layer are respectively sent to multiple parallel MLPs and selectors, and the selectors are used to select the concatenated layers according to the directed graph. The aggregation result of the MLP corresponding to the number of nodes is selected as the area prediction result of the logic synthesis circuit; the multiple parallel MLPs are respectively responsible for circuits with different node number ranges.

[0085] The training process includes the following sub-steps:

[0086] S401: Set the learning rate for training to , the weight decays to .

[0087] S402: using mean square error MSE as a prediction loss function, and using cross entropy loss CE as an auxiliary loss function for the classifier; adding mean square error MSE and cross entropy loss CE to obtain a final loss function;

[0088] S403: Use the Adam optimizer to optimize the network parameters and gradually reduce the loss value.

[0089] The testing process includes the following steps:

[0090] S501: Input the data in the test set into the trained model.

[0091] S502: Output the final area prediction result of each circuit and use MAPE for evaluation. The mathematical description is as follows:

[0092]

[0093] Where n is the number of samples, It is The actual value of the samples, It is The predicted value of a sample.

[0094] Figure 4 The network structure diagram of the classifier is shown in Figure 2. The circuit is divided into four data ranges according to its size, and four MLP branches with a structure of 96-128-128-1 are used. Each MLP branch corresponds to a data range. We concatenate the structural features of the circuit obtained from the upstream and the temporal features of the optimized sequence, and use the concatenated features as the input of the four MLP branches. We also provide the concatenated features to the selector to decide which output range should be used in the four MLP branches. For each data point, the output of the four MLP branches can be regarded as a vector, expressed as , the output of the classifier is a Indicated A vector indicating which MLP branch's output should be used as the final prediction In order to get ,we will and Perform the multiplication operation, the mathematical description is as follows:

[0095]

[0096] We use the mean square error MSE as the final prediction loss function, which is mathematically described as follows:

[0097]

[0098] in is the true value, is the predicted value, is the number of samples; in addition, we can also get the label of the classification result , and use the cross entropy loss CE as the auxiliary loss function for the selector. The mathematical description is as follows:

[0099]

[0100] in, is the number of categories, It is a sample The actual label category The value of is the sample predicted by the model Belongs to category probability.

[0101] We add the prediction loss MSE and the auxiliary loss CE to calculate the final loss, which is mathematically described as follows:

[0102]

[0103] The experimental environment parameters of the logic synthesis circuit area prediction method based on GNN-Transformer proposed in the present invention are as follows in Table 1:

[0104] Table 1

[0105]

[0106] The prediction results of the trained model and the LOSTIN method on 22 circuits in the test set are shown in Table 2:

[0107] Table 2

[0108]

[0109] An embodiment of the present invention provides an electronic device. Specifically, the electronic device includes a memory and a processor. The memory stores executable code. When the processor executes the executable code, the method described in any one of the implementation modes is implemented.

[0110] The memory may include high-speed random access memory (RAM), and may also include non-volatile memory (Non-volatile Memory), such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0111] The bus may be an ISA bus, a PCI bus or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0112] Among them, the memory is used to store the program, and the processor executes the program after receiving the execution instruction. The method executed by the device for flow process definition disclosed in any embodiment of the above-mentioned embodiment of the present invention can be applied to the processor or implemented by the processor.

[0113] The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0114] The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the methods described in the previous method embodiments. The specific implementation can be referred to the previous method embodiments, which will not be repeated here.

[0115] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0116] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A logic synthesis circuit area prediction method based on GNN-Transformer, characterized by: The following steps are involved: Step S1: construct a logic synthesis circuit area prediction dataset and divide the dataset into a training set, a validation set, and a test set; The data set includes input data and label data; the input data includes a circuit described in RTL Verilog and an optimization sequence composed of multiple optimization operators provided by a logic synthesis tool, and the label data uses the area after circuit logic synthesis; Step S2: preprocessing the input data and label data; Step S3: Build a GNN-Transformer-based logic synthesis circuit area prediction model and use the preprocessed dataset for training, verification, and testing; The GNN-Transformer-based logic synthesis circuit area prediction model includes an enhanced GNN module, a Transformer module and a classifier; The enhanced GNN module is used to learn the structural characteristics of the circuit; The Transformer module is used to learn the temporal features of the optimization sequence; The classifier is used to combine the structural features of the circuit and the time features of the optimized sequence, and then perform classification prediction; Step S4: Use the trained, verified, and tested GNN-Transformer-based logic synthesis area prediction model to predict the logic synthesis area of ​​the circuit; In the GNN-Transformer-based logic synthesis circuit area prediction model, the enhanced GNN module includes a graph embedding learning stage and a feature fusion stage; The input of the graph embedding learning stage is the node features, specifically including the first SAGEConv layer, the first BatchNorm layer, the ReLU layer, the second SAGEConv layer, the second BatchNorm layer, and the add_pool layer; The feature fusion stage aggregates the graph features through MLP, and then performs Hadamard product with the graph embedding output by the graph embedding learning stage to obtain the structural features of the circuit; The first SAGEConv layer and the second SAGEConv layer have the same structure, and both update their own node features by aggregating neighbor node features. The mathematical description of the aggregation is as follows: ； ； in It is Layer nodes The embedding representation of the first SAGEConv layer is The embedding representation uses node features, the initial node of the second SAGEConv layer The embedding of represents the output result of the ReLU layer; The average aggregation function is used Aggregate Layer nodes Embedding representation of all neighbor nodes The aggregation result obtained; W is the weight; is the activation function; The Transformer module includes an embedding layer, a position encoding layer, a first Transformer encoder layer, a second Transformer encoder layer, and a linear layer; The embedding layer converts the preprocessed optimized sequence into an embedding vector of fixed dimension, and then the position encoding layer adds the embedding vector output by the embedding layer to the corresponding position encoding to obtain a vector with position encoding added. The first Transformer encoder layer and the second Transformer encoder layer extract temporal features twice on the vector with position encoding added in turn.

2. The method according to claim 1, characterized in that The step S2 comprises the following steps: S201: Convert the circuit described in RTL Verilog into AIG format circuit; construct a directed graph based on the AIG format circuit ;in is a collection of nodes, including logic AND gate nodes and logic NOT gate nodes; is a set of edges, which represent the connection relationship between nodes; Obtain graph features based on AIG format circuit; According to the directed graph Obtaining node features; the node features include node type, node logical level, node in-degree, and node out-degree; S202: Mapping multiple optimization operators to a unique digital index respectively to obtain a digitally encoded optimization sequence; S203: normalizing the area of ​​the circuit after logic synthesis.

3. The method according to claim 2, characterized in that The graph features include the number of primary inputs, the number of primary outputs, the number of AND nodes, the number of edges, the number of reverse edges, and the depth of the graph.

4. The method according to claim 2, characterized in that The node type is 0 or 1, 0 represents an AND node and 1 represents a NOT node; the logical level of the node refers to the number of nodes on the longest path from any main input to the node; the in-degree of the node is the number of edges pointing to the node; the out-degree of the node is the number of edges departing from the node.

5. The method according to claim 1, characterized in that: In the GNN-Transformer-based logic synthesis circuit area prediction model, the classifier includes a splicing layer, a selector, and multiple parallel MLPs; the multiple parallel MLPs are respectively responsible for circuits with different node number ranges; The splicing layer splices the structural features of the circuit and the time features of the optimized sequence; the splicing results of the splicing layer are respectively sent to multiple parallel MLPs and selectors, and the selectors are used to select the circuit according to the directed graph. The number of nodes selected corresponds to the aggregation result of MLP as the logic synthesis circuit area prediction result.

6. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method according to any one of claims 1 to 5.

7. A machine-readable storage medium, characterized in that The machine-readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method according to any one of claims 1 to 5.

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