2.5D packaging method and 2.5D packaging structure

Abstract

The present application provides a 2.5D packaging method and a 2.5D packaging structure, which relate to the field of semiconductor technology. The 2.5D packaging method includes providing a carrier with a first glue layer; opening a first groove on the first glue layer; forming a first dielectric layer in the first groove; forming a first barrier layer on the first dielectric layer; forming a first metal column that penetrates the first barrier layer and the first dielectric layer; forming a first wiring layer electrically connected to the first metal column; removing the carrier; opening a second groove on the side of the first glue layer away from the first wiring layer; forming a second barrier layer in the second groove; forming a second metal column that penetrates the second barrier layer; connecting the second metal column to the first metal column; removing the first glue layer; mounting a first chip on the second metal column. The structural strength can be improved, and the structural stress on the first wiring layer can be reduced, and the packaging structure is more reliable.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D packaging method and a 2.5D packaging structure. Background Art

[0002] In the existing 2.5D packaging structure, a large number of chips are integrated on the adapter board. Each chip needs to be glued at the bottom, that is, the bottom filler is formed. The more chips are integrated, the more glue the bottom filler accumulates. The adapter board is more affected by the colloid structural stress. Since there is a high-density wiring layer in the adapter board, the wire diameter of the wiring layer is very small, and it is easy to deform or break due to the structural stress generated by the colloid. Summary of the invention

[0003] The objects of the present invention include, for example, providing a 2.5D packaging method and a 2.5D packaging structure, which can reduce the influence of colloid stress on the wiring layer and improve the structural strength and packaging reliability.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a 2.5D packaging method, comprising:

[0006] Providing a carrier having a first adhesive layer;

[0007] Opening a first groove on the first adhesive layer;

[0008] forming a first dielectric layer in the first groove;

[0009] forming a first barrier layer on the first dielectric layer;

[0010] forming a first metal column penetrating the first barrier layer and the first dielectric layer;

[0011] forming a substrate having a first wiring layer; wherein the first metal pillar is electrically connected to the first wiring layer;

[0012] removing the carrier;

[0013] A second groove is formed on a side of the first adhesive layer away from the first wiring layer;

[0014] forming a second barrier layer in the second groove;

[0015] forming a second metal column penetrating through the second barrier layer; the second metal column is connected to the first metal column;

[0016] removing the first adhesive layer;

[0017] A first chip is mounted on the second metal pillar.

[0018] In an optional embodiment, the step of forming a first metal column penetrating the first barrier layer and the first dielectric layer includes:

[0019] forming a third groove penetrating through the first barrier layer and the first dielectric layer;

[0020] forming the first metal column in the third groove;

[0021] The step of forming a second metal column penetrating the second barrier layer comprises:

[0022] forming a fourth groove penetrating through the second barrier layer;

[0023] The second metal pillar is formed in the fourth groove.

[0024] In an optional embodiment, the second metal column includes an edge metal column and an intermediate metal column, and the first chip is mounted on the intermediate metal column; a bottom filler is provided at the bottom of the first chip, and the edge metal column is used to prevent the bottom filler from overflowing.

[0025] In an optional embodiment, the step of providing a carrier having a first adhesive layer includes:

[0026] Mounting the second chip on the carrier using the second adhesive layer;

[0027] Covering the second chip with a first adhesive layer;

[0028] forming a third metal column electrically connected to the second chip in the first glue layer;

[0029] In the step of forming a first wiring layer electrically connected to the first metal pillar, the first wiring layer is connected to the first metal pillar and the third metal pillar respectively.

[0030] In an optional embodiment, the first chip includes a plurality of chips, and the plurality of first chips are stacked.

[0031] In an optional embodiment, after the step of mounting the first chip on the second metal pillar, the method further includes:

[0032] forming a plastic package that wraps the first chip;

[0033] A solder ball is formed on a side of the first wiring layer away from the plastic package body.

[0034] In an optional embodiment, after the step of forming a plastic package encapsulating the first chip, the method further includes:

[0035] forming a second wiring layer on a side of the plastic package body away from the first wiring layer;

[0036] A third chip is mounted on the second wiring layer.

[0037] In an optional embodiment, after the step of mounting the first chip on the second metal pillar, a supporting structure is further formed on a side of the first chip away from the first wiring layer, including:

[0038] forming a third glue layer on a side of the first chip away from the first wiring layer;

[0039] forming a fourth metal column penetrating through the third glue layer;

[0040] forming a third barrier layer on the third adhesive layer;

[0041] forming a second dielectric layer on the three barrier layers;

[0042] forming a fifth metal column penetrating the third barrier layer and the second dielectric layer;

[0043] forming a fourth barrier layer on the second dielectric layer;

[0044] A sixth metal column is formed to penetrate the fourth barrier layer; the fourth metal column, the fifth metal column and the sixth metal column are connected in sequence.

[0045] In an optional implementation, the fourth metal pillar is electrically connected to the first chip.

[0046] In an optional embodiment, in the step of mounting the first chip on the second metal pillar, there are a plurality of the first chips and a plurality of the supporting structures, and the supporting structures and the first chips are stacked alternately.

[0047] In an optional embodiment, a plastic package is formed to encapsulate at least a portion of the first chip; and the support structure is located inside and / or outside the plastic package.

[0048] In an optional embodiment, there are a plurality of support structures, at least two of which are connected via a shielding column, the shielding column has a grounding property, and the shielding column is located at the periphery of at least a portion of the first chip.

[0049] In an optional embodiment, the device further includes a plastic package that wraps at least a portion of the first chip, and the shielding column is exposed from a surface of the plastic package.

[0050] In a second aspect, the present invention provides a 2.5D packaging structure, which is manufactured using the 2.5D packaging method described in any one of the aforementioned embodiments.

[0051] The beneficial effects of the embodiments of the present invention include, for example:

[0052] The 2.5D packaging method provided in the embodiment of the present invention forms a support structure composed of a first dielectric layer, a first barrier layer, a first metal column, a second barrier layer and a second metal column, and the first metal column is connected to the first wiring layer, and the first chip is mounted on the second metal column. In this way, the first chip is attached to the support structure instead of directly attached to the substrate, and the support structure can share most of the colloid structure stress, and the structure is more reliable. The support structure prevents a large amount of colloid from gathering on the substrate, avoiding the risk of deformation or fracture of the first wiring layer in the substrate due to colloid stress, and the packaging quality is better and the reliability is higher.

[0053] The 2.5D packaging structure provided by the embodiment of the present invention is manufactured by the above-mentioned 2.5D packaging method. Since the first chip is mounted on the support structure, a large amount of colloid can be prevented from gathering on the substrate, and the risk of deformation or fracture of the first wiring layer in the substrate due to colloid stress can be avoided, so that the packaging quality is better and the reliability is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0055] Figures 1 to 3 A schematic diagram of a process of a 2.5D packaging method provided by an embodiment of the present invention;

[0056] Figure 4 A schematic diagram of a support structure in a 2.5D packaging structure provided by an embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a first structural example of a 2.5D packaging structure provided by an embodiment of the present invention;

[0058] Figure 6 A second structural schematic diagram of a 2.5D packaging structure provided by an embodiment of the present invention;

[0059] Figures 7 to 9 A schematic diagram of a process of a 2.5D packaging method provided by an embodiment of the present invention;

[0060] Figures 10 to 13 Schematic diagrams of several 2.5D packaging structures provided by embodiments of the present invention.

[0061] Icon: 100-2.5D packaging structure; 101-carrier; 102-first glue layer; 103-first groove; 104-first dielectric layer; 105-first barrier layer; 1051-preset opening; 1053-third groove; 106-first metal column; 107-second groove; 108-second barrier layer; 109-second metal column; 1091-edge metal column; 1093-middle metal column; 110-substrate; 111-first wiring layer; 112-fourth dielectric layer; 113-fifth dielectric layer; 114-bump; 115-ground terminal; 120-support Support structure; 121-first chip; 122-second chip; 123-second glue layer; 1231-first via; 124-third metal pillar; 126-film; 1261-second via; 131-bottom filling glue; 132-solder ball; 133-plastic package; 134-second wiring layer; 135-third chip; 141 third glue layer; 1411-third via; 1412-fourth via; 142-fourth metal pillar; 143-third barrier layer; 144-second dielectric layer; 145-fifth metal pillar; 146-fourth barrier layer; 147-sixth metal pillar. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0063] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0065] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0066] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0067] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0068] Please refer to Figures 1 to 3 The present embodiment provides a 2.5D packaging method, which mainly includes the following steps:

[0069] Step S100 : providing a carrier 101 having a first adhesive layer 102 .

[0070] Step S110 : forming a first groove 103 on the first adhesive layer 102 .

[0071] Step S120 : forming a first dielectric layer 104 in the first groove 103 .

[0072] Step S130 : forming a first barrier layer 105 on the first dielectric layer 104 .

[0073] Step S140 : forming a first metal pillar 106 penetrating the first barrier layer 105 and the first dielectric layer 104 .

[0074] Step S150 : forming a substrate 110 having a first wiring layer 111 ; wherein the first metal pillar 106 is electrically connected to the first wiring layer 111 .

[0075] Step S160 : removing the carrier 101 .

[0076] Step S170 : opening a second groove 107 on a side of the first adhesive layer 102 away from the first wiring layer 111 .

[0077] Step S180 : forming a second barrier layer 108 in the second groove 107 .

[0078] Step S190 : forming a second metal pillar 109 penetrating the second barrier layer 108 ; wherein the second metal pillar 109 is connected to the first metal pillar 106 .

[0079] Step S200: removing the first adhesive layer 102 .

[0080] Step S210 : mounting the first chip 121 on the second metal pillar 109 .

[0081] In this way, the first dielectric layer 104, the first barrier layer 105, the first metal column 106, the second barrier layer 108 and the second metal column 109 form a support structure 120. The first metal column 106 is connected to the first wiring layer 111 of the substrate 110, and the first chip 121 is mounted on the second metal column 109. In this way, the first chip 121 is attached to the support structure 120, not directly attached to the substrate 110, and the support structure 120 can share most of the colloid structure stress, and the structure is more reliable. The support structure 120 prevents a large amount of colloid from gathering on the substrate 110, avoiding the risk of deformation or fracture of the first wiring layer 111 in the substrate 110 due to the colloid stress, and the packaging quality is better and the reliability is higher.

[0082] Optionally, step S100 includes step S101, step S102 and step S103.

[0083] Step S101: Mount the second chip 122 on the carrier 101 using the second adhesive layer 123. The second adhesive layer 123 is a decomposable adhesive layer. For example, at least one of propylene glycol methyl ether acetate and 2-methyl propanol acetate can be used. The pad of the second chip 122 faces upward, that is, the side of the second chip 122 away from the pad is mounted on the carrier 101.

[0084] Step S102: Cover the second chip 122 with the first adhesive layer 102. Optionally, the first adhesive layer 102 is formed on the surface of the carrier 101 with the second chip 122 attached by a spin coating process. The first adhesive layer 102 completely covers the second chip 122, and the thickness of the first adhesive layer 102 is greater than the thickness of the second chip 122. The first adhesive layer 102 is a decomposable adhesive layer, and the material is the same or similar to the material of the second adhesive layer 123. Of course, the process of forming the first adhesive layer 102 includes but is not limited to any one of spin coating, spraying, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0085] Step S103: forming a third metal column 124 electrically connected to the second chip 122 in the first adhesive layer 102. Optionally, after the first adhesive layer 102 is solidified, a first via hole 1231 is opened in the first adhesive layer 102 by dry etching to expose the pad of the second chip 122. A third metal column 124 electrically connected to the pad of the second chip 122 is formed in the first via hole 1231. The height of the third metal column 124 is equal to the depth of the first via hole 1231, that is, the end of the third metal column 124 away from the pad is flush with the surface of the first adhesive layer 102. The molding method of the third metal column 124 includes but is not limited to any one of sputtering, chemical plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0086] Step S110: A first groove 103 is formed on the first adhesive layer 102. Optionally, the first groove 103 is formed on a side of the first adhesive layer 102 away from the carrier 101, including but not limited to etching, laser grooving or electron beam grooving. The first groove 103 is located between the intervals of the plurality of second chips 122, that is, the first groove 103 is spaced apart from the second chips 122 and is staggered. In other words, the projection of the first groove 103 on the carrier 101 and the projection of the second chip 122 on the carrier 101 do not overlap. The depth of the first groove 103 is less than the thickness of the first adhesive layer 102, that is, it does not penetrate the first adhesive layer 102.

[0087] Step S120: forming a first dielectric layer 104 in the first groove 103. Optionally, the first dielectric layer 104 may be formed by any of spin coating, spray coating, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The material of the first dielectric layer 104 includes but is not limited to at least one of silicon nitride, silicon oxynitride, polyimide and benzocyclobutene. Optionally, the first dielectric layer 104 may be formed only at the bottom of the first groove 103, or may be formed at the bottom and the wall of the first groove 103, which is not specifically limited here.

[0088] Step S130: forming a first barrier layer 105 on the first dielectric layer 104. Optionally, a photoresist is spin-coated on the first dielectric layer 104, and a mask is used for shielding. A light source is irradiated on the photoresist for exposure and development to form a window, and a barrier material is filled in the window to form the first barrier layer 105, and then the photoresist is removed. The first barrier layer 105 can be made of at least one of lead, gold, silver and copper, preferably lead. The first barrier layer 105 can be used to block X-rays to prevent the first chip 121 from being damaged when X-rays are used for quality detection. The first barrier layer 105 can be formed by any of sputtering, chemical plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0089] Optionally, the formed first barrier layer 105 has a preset opening 1051. The position of the preset opening 1051 is formed after removing excess photoresist.

[0090] Step S140 : forming a first metal column 106 penetrating the first barrier layer 105 and the first dielectric layer 104 , including: forming a third groove 1053 penetrating the first barrier layer 105 and the first dielectric layer 104 ; and forming the first metal column 106 in the third groove 1053 .

[0091] Optionally, a through hole is formed in the first dielectric layer 104 by dry etching or chemical etching, wherein the through hole corresponds to the preset opening 1051 on the first barrier layer 105. The through hole and the preset opening 1051 together form a third groove 1053. The first metal column 106 is formed in the third groove 1053 by any one of sputtering, chemical plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0092] Optionally, one end of the first metal column 106 away from the carrier 101 is flush with the surface of the first adhesive layer 102. The first metal column 106 can be made of at least one material selected from gold, silver, copper, tin, aluminum and zinc, preferably copper.

[0093] Step S150 : forming a substrate 110 having a first wiring layer 111 ; wherein the first metal pillar 106 is electrically connected to the first wiring layer 111 .

[0094] Optionally, a film 126 is coated on the surface of the first adhesive layer 102 or a third dielectric layer is spin-coated. An opening is formed by etching on the film 126 or the third dielectric layer. In this embodiment, the film 126 is taken as an example. The entire upper surface of the first adhesive layer 102 is coated with a film 126, and the film layer also covers the first metal column 106. A second via 1261 is opened on the film 126 by dry etching, chemical etching, or laser drilling to expose the first metal column 106.

[0095] The fourth dielectric layer 112 is spin-coated on the coating 126, and the image layer opening is formed by exposure and development, and the first wiring layer 111 is formed in the image layer opening. Then, the fifth dielectric layer 113 covering the first wiring layer 111 is spin-coated. The opening is formed by exposure and development, and the bump 114 is formed in the opening for subsequent ball planting. In this way, the production of the substrate 110 is completed.

[0096] Step S160 : removing the carrier 101 . Optionally, UV light is irradiated on the back of the carrier 101 to perform debonding, so as to separate the carrier 101 from the first adhesive layer 102 and remove the carrier 101 .

[0097] Step S170 : opening a second groove 107 on a side of the first adhesive layer 102 away from the first wiring layer 111 .

[0098] Optionally, the product is turned over, with the substrate 110 facing downward, and a second groove 107 is opened on the side of the first adhesive layer 102 away from the first wiring layer 111. The second groove 107 is arranged correspondingly to the first groove 103. The second groove 107 is formed in the same manner as the first groove 103. The depth of the second groove 107 is preferably sufficient to expose the first dielectric layer 104.

[0099] Step S180: forming a second barrier layer 108 in the second groove 107. The second barrier layer 108 is formed in a manner similar to or the same as the first barrier layer 105, and will not be described in detail herein. The material of the second barrier layer 108 is similar to or the same as the material of the first barrier layer 105. It can be understood that the second barrier layer 108 also has a preset opening 1051 after being formed, and the preset opening 1051 exposes the first metal pillar 106.

[0100] Step S190: forming a second metal column 109 penetrating the second barrier layer 108. The preset opening 1051 on the second barrier layer 108 is the fourth groove. Electroplating metal in the preset opening 1051 of the second barrier layer 108 forms the second metal column 109. The material and molding method of the second metal column 109 are the same as those of the first metal column 106. The second metal column 109 is flush with the surface of the first glue layer 102. The second metal column 109 is preferably made of copper. The second metal column 109 is electrically connected to the first metal column 106.

[0101] Step S200: removing the first adhesive layer 102. Optionally, the first adhesive layer 102 and the second adhesive layer 123 are removed by chemical cleaning. The chemical agent used for cleaning is an alkaline or acidic agent.

[0102] In this way, the preparation of the support structure 120 and the substrate 110 is completed. Figure 4 The support structure 120 in this article refers to a structure formed by the first dielectric layer 104, the first barrier layer 105, the first metal pillar 106, the second barrier layer 108 and the second metal pillar 109. It should be noted that the order of the above steps can be flexibly adjusted, for example, the support structure 120 is first made, and then a substrate 110 with a first wiring layer 111 is formed on one side of the support structure 120, and then the second chip 122 is mounted on the substrate 110, which is not specifically limited here.

[0103] Step S210: Mount the first chip 121 on the second metal pillar 109. Mount the first chip 121 on the side of the support structure 120 away from the substrate 110. The first chip 121 can be arranged in a flat or stacked manner, and the stacking can be in a normal stacking or a staggered stacking manner, which is not specifically limited here. In this embodiment, the first chip 121 adopts an HBM chip, and multiple HBM chips are stacked in sequence to improve the integration.

[0104] After mounting the first chip 121, glue is cut at the bottom of the first chip 121 and the second chip 122 respectively to form a bottom filling glue 131. Since the first chip 121 is mounted on the support structure 120. Most of the bottom filling glue 131 under the first chip 121 is gathered on the support structure 120. It can be understood that glue is cut after each first chip 121 is mounted, and the more the first chips 121 are stacked, the more the bottom filling glue 131 accumulates. After the support structure 120 is set, the structural strength of the substrate 110 at the bottom of the first chip 121 is greater, and the support structure 120 bears a large amount of colloid stress, which reduces the influence of the colloid stress on the substrate 110, thereby avoiding deformation or fracture of the first wiring layer 111 in the substrate 110.

[0105] Optionally, the second metal pillar 109 includes an edge metal pillar 1091 and an intermediate metal pillar 1093, and the first chip 121 is mounted on the intermediate metal pillar 1093; a bottom filler 131 is provided at the bottom of the first chip 121, and the edge metal pillar 1091 is used to prevent the bottom filler 131 from overflowing. The edge metal pillar 1091 refers to a circle of metal pillars at the outermost edge of the support structure 120, which can play a good role in blocking the bottom filler, further preventing the bottom filler 131 from overflowing onto the substrate 110, thereby reducing the impact of the structural stress of the colloid on the substrate 110.

[0106] Optionally, after mounting the first chip 121, the first chip 121, the second chip 122 and the substrate 110 may be plastic-encapsulated. Of course, in some embodiments, the plastic encapsulation body 133 may also be omitted, such as Figure 5 As shown. Alternatively, the plastic encapsulation body 133 only encapsulates part of the first chip 121. Alternatively, the plastic encapsulation body 133 only encapsulates part of the second chip 122. Alternatively, the plastic encapsulation body 133 only encapsulates part of the first chip 121 and part of the second chip 122. No specific limitation is made here.

[0107] After plastic packaging, balls are planted under the substrate 110 , and the solder balls 132 are electrically connected to the first wiring layer 111 .

[0108] Combination Figure 6 , the number of the supporting structures 120 is more than one. If there are multiple supporting structures 120, the multiple supporting structures 120 can be flatly distributed or stacked on the substrate 110. In this embodiment, the multiple supporting structures 120 are stacked in the height direction, and one or more stacked first chips 121 are provided between two adjacent supporting structures 120 in the height direction. It can be understood that the multiple supporting structures 120 can be inside the plastic package 133 or outside the plastic package 133, or part of the supporting structures 120 can be inside the plastic package 133 and part of the supporting structures 120 can be outside the plastic package 133. The supporting structure 120 can not only improve the structural strength, play the role of blocking glue, reduce the influence of the glue stress on the substrate 110 and the first wiring layer 111, but also improve the bonding force between the substrate 110, the first chip 121 and the plastic package 133.

[0109] Exemplarily, two support structures 120 are included. One is mounted on the substrate 110, and two first chips 121 are stacked thereon. The plastic package 133 covers the first chip 121, the support structure 120 below the first chip 121, and the second chip 122. Another support structure 120 is arranged above the first chip 121, and the support structure 120 is located outside the plastic package 133, which can play a better role in heat dissipation. In addition, the support structure 120 includes a first barrier layer 105 and a second barrier layer 108, which can also block X-rays from meeting the first chip 121, avoiding the photoelectric effect that causes damage to the first chip 121, and thus protecting the first chip 121.

[0110] It is easy to understand that the first chip 121 includes but is not limited to the HBM chip. After the first barrier layer 105 and the second barrier layer 108 are provided, X-rays can be prevented from meeting the first chip 121 to avoid the generation of a photoelectric effect and thus damage to the first chip 121.

[0111] Optionally, the supporting structure 120 outside the plastic package body 133 is formed in the following manner:

[0112] Combination Figures 7 to 9 , spin-coat the third adhesive layer on the surface of the plastic package 133. The material of the third adhesive layer is similar to that of the first adhesive layer 102. A third via hole 1411 is opened on the third adhesive layer to expose the pad of the top first chip 121. A fourth via hole 1412 is opened to form an edge metal column 1091. The depth of the fourth via hole 1412 is set according to actual needs. If it is necessary to electrically connect with the support structure 120 below, the fourth via hole 1412 needs to expose the edge metal column 1091 in the support structure 120 below. If it is not necessary to electrically connect with the support structure 120 below, the depth of the fourth via hole 1412 is reduced, and it is not necessary to expose the edge metal column 1091 in the support structure 120 below.

[0113] Electroplating metal in the third via hole 1411 and the fourth via hole 1412 forms a fourth metal column 142 penetrating the third glue layer. The fourth metal column 142 is electrically connected to the top first chip 121. A third barrier layer 143 having a preset opening 1051 is formed on the third glue layer. A second dielectric layer 144 is formed on the three barrier layers. An opening penetrating the third barrier layer 143 and the second dielectric layer 144 is formed, and metal is electroplated in the opening to form a fifth metal column 145. It can be understood that an opening corresponding to the preset opening 1051 of the third barrier layer 143 is first formed on the second dielectric layer 144, and then metal is electroplated in the opening to form the fifth metal column 145. The fifth metal column 145 is connected to the fourth metal column 142.

[0114] A fourth barrier layer 146 is formed on the second dielectric layer 144; a sixth metal column 147 is formed to penetrate the fourth barrier layer 146. Optionally, a fourth barrier layer 146 with a local preset opening 1051 is first formed, a dielectric layer is formed on the fourth barrier layer 146, an opening corresponding to the preset opening 1051 of the fourth barrier layer 146 is formed on the dielectric layer, and then a metal is electroplated in the opening to form the sixth metal column 147. The sixth metal column 147 is connected to the fifth metal column 145. In this way, the fourth metal column 142, the fifth metal column 145 and the sixth metal column 147 are connected in sequence. Finally, chemical cleaning is used to remove the third adhesive layer.

[0115] The materials of the third barrier layer 143 and the fourth barrier layer 146 are the same as or similar to the materials of the first barrier layer 105 , and the molding methods are also substantially the same.

[0116] Of course, in this embodiment, the number of first chips 121 between two support structures 120 can be one, three, four, five or more, which is not specifically limited here. It can be understood that if the number of stacked first chips 121 is large and the stacking height is high, one or more support structures 120 can be set between the two support structures 120. In this way, the stacked multiple first chips 121 can be separated into multiple sections, that is, after stacking a certain number of first chips 121, a support structure 120 is set, and after continuing to stack a certain number of first chips 121, another support structure 120 is set, and so on, to achieve alternating stacking of support structures 120 and first chips 121.

[0117] For example, in combination Fig.10 , a support structure 120 is provided after each stack of two first chips 121. In this way, a large amount of colloid can be distributed to multiple support structures 120, which can not only improve the structural strength, but also reduce the stress on each support structure 120, and the blocking effect is better, effectively avoiding the influence of colloid stress on the substrate 110. In addition, the bonding force between the support structure 120, the first chip 121 and the plastic package 133 can be improved, and the structure is more reliable. Of course, in some embodiments, the plastic package 133 can partially or completely cover the first chip 121, which is not specifically limited here. The support structure 120 is located inside and / or outside the plastic package 133. It can be understood that all support structures 120 are all located in the plastic package 133, that is, the plastic package 133 completely covers the support structure 120. Alternatively, no plastic package 133 is provided, and all support structures 120 are located outside the plastic package 133. Alternatively, part of the support structure 120 can be located inside the plastic package 133, and another part of the support structure 120 can be located outside the plastic package 133. If the support structure 120 is disposed outside the plastic package 133 , the heat dissipation effect can be improved. In this embodiment, the first chip 121 , the support structure 120 and the second chip 122 are all located inside the plastic package 133 .

[0118] Understandably, Fig.10 In the support structure 120 shown, if the edge metal pillars in the first metal pillar 106 or the second metal pillar 109 of the support structure 120 have grounding characteristics, the electrostatic ions around the chip can be guided by the edge metal pillars, pass through the first barrier layer 105 or the second barrier layer 108 to reach the grounding end of the chip, and then be introduced layer by layer into the edge metal pillars of the bottommost support structure 120, and finally released from the grounding point of the substrate 110, thereby achieving the purpose of static dissipation.

[0119] Optional, such as Fig.11 ,exist Fig.10On the basis of the above, a substrate 110 having a second wiring layer 134 is formed again on the outside of the plastic package 133, and the third chip 135 or other components are continuously mounted on the second wiring layer 134. The second wiring layer 134 is electrically connected to the top first chip 121, or to the top support structure 120, and the third chip 135 is electrically connected to the second wiring layer 134. This can improve the integration. Of course, according to actual needs, at least one of the first chip 121, the second chip 122 and the support structure 120 can continue to be stacked on the substrate 110 having the second wiring layer 134, which is not specifically limited here.

[0120] It should be noted that, in some embodiments, the bottom filling glue 131 under the second chip 122 may be provided or not provided according to actual needs.

[0121] Optional, such as Fig.12 ,exist Fig.10 On the basis of the above, the edge metal column 1091 of the uppermost support structure 120 is extended to the outside of the plastic package 133. In this way, it can play a role in heat dissipation. When the edge metal column 1091 is grounded, it can also play a role in guiding and releasing static electricity, avoiding the influence or damage of static electricity interference on the chip. In addition, it can also play an electromagnetic shielding role for at least part of the first chip 121.

[0122] Optionally, the edge metal pillars 1091 of multiple support structures 120 in the height direction are connected in sequence. The edge metal pillar 1091 in the second metal pillar 109 of the lower support structure 120 may be directly connected to the edge metal pillar 1091 in the first metal pillar 106 of the adjacent upper support structure 120, or indirectly connected through a shielding pillar, which is not specifically limited here. Optionally, the shielding pillar has a grounding property, which can achieve an electromagnetic shielding effect or an electrostatic guiding effect. For example, the first metal pillar 106 at the edge of the bottom support structure 120 is connected to the grounding terminal 115 in the substrate 110, and the edge metal pillar 1091 in the second metal pillar 109 of the top support structure 120 extends to the outside of the plastic package 133, which plays a role in guiding the static electricity outside the plastic package 133. At the same time, it can also play an electromagnetic shielding role for the first chip 121. Alternatively, the edge metal column 1091 in the second metal column 109 of the uppermost support structure 120 is connected to the shielding column, and the shielding column extends outside the plastic package 133 to guide the static electricity outside the plastic package 133.

[0123] like Fig.13Optionally, some of the multiple support structures 120 may be electrically connected, such as metal pillars at the edges of one or more support structures 120 near the bottom substrate 110 are electrically connected and grounded, such as connected to the ground terminal 115 in the substrate 110. This can provide electromagnetic shielding for the first chip 121 surrounded by the grounded metal pillars, that is, it can provide electromagnetic shielding for part of the first chip 121.

[0124] In summary, the embodiments of the present invention provide a 2.5D packaging method and a 2.5D packaging structure 100, which have the following beneficial effects:

[0125] The 2.5D packaging method and 2.5D packaging structure 100 provided in the embodiment of the present invention are provided with a support structure 120, which has the function of preventing the colloid from overflowing to the substrate 110, thereby reducing the influence of the colloid structure stress on the substrate 110 and avoiding deformation or fracture of the wiring layer in the substrate 110. It is also beneficial to improve the structural strength of the substrate 110, improve the heat dissipation performance and improve the bonding force of the plastic package 133. In addition, the chip integration can be improved to achieve high-density packaging. When the edge metal column 1091 in the support structure 120 is grounded, electromagnetic shielding of some chips or electromagnetic shielding of all first chips 121 can be achieved, and it also has the function of electrostatic guidance and release. The packaging quality and packaging reliability can be greatly improved.

[0126] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A 2.5D packaging method, characterized in that: include: providing a carrier having a first adhesive layer; Opening a first groove on the first adhesive layer; forming a first dielectric layer in the first groove; forming a first barrier layer on the first dielectric layer; forming a first metal column penetrating the first barrier layer and the first dielectric layer; forming a substrate having a first wiring layer; wherein the first metal pillar is electrically connected to the first wiring layer; removing the carrier; A second groove is formed on a side of the first adhesive layer away from the first wiring layer; forming a second barrier layer in the second groove; forming a second metal column penetrating through the second barrier layer; the second metal column is connected to the first metal column; removing the first adhesive layer; A first chip is mounted on the second metal pillar.

2. The 2.5D packaging method according to claim 1, characterized in that: The step of forming a first metal column penetrating the first barrier layer and the first dielectric layer comprises: forming a third groove penetrating through the first barrier layer and the first dielectric layer; forming the first metal column in the third groove; The step of forming a second metal column penetrating the second barrier layer comprises: forming a fourth groove penetrating through the second barrier layer; The second metal pillar is formed in the fourth groove.

3. The 2.5D packaging method according to claim 1, characterized in that: The second metal pillars include edge metal pillars and middle metal pillars, and the first chip is mounted on the middle metal pillars; bottom filling glue is provided at the bottom of the first chip, and the edge metal pillars are used to prevent the bottom filling glue from overflowing.

4. The 2.5D packaging method according to claim 1, characterized in that: The step of providing a carrier having a first adhesive layer includes: Mounting the second chip on the carrier using the second adhesive layer; Covering the second chip with a first adhesive layer; forming a third metal column electrically connected to the second chip in the first glue layer; In the step of forming a first wiring layer electrically connected to the first metal pillar, the first wiring layer is connected to the first metal pillar and the third metal pillar respectively.

5. The 2.5D packaging method according to claim 1, characterized in that: The first chips include a plurality of chips, and the plurality of first chips are stacked.

6. The 2.5D packaging method according to claim 1, characterized in that: After the step of mounting the first chip on the second metal pillar, the method further includes: forming a plastic package that wraps the first chip; A solder ball is formed on a side of the first wiring layer away from the plastic package body.

7. The 2.5D packaging method according to claim 6, characterized in that: After the step of forming a plastic package body encapsulating the first chip, the method further includes: forming a second wiring layer on a side of the plastic package body away from the first wiring layer; A third chip is mounted on the second wiring layer.

8. The 2.5D packaging method according to claim 1, characterized in that: After the step of mounting the first chip on the second metal pillar, the method further includes forming a support structure on a side of the first chip away from the first wiring layer, including: forming a third glue layer on a side of the first chip away from the first wiring layer; forming a fourth metal column penetrating through the third glue layer; forming a third barrier layer on the third adhesive layer; forming a second dielectric layer on the three barrier layers; forming a fifth metal column penetrating the third barrier layer and the second dielectric layer; forming a fourth barrier layer on the second dielectric layer; A sixth metal column is formed to penetrate the fourth barrier layer; the fourth metal column, the fifth metal column and the sixth metal column are connected in sequence.

9. The 2.5D packaging method according to claim 8, characterized in that: The fourth metal pillar is electrically connected to the first chip.

10. The 2.5D packaging method according to claim 9, characterized in that: In the step of mounting the first chip on the second metal pillar, there are a plurality of the first chips and a plurality of the support structures, and the support structures and the first chips are stacked alternately.

11. The 2.5D packaging method according to claim 8, characterized in that: A plastic package is formed to encapsulate at least a portion of the first chip; the support structure is located inside and / or outside the plastic package.

12. The 2.5D packaging method according to claim 8, characterized in that: There are a plurality of support structures, at least two of which are connected via a shielding column, the shielding column has a grounding property, and the shielding column is located at the periphery of at least part of the first chip.

13. The 2.5D packaging method according to claim 12, characterized in that: It also includes a plastic package that wraps at least a portion of the first chip, and the shielding column is exposed from the surface of the plastic package.

14. A 2.5D packaging structure, characterized in that: The 2.5D packaging method is used as claimed in any one of claims 1 to 13.

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