Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present disclosure proposes a semiconductor device and a method for manufacturing the same, the method for manufacturing the semiconductor device comprising: providing a silicon carbide body; forming a plurality of first grooves extending from a first surface of the silicon carbide body into the silicon carbide body, wherein the first grooves have sidewalls and a bottom; forming a shielding area extending from the bottom of the first grooves into the silicon carbide body; forming a metal contact layer, wherein the metal contact layer covers the first surface and fills the first grooves, and the metal contact layer forms a Schottky junction with the silicon carbide body by contacting the sidewalls and / or the first surface of the first grooves.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to semiconductor devices and methods for manufacturing the same. Background Art

[0002] Diodes occupy a fundamental and key position in semiconductor technology, playing an important role in power management, signal control and circuit protection.

[0003] Schottky diode, also known as Schottky barrier diode, is a special diode based on metal-semiconductor contact, with low forward voltage drop and fast switching characteristics. The working principle of this diode is different from the traditional PN junction diode, and it uses the Schottky barrier effect formed between metal and semiconductor to conduct electricity.

[0004] Schottky diodes are widely used in rectification, high-speed switching and power management due to their low forward voltage drop, fast switching and low power consumption.

[0005] However, the reverse breakdown voltage of existing Schottky diodes is low, which limits their use in certain applications. In addition, the frequent occurrence of transient voltage and current in circuits places higher demands on surge protection. Summary of the invention

[0006] In view of this, the embodiments of the present disclosure are intended to provide a semiconductor device and a method for manufacturing the same, which solves the problem of low breakdown voltage and high reverse leakage current of a Schottky diode and improves the working reliability and stability of the semiconductor device by optimizing the electric field distribution.

[0007] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0008] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0009] Providing a silicon carbide body;

[0010] forming a plurality of first trenches extending from a first surface of the silicon carbide body into the silicon carbide body, wherein the first trenches have sidewalls and a bottom;

[0011] forming a shielding region extending from a bottom of the first trench into the silicon carbide body;

[0012] A metal contact layer is formed, wherein the metal contact layer covers the first surface and fills the first trench, and the metal contact layer forms a Schottky junction with the silicon carbide body by contacting a sidewall of the first trench and / or the first surface.

[0013] In some optional examples, before forming the metal contact layer, the method further includes: forming two first doping regions on the first surface, wherein:

[0014] The plurality of first trenches are located between the two first doping regions,

[0015] The first doping region has the same conductivity type as the silicon carbide body and has a doping concentration less than that of the silicon carbide body,

[0016] The shielding region is located between the first doping region and the metal contact layer.

[0017] In some optional examples, the method further includes: forming a second doping region on a side of the first doping region away from the silicon carbide body, the second doping region having the same conductivity type as the shielding region and a doping concentration less than that of the shielding region.

[0018] In some optional examples, the method further includes: forming a third doping region having the same conductivity type as the second doping region and a doping concentration greater than that of the second doping region, wherein the second doping region is located between the first doping region and the third doping region.

[0019] In some optional examples, the shielding region is formed to extend from the sidewall of the first trench into the silicon carbide body, and the shielding region is located between the third doping region and the metal contact layer.

[0020] In some optional examples, before forming the metal contact layer, the method also includes: forming a metal isolation layer on a side wall of each of any two adjacent first trenches, wherein the metal isolation layers on the side walls of any two adjacent first trenches are adjacent to each other, and the metal isolation layer is located between the metal contact layer and the side walls of the first trench.

[0021] In some optional examples, before forming the metal contact layer, the method also includes: forming a metal electrode layer having a work function lower than that of the metal contact layer, wherein the metal electrode layer is located between the metal contact layer and the shielding region and / or between the metal contact layer and the third doping region.

[0022] In some optional examples, the method further includes: forming a second groove between any two adjacent first grooves among the plurality of first grooves, wherein the second groove connects the two adjacent first grooves.

[0023] In a second aspect, an embodiment of the present disclosure further provides a semiconductor device, wherein the semiconductor device includes a silicon carbide body, and the silicon carbide body includes:

[0024] a plurality of first trenches extending from a first surface of the silicon carbide body into the silicon carbide body and having sidewalls and a bottom;

[0025] a shielding region extending from a bottom of the first trench into the silicon carbide body;

[0026] A metal contact layer covers the first surface and fills the first trench, and the metal contact layer forms a Schottky junction with the silicon carbide body by contacting a sidewall of the first trench and / or the first surface.

[0027] In some optional examples, the semiconductor device further includes two first doping regions located on the first surface, wherein:

[0028] The plurality of first trenches are located between the two first doping regions,

[0029] The first doping region has the same conductivity type as the silicon carbide body and has a doping concentration less than that of the silicon carbide body,

[0030] The shielding region is located between the first doping region and the metal contact layer.

[0031] In some optional examples, the semiconductor device also includes a second doping region formed on a side of the first doping region away from the silicon carbide body, wherein the second doping region has the same conductivity type as the shielding region and has a doping concentration less than that of the shielding region.

[0032] In some optional examples, the semiconductor device further includes a third doping region having the same conductivity type as the second doping region and a doping concentration greater than that of the second doping region, wherein the second doping region is located between the first doping region and the third doping region.

[0033] In some optional examples, the shielding region is formed to extend from the sidewall of the first trench into the silicon carbide body, and the shielding region is located between the third doping region and the metal contact layer.

[0034] In some optional examples, the semiconductor device also includes: a metal isolation layer formed on a side wall of each of any two adjacent first trenches, wherein the metal isolation layers on the side walls of any two adjacent first trenches are adjacent to each other, and the metal isolation layer is located between the metal contact layer and the side walls of the first trench.

[0035] In some optional examples, the semiconductor device further includes: a metal electrode layer having a work function lower than that of the metal contact layer, wherein the metal electrode layer is located between the metal contact layer and the shielding region and / or between the metal contact layer and the third doping region.

[0036] In some optional examples, the semiconductor device further includes: a second trench formed between any two adjacent first trenches among the plurality of first trenches, wherein the second trench connects the two first trenches.

[0037] The disclosed embodiments provide a semiconductor device and a method for manufacturing the same. In the semiconductor device, a Schottky junction is formed by a silicon carbide body and a metal contact layer, and a PN junction opposite to the Schottky junction is formed with the silicon carbide body by forming a shielding region at the bottom of a first trench. On the one hand, the combination of the Schottky junction and the reverse biased PN junction can improve the breakdown voltage of the semiconductor device and reduce the reverse leakage current while ensuring that the semiconductor device has a lower forward voltage drop. On the other hand, the introduction of the shielding region can optimize the electric field distribution, thereby improving the working reliability and stability of the semiconductor device in a high-voltage, high-temperature environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0039] Figure 2 A vertical cross-sectional schematic diagram of a silicon carbide body provided in an embodiment of the present disclosure.

[0040] Figure 3 A vertical cross-sectional schematic diagram of a semiconductor device after a first trench is formed provided in an embodiment of the present disclosure.

[0041] Figure 4 A vertical cross-sectional schematic diagram of a semiconductor device after a shielding region is formed according to an embodiment of the present disclosure.

[0042] Figure 5 A vertical cross-sectional schematic diagram of a semiconductor device after a metal contact layer is formed according to an embodiment of the present disclosure.

[0043] Figure 6 A vertical cross-sectional schematic diagram of a semiconductor device after forming a first doped region is provided in an embodiment of the present disclosure.

[0044] Figure 7 A vertical cross-sectional schematic diagram of a semiconductor device after forming a second doping region is provided in an embodiment of the present disclosure.

[0045] Figure 8A vertical cross-sectional schematic diagram of a semiconductor device after a third doping region is formed provided in an embodiment of the present disclosure.

[0046] Fig. 9 A vertical cross-sectional schematic diagram of a semiconductor device after a metal isolation layer is formed according to an embodiment of the present disclosure.

[0047] Fig.10 A vertical cross-sectional schematic diagram of a semiconductor device after a metal electrode layer is formed provided in an embodiment of the present disclosure.

[0048] Fig.11 A vertical cross-sectional schematic diagram of a semiconductor device after a second trench is formed according to an embodiment of the present disclosure.

[0049] Fig.12 A vertical cross-sectional schematic diagram of a semiconductor device after forming a first doped region is provided according to another embodiment of the present disclosure.

[0050] Fig.13 A vertical cross-sectional schematic diagram of a semiconductor device after a shielding region is formed is provided according to another embodiment of the present disclosure.

[0051] Fig.14 A vertical cross-sectional schematic diagram of a semiconductor device after forming a second doping region is provided according to another embodiment of the present disclosure.

[0052] Fig.15 A vertical cross-sectional schematic diagram of a semiconductor device after a third doping region is formed is provided for another embodiment of the present disclosure.

[0053] Fig.16 A vertical cross-sectional schematic diagram of a semiconductor device after forming a first trench and a second trench is provided according to another embodiment of the present disclosure.

[0054] Fig.17 A vertical cross-sectional schematic diagram of a semiconductor device after a metal isolation layer is formed is provided according to another embodiment of the present disclosure.

[0055] Fig.18 A vertical cross-sectional schematic diagram of a semiconductor device after a metal electrode layer is formed is provided in accordance with another embodiment of the present disclosure.

[0056] Fig.19 A vertical cross-sectional schematic diagram of another semiconductor device after a metal isolation layer is formed according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which specific embodiments in which silicon carbide devices may be implemented are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used on other embodiments or used in combination with other embodiments to produce yet another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. If not otherwise stated, corresponding elements in different drawings are represented by the same reference symbols.

[0058] The terms "having", "comprising", "including", and "comprising" and the like are open ended, and the terms indicate the presence of stated structures, elements, or features but do not exclude the presence of additional elements or features. The quantifiers and pronouns "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0059] Ohmic contact is a non-rectifying electrical junction with linear or almost linear current-voltage characteristics. Schottky junction, i.e. Schottky contact, is a metal-semiconductor junction with rectifying characteristics, in which the work function of the metal and the dopant concentration in the semiconductor material are selected so that a depletion zone is formed in the semiconductor material along the metal-semiconductor junction in the absence of an externally applied electric field. In the case of Schottky contact, the term "metal-semiconductor junction" can also refer to a junction between a metalloid semiconductor and a semiconductor, wherein the junction has the same characteristics as a metal-semiconductor junction. For example, a Schottky contact can be formed between polycrystalline silicon and silicon carbide. If two components (e.g., two regions) form an ohmic contact or a Schottky contact, respectively, this may mean that there is an ohmic contact or a Schottky contact between the two components. In both cases, it can be directly adjacent to each other for the two regions. However, it can also be that a further component is located between the two components.

[0060] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations. Two adjacent doping regions of the same conductivity type and having different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doping regions. At a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0061] Schottky diodes have some significant advantages over traditional PN junction diodes, making Schottky diodes more suitable for some specific applications.

[0062] First, Schottky diodes have a lower forward voltage drop than PN junction diodes. Low forward voltage drop means that when the diode is forward-conducting, less power loss is generated, which can significantly improve system efficiency, especially in low-voltage, high-current applications.

[0063] In addition, since the carriers of Schottky diodes are majority carriers (such as electrons), there is no minority carrier storage effect, so the switching speed is very fast. In contrast, PN junction diodes need to deplete minority carriers when switching, so the switching speed is slower. This characteristic of Schottky diodes makes them perform well in high-frequency applications, such as switching power supplies, RF circuits, etc.

[0064] Furthermore, Schottky diodes have almost no reverse recovery time, which means that they can switch very quickly between forward conduction and reverse blocking. In contrast, PN junction diodes need to clear minority carriers during the shutdown process, and there will be a significant reverse recovery time. The shorter recovery time gives Schottky diodes a significant advantage in high-speed switching circuits.

[0065] However, it is precisely because of the above structural characteristics that Schottky diodes also have some disadvantages. One of the main disadvantages of Schottky diodes is that they have a large reverse leakage current under reverse bias. Since the Schottky barrier is relatively low, there will be a large reverse leakage current when a reverse voltage is applied. This feature makes it perform poorly in applications with high voltage or where low leakage current is required. In addition, the reverse breakdown voltage of Schottky diodes is usually low, which makes them unsuitable for high voltage applications.

[0066] In view of the above situation, the embodiments of the present disclosure are intended to provide a semiconductor device and a method for manufacturing the same, which solves the problem of low breakdown voltage and high reverse leakage current of Schottky diodes and improves the working reliability and stability of the semiconductor device by optimizing the electric field distribution.

[0067] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0068] See also Figure 1 Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, which may include steps S101 to S104.

[0069] In step S101 , a silicon carbide body is provided.

[0070] See also Figure 2 , the silicon carbide body 1 may include a first surface 1A at the front side and an opposite second surface 1B at the back side. The silicon carbide body 1 may be of polytype 15R-SiC, 2H-SiC, 4H-SiC or 6H-SiC. In addition to the main components of silicon and carbon, the silicon carbide body 1 may also include dopant atoms such as nitrogen N, phosphorus P, arsenic As, antimony Sb, tellurium Te, so that the conductivity type of the silicon carbide body 1 is n-type.

[0071] In addition, the silicon carbide body 1 may also include unavoidable impurities, such as hydrogen and / or oxygen.

[0072] In step S102 , a plurality of first trenches extending from a first surface of the silicon carbide body into the silicon carbide body are formed, wherein the first trenches have sidewalls and a bottom.

[0073] In some embodiments of the present disclosure, see Figure 3 A plurality of first trenches 11 extending from the first surface 1A into the silicon carbide body 1 may be formed on the silicon carbide body 1, wherein the first trenches 11 are formed to have sidewalls and a bottom. Figure 3 Two first grooves 11 are shown in FIG. It is understandable that more first grooves 11 can be formed on the silicon carbide body 1 according to specific application scenarios, and the size, position and spacing between different first grooves 11 can also be determined according to application requirements. The sizes of different first grooves 11 can be the same or different, and the present disclosure does not limit this.

[0074] As an example, a mask etching process may be used to etch the silicon carbide body 1 to form the first trench 11. The selection of mask material and determination of specific process parameters may be determined according to the specific depth and sidewall accuracy requirements of the first trench 11, which will not be described in detail in this disclosure.

[0075] In step S103, a shielding region extending from the bottom of the first trench into the silicon carbide body is formed;

[0076] In some embodiments of the present disclosure, see Figure 4 After forming the first trench 11 , a shielding region 12 extending into the silicon carbide body 1 may be formed at the bottom of the first trench 11 .

[0077] It should be noted that the conductivity type of the shielding region 12 is p-type, which is different from the conductivity type of the silicon carbide body 1. The shielding region 12 is arranged between the first trench 11 and the silicon carbide body 1, which helps to reduce the electric field concentration effect, improve the distribution of the electric field, and prevent local breakdown under high-voltage operation. Moreover, the introduction of the shielding region 12 can effectively alleviate the electric field concentration at the bottom of the first trench 11, and increase the voltage resistance and reliability of the semiconductor device.

[0078] The formation of the shielding region can be achieved by doping. As an example, a p-type doped region can be formed by high-temperature and high-energy ion implantation of aluminum Al elements to serve as the shielding region 12. High-energy ion implantation means that the energy of the implanted ions is high enough so that dopants such as aluminum can penetrate the surface and reach deep into the silicon carbide body. The energy selection of the ions can be adjusted according to the required doping depth and concentration. During the implantation process, maintaining a high temperature state can reduce the lattice defects generated during the implantation process and ensure that the dopant is evenly distributed. At the same time, high temperature can also reduce stress concentration and prevent degradation of device performance. It can be understood that the above content is only exemplary. In actual applications, other elements can also be used as dopants and other doping methods can be used.

[0079] In step S104 , a metal contact layer is formed, wherein the metal contact layer covers the first surface and fills the first trench, and the metal contact layer forms a Schottky junction with the silicon carbide body by contacting the sidewall and / or the first surface of the first trench.

[0080] In some embodiments of the present disclosure, see Figure 5 After forming the shielding region 12, a metal contact layer 2 covering the first surface 1A and filling the first trench 11 may be formed. The metal contact layer 2 may contact at least one of the sidewall of the first trench 11 and the first surface 1A to form a Schottky junction.

[0081] exist Figure 5 In the embodiment shown in FIG. 1 , the metal contact layer 2 contacts both the sidewall of the first trench 11 and the first surface 1A. In other embodiments not shown, the metal contact layer 2 may contact only the sidewall of the first trench 11 or the first surface 1A, as long as a Schottky junction can be formed.

[0082] When selecting a material for the metal contact layer 2, the work function of the material needs to be considered to ensure that a good Schottky barrier height can be achieved. As an example, materials such as titanium Ti, aluminum Al, etc. can be selected, and alloy materials including these metal elements can also be selected.

[0083] The metal contact layer 2 may be formed by, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD). In practical applications, a suitable process may be selected according to the depth and shape of the first trench 11 .

[0084] The embodiment of the present disclosure provides a method for manufacturing a semiconductor device. In the semiconductor device, a Schottky junction is formed by a silicon carbide body 1 and a metal contact layer 2, and a PN junction opposite to the Schottky junction is formed with the silicon carbide body 1 by forming a shielding area 12 at the bottom of the first trench 11. On the one hand, the combination of the Schottky junction and the reverse biased PN junction can improve the breakdown voltage of the semiconductor device and reduce the reverse leakage current while ensuring that the semiconductor device has a lower forward voltage drop. On the other hand, the introduction of the shielding area can optimize the electric field distribution, thereby improving the working reliability and stability of the semiconductor device in a high-voltage, high-temperature environment.

[0085] In some embodiments of the present disclosure, before forming the metal contact layer 2, referring to Figure 6 Two first doping regions 13 can be formed on the first surface 1A, wherein a plurality of first grooves 11 are located between the two first doping regions 13, the first doping region 13 has the same conductivity type as the silicon carbide body 1 and has a doping concentration less than that of the silicon carbide body 1, and the shielding region 12 is located between the first doping region 13 and the metal contact layer 2.

[0086] exist Figure 6 , an embodiment of a semiconductor device including three first trenches 11 is shown, wherein the three first trenches 11 are arranged side by side in a left-right adjacent manner. Since the first trench 11 located on the leftmost side and the first trench 11 located on the rightmost side of the three first trenches 11 are not directly adjacent, the spacing between the two is greater than the spacing between any two adjacent first trenches.

[0087] A first doping region 13 may be formed on a portion of the first surface 1A. Figure 6 As shown, two first doping regions 13 may be formed on the first surface 1A on the left side of the leftmost first trench 11 and on the first surface 1A on the right side of the rightmost first trench 11. That is, the three first trenches 11 are located between the two first doping regions 13.

[0088] exist Figure 6In the illustrated embodiment, the shielding region 12 is formed to extend from the sidewalls of the two farthest first trenches 11 into the silicon carbide body 1 and be located between the first doping region 13 and the metal contact layer 2, so that the shielding region 12 can directly contact the first doping region 13. In addition, the first doping region 13 can contact the metal contact layer 2.

[0089] The first doped region 13 may have the same conductivity type as the silicon carbide body 1 , but with a lower doping concentration, ie, may be n-type, which may increase the overall breakdown voltage of the device by forming a moderate electric field shielding effect near the Schottky junction.

[0090] In particular, since the electric field concentration phenomenon usually occurs in the boundary area between the conductive material and the insulating material, especially in the area with sharp geometric shapes such as the groove area, the transition effect of the first doped region 13 can alleviate the local electric field strength in the first groove 11 area, reduce the breakdown risk caused by the electric field concentration, and thus improve the voltage resistance and reliability of the device.

[0091] Moreover, since the doping concentration of the first doping region 13 is low, the path through which the current passes can be extended and the resistance can be increased, thereby reducing the chance of reverse current passing through the Schottky junction and reducing current leakage during reverse bias, that is, reducing reverse leakage current. This can help maintain efficient operation of semiconductor devices, especially in high-voltage applications, can reduce energy loss and improve the overall efficiency of the device.

[0092] In addition, arranging the shielding region 12 between the first doping region 13 and the metal contact layer 2 can effectively combine the advantages of the doping region and the shielding region, making the electric field distribution more uniform, thereby further optimizing the overall performance of the device.

[0093] In some embodiments of the present disclosure, see Figure 7 The method may further include: forming a second doping region 14 having the same conductivity type as the shielding region 12 and a doping concentration less than that of the shielding region 12 on a side of the first doping region 13 away from the silicon carbide body 1 .

[0094] like Figure 7 As shown, the first doping region 13 may be disposed on the first surface 1A, and the second doping region 14 may be disposed on the upper surface of the first doping region 13, that is, disposed on a side of the first doping region 13 away from the silicon carbide body 1. The second doping region 14 may contact the metal contact layer 2.

[0095] Since the second doping region 14 has the same conductivity type as the shielding region 12, but has a lower doping concentration than the shielding region 12, that is, it can be p-type, the sudden change of the electric field is further mitigated by forming the low-doped second doping region 14 above the first doping region 13. This dual-doping region design makes the electric field distribution smoother through step-by-step transition, reduces the sharp change of the local electric field, and thus improves the device's anti-breakdown capability.

[0096] Moreover, the second doping region further delays the expansion of the depletion region due to its low doping concentration. The multi-layer doping structure increases the range of the depletion region, allowing the device to withstand a higher voltage and further improving the breakdown voltage of the device.

[0097] In addition, the low doping concentration of the second doping region further suppresses the generation of reverse current, and the low doping region can provide a greater blocking effect when reverse biased, thereby reducing reverse leakage current.

[0098] In some embodiments of the present disclosure, see Figure 8 The method further includes: forming a third doping region 15 having the same conductivity type as the second doping region 14 and a doping concentration greater than that of the second doping region 14 , wherein the second doping region 14 is located between the first doping region 13 and the third doping region 15 .

[0099] like Figure 8 As shown, a third doping region 15 may be formed on a surface of the second doping region 14 away from the silicon carbide body 1, that is, Figure 8 A third doping region 15 is formed on the upper surface of the second doping region 14. The conductivity type of the third doping region 15 may be p+ type. The doping concentration of the third doping region 15 may be the same as or different from the doping concentration of the shielding region 12, which is not limited in the present disclosure.

[0100] By providing a third doping region 15 with a higher doping concentration, the electric field distribution can be further optimized, forming a step-by-step transition electric field buffer structure. The third doping region 15 can provide a stronger electric field shielding effect, and work together with the second doping region 14 to slow down the electric field change and avoid excessive local electric field concentration.

[0101] Moreover, the addition of the third doping region 15 can more effectively delay the expansion of the depletion region and provide a higher breakdown voltage. Since the doping concentration of the third doping region 15 is higher than that of the second doping region 14, the third doping region 15 can provide a stronger electric field shielding and support for the device, so that the device can work normally at a higher voltage.

[0102] The high doping concentration of the third doping region 15 also helps to further reduce the leakage current during reverse bias. The introduction of the third doping region 15 increases the electric field blocking effect, further restricts the path of the reverse current, effectively reduces the generation of leakage current, and shows better leakage current control especially under high voltage conditions.

[0103] In some embodiments of the present disclosure, see Figures 6 to 8 The shielding region 12 may be formed to extend from the sidewall of the first trench 11 into the silicon carbide body 1 , and the shielding region 12 is located between the third doping region 15 and the metal contact layer 2 .

[0104] exist Figures 6 to 8 In the illustrated embodiment, the shielding area 12 is not only formed at the bottom of the first groove 11, but also extends to the sidewall of the first groove 11. The sidewall of the first groove 11 is often an electric field concentration area, which is prone to local breakdown under high voltage conditions. By extending the shielding area 12 to the sidewall of the first groove 11, not only can the bottom of the first groove 11 be shielded from the electric field, but the sidewall area of ​​the entire first groove 11 can also be adjusted to the electric field, so that the electric field concentration phenomenon in the entire groove area is effectively alleviated. This arrangement of the shielding area 12 improves the overall voltage resistance of the semiconductor device, ensuring that when working in a high-voltage environment, no local breakdown occurs in the first groove area, thereby improving the high-voltage working performance of the semiconductor device.

[0105] The working principle of the semiconductor device including the first doping region 13 , the second doping region 14 and the third doping region 15 is described below.

[0106] When a forward bias voltage is applied to the semiconductor device, the Schottky junction formed by the metal contact layer 2 and the silicon carbide body 1 is turned on first. The Schottky junction can be turned on quickly at a low forward voltage due to its low forward voltage drop and fast response characteristics. The turn-on of the Schottky junction provides a fast current conduction path, which helps to improve switching efficiency and reduce switching losses.

[0107] As the voltage further increases, the first doping region 13 and the second doping region 14 begin to conduct, that is, the p-region and the n-region begin to conduct. The conduction of this region provides an additional current conduction path and affects the conductive properties of the semiconductor device. The conduction of the first doping region 13 and the second doping region 14 means that a larger current can flow through this region, helping the device to withstand higher current shocks.

[0108] After further increasing the forward bias voltage, the PN junction formed by the shielding region 12 and the first doped region 13 is turned on. The opening of this PN junction makes the conductivity modulation effect more obvious. This is because when the PN junction is turned on, holes and electrons recombine, increasing the conductivity of the epitaxial region, allowing the region to withstand a larger current. This effect can significantly improve the current carrying capacity of the semiconductor device and enhance its surge resistance.

[0109] Finally, the PN junction formed by the shielding area 12 and the silicon carbide body 1 is turned on. The opening of this PN junction further enhances the current conduction. Since both the shielding area 12 and the silicon carbide body 1 have a high doping concentration, the conductivity is further improved. This part of the structure not only improves the forward current conduction capability of the semiconductor device, but also can withstand large currents under surge conditions, thereby enhancing the surge resistance.

[0110] When a reverse bias voltage is applied to the semiconductor device, the silicon carbide body 1 and the shielding area 12 form a reverse biased PN junction. The reverse biased PN junction can effectively shield the Schottky junction to prevent it from being broken down under a high reverse voltage. This is because the withstand voltage of the reverse biased PN junction is usually higher than that of the Schottky junction, so under a reverse voltage, the reverse biased PN junction plays a protective role.

[0111] In fact, due to the shielding effect of the reverse biased PN junction, the Schottky junction no longer directly bears the entire reverse voltage, but the reverse biased PN junction bears most of the reverse electric field. This makes the semiconductor device have a higher voltage resistance and can work stably under high voltage environment without failure due to premature breakdown of the Schottky junction.

[0112] In summary, the semiconductor device obtained by the above method can, under forward bias, as multiple PN junctions are gradually turned on, the conductivity modulation effect enables the semiconductor device to withstand higher currents. This multi-layer structure design increases the carrying capacity of the semiconductor device under high surge current conditions by increasing the conductive channel, effectively improving the surge resistance performance.

[0113] Under reverse bias, the shielding effect of the reverse biased PN junction significantly improves the voltage resistance of semiconductor devices. By shielding the Schottky junction with the reverse biased PN junction, semiconductor devices can avoid the breakdown of the Schottky junction under reverse voltage, thereby maintaining stable operation under high voltage conditions.

[0114] The low forward voltage drop and fast response of the Schottky junction make the semiconductor device have lower switching loss and higher switching speed when forward conducting, which is suitable for high-frequency applications. At the same time, the introduction of the reverse biased PN junction can provide good current carrying capacity under high current conditions.

[0115] In some embodiments of the present disclosure, before forming the metal contact layer 2, see Fig. 9 The method further includes: forming a metal isolation layer 16 on a side wall of each of any two adjacent first trenches 11, wherein the metal isolation layers 16 on the side walls of any two adjacent first trenches 11 are adjacent to each other, and the metal isolation layer 16 is located between the metal contact layer 2 and the side wall of the first trench 11.

[0116] Refer to the following Fig. 9 In the description, a semiconductor device having two first trenches 11 is taken as an example.

[0117] like Fig. 9 As shown, the two first trenches 11 are arranged side by side, that is, the two first trenches 11 are adjacent to each other, so the right side wall of the first trench 11 on the left is also adjacent to the left side wall of the first trench 11 on the right. A metal isolation layer 16 is formed on the right side wall of the first trench 11 on the left and on the left side wall of the first trench 11 on the right. Therefore, the two metal isolation layers 16 formed on the side walls of the two first trenches 11 are also adjacent to each other.

[0118] As an example, the metal isolation layer 16 may be formed of silicon dioxide, or may be formed of materials such as aluminum oxide, silicon nitride, etc. The specific material selection of the metal isolation layer 16 may be customized according to process requirements, and the present disclosure does not limit this.

[0119] The metal isolation layer 16 can separate the metal contact layer 2 from the sidewall of the first trench 11, reducing the direct electrical contact between the metal and the semiconductor, and avoiding the electric field concentration phenomenon under high voltage conditions. Through this electrical isolation structure, the electric field is more evenly distributed in the area of ​​the first trench 11, thereby reducing the situation where the local electric field is too high.

[0120] Moreover, the metal isolation layer 16 also prevents excessive accumulation of electric field in the sidewall region of the first trench 11, reducing parasitic capacitance caused by electric field coupling, which is particularly beneficial to high-frequency switching circuits, reducing switching losses and improving overall switching efficiency.

[0121] In addition, the metal isolation layer 16 acts as an electric field shielding structure, reducing the concentration effect of surge voltage in the sidewall area and preventing local breakdown, thereby protecting the stability of the semiconductor device under high surge conditions. Its additional isolation function enables the device to withstand higher transient voltage and current shocks.

[0122] In some embodiments of the present disclosure, before forming the metal contact layer 2, see Fig.10The method further includes: forming a metal electrode layer 3 having a work function lower than that of the metal contact layer 2 , wherein the metal electrode layer 3 is located between the metal contact layer 2 and the shielding region 12 and / or between the metal contact layer 2 and the third doping region 15 .

[0123] exist Fig.10 In the embodiment shown in the figure, the metal electrode layer 3 extends continuously, so that the surface of the metal electrode layer 3 close to the silicon carbide body 1 is in contact with the shielding area 12 and the third doping area 15, and the surface of the metal electrode layer 3 away from the silicon carbide body 1 is in contact with the metal contact layer 2. It can be understood that, although not shown in the figure, in actual applications, the metal electrode layer 3 can also be provided only between the metal contact layer 2 and the shielding area 12, or the metal electrode layer 3 can be provided only between the metal contact layer 2 and the third doping area 15.

[0124] The metal electrode layer 3 has a lower work function than the metal contact layer 2, so it is easier to form an ohmic contact with the semiconductor. The metal electrode layer 3 can be deposited on the surface of the shielding area 12 and the third doping area 15 away from the silicon carbide body 1 by evaporation or sputtering, and then annealed at high temperature, so that the metal and the shielding area 12 and the third doping area 15 form a metal silicon compound with low contact resistivity, such as NiSi alloy.

[0125] The materials and processes for forming the metal electrode layer 3 are not limited to the above contents, and other materials and processes may also be used according to specific application requirements, which is not limited in the present disclosure.

[0126] By making the metal electrode layer 3 form a better ohmic contact on the shielding area 12 and the third doped area 15, the interface potential difference can be reduced, thereby reducing the contact resistance when the current passes through. This improvement in contact can reduce the power consumption of the semiconductor device during forward conduction and improve the current transmission efficiency. In the case of reverse bias, the metal electrode layer 3 can also provide a better electric field buffering effect, further enhancing the reverse withstand voltage capability of the semiconductor device. Through the optimized contact between the shielding area 12 and the metal electrode layer 3, the reverse voltage can be better borne and the concentration effect of the electric field in the metal contact layer 2 can be reduced.

[0127] In addition, the introduction of the metal electrode layer 3 not only improves the contact resistance, but also enhances the semiconductor device's ability to withstand surge voltage shocks by optimizing the ohmic contact and electric field distribution. Especially under high current surges, the improvement of the ohmic contact can reduce power loss in current transmission and avoid local overheating and damage.

[0128] In some embodiments of the present disclosure, see Fig.11The method further includes: forming a second groove 17 between any two adjacent first grooves 11 among the plurality of first grooves 11 , wherein the second groove 17 connects the two adjacent first grooves 11 .

[0129] See also Fig.11 , the second trench 17 can be formed by partially removing the silicon carbide body 1 located between two adjacent first trenches 11. That is, the sidewalls of the two adjacent first trenches 11 adjacent to the other first trench 11 can be partially removed. The second trench 17 enables the two first trenches 11 to communicate with each other. Fig.11 As shown, the distance between the bottom of the second trench 17 and the second surface 1B is greater than the distance between the bottom of the first trench 11 and the second surface 1B.

[0130] The second groove 17 can serve as an electric field buffer to effectively disperse the electric field gradient between two adjacent first grooves 11, so that the electric field is more evenly distributed between the two adjacent first grooves 11, reducing the concentration effect caused by the electric field difference between the adjacent first grooves 11, thereby making the electric field more evenly distributed and reducing the local electric field strength.

[0131] In addition, in high-power applications, the groove structure is prone to form local hot spots. By adding the second groove 17, an additional path can be provided for the heat dissipation of the semiconductor device, effectively improving the thermal management performance. Due to the connection between adjacent first grooves 11, heat can be diffused out faster through the second groove, thereby avoiding local overheating and improving the thermal stability of the device.

[0132] A process for forming a semiconductor device is described below by way of example.

[0133] First, see Fig.12 , a first doping region 13 can be grown on the first surface 1A of the silicon carbide body 1 of n-type conductivity by, for example, CVD, wherein the first doping region 13 has the same conductivity type as the silicon carbide body 1 and has a doping concentration less than that of the silicon carbide body 1. Fig.12 As shown, the first doped region 13 is an n-region.

[0134] Next, see Fig.13 According to the requirements of the application scenario, a shielding area 12 having a different conductivity type from the silicon carbide body 1 can be formed at a predetermined position from the surface of the first doping area 13 away from the silicon carbide body 1, toward the silicon carbide body 1, for example, by high-temperature and high-energy ion implantation. Fig.13 As shown, the shielding region 12 extends from the surface of the first doping region 13 away from the silicon carbide body 1 into the silicon carbide body 1. The shielding region 12 is a p+ region.

[0135] Next, see Fig.14 , a second doping region 14 having the same conductivity type as the shielding region 12 and a doping concentration less than that of the shielding region 12 can be formed at a side of each of the two first trenches 11 that are farthest apart from the other first trenches 11, from a surface of the first doping region 13 that is far away from the silicon carbide body 1 toward the silicon carbide body 1, for example, by high-temperature and high-energy ion implantation. Fig.14 As shown, the second doped region 14 is a p-region.

[0136] Then, see Fig.15 A third doping region 15 having the same conductivity type as the second doping region 14 and a greater doping concentration than the second doping region 14 can be formed from the surface of the second doping region 14 away from the silicon carbide body 1 toward the silicon carbide body 1, for example, by high-temperature and high-energy ion implantation. Fig.15 As shown, the third doped region 15 is a p+ region.

[0137] Next, see Fig.16 The first trench 11 and the second trench 17 can be formed in sequence from the surface of the shielding area 12 away from the silicon carbide body 1 toward the silicon carbide body 1 by, for example, dry etching or wet etching. The distance between the bottom of the second trench 17 and the second surface 1B is greater than the distance between the bottom of the first trench 11 and the second surface 1B.

[0138] Next, see Fig.17 A metal isolation layer 16 can be grown at a position between two adjacent first grooves 11, on the silicon carbide body 1 exposed by forming the first groove 11 and the second groove 17, by, for example, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or the like.

[0139] Then, see Fig.18 A metal such as nickel Ni is deposited on the surface of the shielding region 12 and the third doping region 15 away from the silicon carbide body 1 by means of evaporation or sputtering and subjected to high-temperature annealing, so that the metal and the shielding region 12 and the third doping region 15 which are p+ regions form a metal silicon compound with lower contact resistivity, such as NiSi alloy, to serve as the metal electrode layer 3.

[0140] Next, see Fig.19, a portion of the metal isolation layer 16 can be removed by an etching process, and only the metal isolation layer 16 located on the side wall of the first trench 11 is retained.

[0141] Finally, see Fig.11 , metal is deposited on the metal electrode layer 3 , the metal isolation layer 16 and the silicon carbide body 1 to form a metal contact layer 2 .

[0142] It is understood that the above process is only exemplary, and other process sequences may be used to form a semiconductor device. For example, the first doping region 13, the second doping region 14, and the third doping region 15 may be formed layer by layer by deposition. For another example, after forming the first trench 11, the shielding region 12 may be formed by ion implantation. The specific process flow is not described in detail here.

[0143] Some embodiments of the present disclosure also provide a semiconductor device. The semiconductor device includes a silicon carbide body 1. Figure 5 The silicon carbide body 1 includes: a plurality of first grooves 11, the first grooves 11 extend from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1, and have side walls and a bottom; a shielding area 12, the shielding area 12 extends from the bottom of the first groove 11 into the silicon carbide body 1; a metal contact layer 2, the metal contact layer 2 covers the first surface 1A and fills the first groove 11, and the metal contact layer 2 forms a Schottky junction with the silicon carbide body 1 by contacting the side walls and / or the first surface 1A of the first groove 11.

[0144] In some embodiments of the present disclosure, see Figure 6 The semiconductor device further includes two first doping regions 13 located on the first surface 1A, wherein the plurality of first grooves 11 are located between the two first doping regions 13, the first doping region 13 has the same conductivity type as the silicon carbide body 1 and has a doping concentration less than that of the silicon carbide body 1, and the shielding region 12 is located between the first doping region 13 and the metal contact layer 2.

[0145] In some embodiments of the present disclosure, see Figure 7 The semiconductor device further includes a second doping region 14 formed on a side of the first doping region 13 away from the silicon carbide body 1, wherein:

[0146] The second doping region 14 has the same conductivity type as the shielding region 12 and has a doping concentration lower than that of the shielding region 12 .

[0147] In some embodiments of the present disclosure, see Figure 8 The semiconductor device further includes a third doping region 15 having the same conductivity type as the second doping region 14 and a doping concentration greater than that of the second doping region 14 , wherein the second doping region 14 is located between the first doping region 13 and the third doping region 15 .

[0148] In some embodiments of the present disclosure, the shielding region 12 is formed to extend from the sidewall of the first trench 11 into the silicon carbide body 1 and the shielding region 12 is located between the third doping region 15 and the metal contact layer 2 .

[0149] In some embodiments of the present disclosure, see Fig. 9 The semiconductor device further includes: a metal isolation layer 16 formed on a side wall of each of any two adjacent first trenches 11, wherein the metal isolation layers 16 on the side walls of any two adjacent first trenches 11 are adjacent to each other, and the metal isolation layer 16 is located between the metal contact layer 2 and the side walls of the first trench 11.

[0150] In some embodiments of the present disclosure, see Fig.10 The semiconductor device further includes: a metal electrode layer 3 having a work function lower than that of the metal contact layer 2 , wherein the metal electrode layer 3 is located between the metal contact layer 2 and the shielding region 12 and / or between the metal contact layer 2 and the third doping region 15 .

[0151] In some embodiments of the present disclosure, see Fig.11 The semiconductor device further includes: a second trench 17 formed between any two adjacent first trenches 11 among the plurality of first trenches 11 , wherein the second trench 17 connects the two first trenches 11 .

[0152] It should be understood that the semiconductor device can be configured to carry a load current to be fed to a load and / or provided by a power supply, respectively. For example, the semiconductor device may include: one or more active power unit cells, such as a monolithic integrated diode cell. Such a diode cell and / or such a transistor cell can be integrated in a power semiconductor module. The semiconductor device structure provided in each embodiment of the present disclosure can be used as a cell. A plurality of such cells can constitute a cell field arranged together with the active area of ​​the power semiconductor device.

[0153] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0154] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a silicon carbide body (1); forming a plurality of first grooves (11) extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1), wherein the first grooves (11) have side walls and a bottom; forming a shielding region (12) extending from the bottom of the first trench (11) into the silicon carbide body (1); forming a metal contact layer (2), wherein the metal contact layer (2) covers the first surface (1A) and fills the first trench (11), and the metal contact layer (2) forms a Schottky junction with the silicon carbide body (1) by contacting the side wall of the first trench (11) and / or the first surface (1A), Before forming the metal contact layer (2), the method further comprises: forming two first doping regions (13) on the first surface (1A), wherein: The plurality of first trenches (11) are located between the two first doping regions (13), The first doping region (13) has the same conductivity type as the silicon carbide body (1) and has a doping concentration lower than that of the silicon carbide body (1). The shielding region (12) is located between the first doping region (13) and the metal contact layer (2).

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further comprises: A second doping region (14) having the same conductivity type as the shielding region (12) and a lower doping concentration than the shielding region (12) is formed on a side of the first doping region (13) away from the silicon carbide body (1).

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The method further comprises: forming a third doping region (15) having the same conductivity type as the second doping region (14) and a doping concentration greater than that of the second doping region (14), wherein the second doping region (14) is located between the first doping region (13) and the third doping region (15).

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The shielding region (12) is formed to extend from the side wall of the first trench (11) into the silicon carbide body (1), and the shielding region (12) is located between the third doping region (15) and the metal contact layer (2).

5. The method for manufacturing a semiconductor device according to claim 3 or 4, characterized in that: Before forming the metal contact layer (2), the method further comprises: forming a metal isolation layer (16) on a side wall of each first trench (11) of any two adjacent first trenches (11), wherein the metal isolation layers (16) on the side walls of the any two adjacent first trenches (11) are adjacent to each other, and the metal isolation layer (16) is located between the metal contact layer (2) and the side wall of the first trench (11).

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Before forming the metal contact layer (2), the method further comprises: forming a metal electrode layer (3) having a work function lower than that of the metal contact layer (2), Wherein, the metal electrode layer (3) is located between the metal contact layer (2) and the shielding region (12) and / or between the metal contact layer (2) and the third doping region (15).

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: The method further comprises: forming a second groove (17) between any two adjacent first grooves (11) among the plurality of first grooves (11), wherein the second groove (17) connects the two adjacent first grooves (11).

8. A semiconductor device, characterized in that: The semiconductor device comprises a silicon carbide body (1), wherein the silicon carbide body (1) comprises: A plurality of first grooves (11), the first grooves (11) extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1) and having side walls and a bottom; A shielding region (12), the shielding region (12) extending from the bottom of the first groove (11) into the silicon carbide body (1); a metal contact layer (2), the metal contact layer (2) covering the first surface (1A) and filling the first groove (11), and the metal contact layer (2) forming a Schottky junction with the silicon carbide body (1) by contacting the side wall of the first groove (11) and / or the first surface (1A); The semiconductor device further comprises two first doping regions (13) located on the first surface (1A), wherein: The plurality of first trenches (11) are located between the two first doping regions (13), The first doping region (13) has the same conductivity type as the silicon carbide body (1) and has a doping concentration lower than that of the silicon carbide body (1). The shielding region (12) is located between the first doping region (13) and the metal contact layer (2).

9. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises a second doping region (14) formed on a side of the first doping region (13) away from the silicon carbide body (1), wherein the second doping region (14) has the same conductivity type as the shielding region (12) and has a doping concentration less than that of the shielding region (12).

10. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises a third doping region (15) having the same conductivity type as the second doping region (14) and a greater doping concentration than the second doping region (14), wherein the second doping region (14) is located between the first doping region (13) and the third doping region (15).

11. The semiconductor device according to claim 10, characterized in that The shielding region (12) is formed to extend from the side wall of the first trench (11) into the silicon carbide body (1), and the shielding region (12) is located between the third doping region (15) and the metal contact layer (2).

12. The semiconductor device according to claim 10 or 11, characterized in that: The semiconductor device further comprises: a metal isolation layer (16) formed on a side wall of each first trench (11) of any two adjacent first trenches (11), wherein the metal isolation layers (16) on the side walls of the any two adjacent first trenches (11) are adjacent to each other, and the metal isolation layer (16) is located between the metal contact layer (2) and the side wall of the first trench (11).

13. The semiconductor device according to claim 12, characterized in that The semiconductor device further comprises: a metal electrode layer (3) having a work function lower than that of the metal contact layer (2), Wherein, the metal electrode layer (3) is located between the metal contact layer (2) and the shielding region (12) and / or between the metal contact layer (2) and the third doping region (15).

14. The semiconductor device according to any one of claims 8 to 11, characterized in that The semiconductor device further comprises: a second trench (17) formed between any two adjacent first trenches (11) among the plurality of first trenches (11), wherein the second trench (17) connects the two first trenches (11).

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