A resistance adjustment network and integrated circuit for LDO

Abstract

The present invention discloses a resistor trimming network and integrated circuit applied to LDO, the network includes a low-order resistor trimming module, a high-order resistor trimming module and two sets of decoders, wherein the low-order resistor trimming module includes multiple low-order resistors and multiple first MOS switches, and the high-order resistor trimming module includes multiple high-order resistors and multiple second MOS switches; the two sets of decoders are used to control the low-order resistor trimming module and the high-order resistor trimming module respectively. The present invention greatly reduces the use of control ports by using encoders; the present invention fixedly introduces two switch on-impedances, so that the unit step change of the trimming is the same, and the output is less affected by the TC change of the switch; the present invention realizes resistor multiplexing, reduces the area occupied by some resistors of the resistor trimming network, and improves the matching degree of the layout.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a resistance trimming network and an integrated circuit applied to LDO. Background Art

[0002] In high-speed and high-precision ADC (Analog-Digital-converter) circuits, high-precision LDO (Low Dropout Regulator) is an indispensable part. LDO linear regulators have the advantages of low power consumption, low noise, simple structure, etc. and are widely used in various electronic devices. Since the input signal of LDO is affected by the deviation of BG (Bandgap) output voltage and the offset deviation of the error amplifier, it will cause a certain error in the absolute value of the LDO output signal. At this time, it is particularly important to add a trimming circuit to deal with the deviation of the LDO output signal.

[0003] When the trimming circuit is introduced into the integrated circuit, the deviation of the resistor network itself will cause deviation in the final output voltage, resulting in various effects such as inaccurate absolute value of circuit output, substandard temperature compensation (TC) variation, poor power supply rejection, complex logic, huge area loss, etc. Therefore, it is very necessary to reasonably design a high-precision resistor trimming solution for LDO output.

[0004] At present, there are three commonly used resistance trimming schemes. The first is a traditional binary resistance trimming network, in which the trimming resistors in the resistance trimming network are distributed according to binary proportional impedance, and m switches are used to achieve The second type is a switch parallel binary resistor adjustment network. This resistor adjustment network reduces the on-resistance of the switch introduced into the circuit by connecting a single switch in parallel to multiple consecutive closed switches, thereby reducing the step deviation of the adjustment and the influence of the switch TC on the output. However, this resistor adjustment network has too many switch control bits in parallel, making the adjustment scheme particularly complicated. The third type is a resistor adjustment network that sets the adjustment switch at the gate of the error operational amplifier. This resistor adjustment network can ignore the on-resistance of the introduced switch by setting the switch at the gate of the error amplifier, and adjust the circuit without considering the influence of the switch on-resistance on the output. Although this method eliminates the influence of the switch on-resistance on the output voltage, it requires a relatively precise proportional resistance of the circuit. The proportional resistance setting is often cumbersome, which will affect the matching problem of the subsequent circuit. In addition, a large number of switches are used, resulting in a large number of control bits, making the adjustment more complicated. Summary of the invention

[0005] The object of the present invention is to provide a resistance trimming network and an integrated circuit for LDO in view of the deficiencies of the prior art.

[0006] The object of the present invention is achieved through the following technical solutions: In a first aspect, an embodiment of the present invention provides a resistance trimming network applied to LDO, comprising: a low resistance trimming module, a high resistance trimming module and two sets of decoders, wherein the low resistance trimming module comprises A low resistance and A first MOS switch, the high-level resistance adjustment module includes A high resistance and a second MOS switch; wherein n represents the number of adjustment control bits, and n is an even number;

[0007] In the low resistance adjustment module, low-level resistors are connected in series; the initial end of the first low-level resistor is connected to the source of the first first MOS switch, the connection node between two adjacent low-level resistors is connected to the source of a first MOS switch, and the end of the last low-level resistor is connected to the source of the last first MOS switch; The drains of the first MOS switches are connected together;

[0008] In the high resistance adjustment module, high-level resistors are connected in series; the initial end of the first high-level resistor is connected to the source of the first second MOS switch, the connection node between two adjacent high-level resistors is connected to the source of a second MOS switch, and the end of the last high-level resistor is connected to the source of the last second MOS switch; The drains of the second MOS switches are connected together;

[0009] Wherein, the drain of the last first MOS switch is connected to the source of the first second MOS switch; The gates of the first MOS switches are respectively connected to the output terminals of a group of decoders. The gates of the second MOS switches are respectively connected to the output ends of another group of decoders, and the input ends of the two groups of decoders are connected to the control signals input from the outside.

[0010] Furthermore, the adjustment range of the resistance adjustment network is (0- )R.

[0011] Furthermore, the number of adjustment control bits n is determined by the overall range of adjustment and the unit step size of adjustment.

[0012] Furthermore, the selection of the decoder is determined by the following method:

[0013] The number of input terminals and the number of output terminals of the decoder are determined according to the number of adjustment control bits n, and the decoder is determined according to the number of input terminals and the number of output terminals.

[0014] Furthermore, the low-order resistor is R, and the high-order resistor is determined by the output of the decoder.

[0015] Furthermore, the first MOS switch and the second MOS switch are both P-type MOS tubes.

[0016] A second aspect of an embodiment of the present invention provides an integrated circuit, comprising the above-mentioned resistance trimming network applied to LDO.

[0017] The beneficial effects of the present invention are as follows: the present invention fixedly introduces two switch on-impedances, so that the unit step change of the adjustment is the same, and the output is less affected by the TC change of the switch; the present invention solves the problem that in the process of adjustment of the traditional resistance adjustment network, the unit step change deviation is too large due to the change in the number of switch on-impedances and the TC change of the output voltage VREF is serious due to the introduction of too many switches; the present invention greatly reduces the use of control ports by using encoders; the present invention uses the proportional design of resistors, so that in the process of improving the adjustment range, the number of switches increases relatively less, and a large range of regulation is achieved; the present invention realizes resistor reuse, reduces the area occupied by some resistors in the resistance adjustment network, and improves the matching degree of the layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of a circuit structure in which the resistance trimming network described in the present invention is applied to an LDO;

[0019] Figure 2 is a structural schematic diagram of a resistance trimming network provided by an embodiment of the present invention;

[0020] Figure 3 is a structural schematic diagram of a resistance trimming network provided by an embodiment of the present invention;

[0021] Figure 4 It is another structural schematic diagram of the resistance trimming network provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0023] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "the" and "the" used in the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0024] It should be understood that although the terms first, second, third, etc. may be used in the present invention to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0025] The present invention is described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0026] See also Figure 2-Figure 4 The resistance adjustment network applied to LDO of the present invention comprises a low resistance adjustment module, a high resistance adjustment module and two sets of decoders. The low resistance adjustment module comprises A low resistance and A first MOS switch, a high resistance trimming module includes A high resistance and A second MOS switch; wherein n represents the number of adjustment control bits, n is an even number, and the adjustment range corresponding to the resistor adjustment network is (0- )R.

[0027] In this embodiment, in the low resistance adjustment module, low-level resistors are connected in series; the initial end of the first low-level resistor is connected to the source of the first first MOS switch, the connection node between two adjacent low-level resistors is connected to the source of a first MOS switch, and the end of the last low-level resistor is connected to the source of the last first MOS switch; The drains of the first MOS switches are connected together. In the high-level resistance trimming module, high-level resistors are connected in series; the initial end of the first high-level resistor is connected to the source of the first second MOS switch, the connection node between two adjacent high-level resistors is connected to the source of a second MOS switch, and the end of the last high-level resistor is connected to the source of the last second MOS switch; The drains of the second MOS switches are connected together. The drain of the last first MOS switch is connected to the source of the first second MOS switch. The gates of the first MOS switches are respectively connected to the output terminals of a group of decoders. The gates of the second MOS switches are respectively connected to the output ends of the other decoders, and the input ends of the two decoders are connected to the control signals input from the outside. The two decoders respectively control the low resistance trimming module and the high resistance trimming module to form an n-bit binary code. Thus, during use, one decoder controls the MOS switch of the low resistance trimming module or the high resistance trimming module. Since one decoder will only turn on one MOS switch, the application circuit of the resistance trimming network will be fixedly introduced with two on-resistances. During the circuit trimming process, the unit step will not change, and the trimming range of the n-bit control is (0- )R’s resistance trimming network.

[0028] Furthermore, the number of adjustment control bits n is determined by the overall range of adjustment and the unit step size (precision) of adjustment.

[0029] Furthermore, the selection of the decoder is determined by the following method: the number of input terminals and the number of output terminals of the decoder are determined according to the number of adjustment control bits n, and the decoder is determined according to the number of input terminals and the number of output terminals. For example, n=4, then the number of input terminals of a decoder is , the number of its output terminals is , so we choose 2-4 decoder; for another example, n=8, then the number of input terminals of a decoder is , the number of its output terminals is , so the 4-16 decoder is selected.

[0030] It should be understood that the resistance trimming network described in the present invention is applied to the circuit of LDO. Compared with the existing resistance trimming network, the resistance trimming network described in the present invention utilizes 2-4 decoders, 3-8 decoders, and 4-16 decoders, which can reduce the use of control ports. The low-order resistance trimming module and the high-order resistance trimming module are controlled by two groups of decoders, so that the circuit fixedly introduces the on-impedance of two MOS switches, and this on-impedance does not change during the trimming change process, which makes the trimming step uniform, reduces the output TC change, and greatly improves the trimming accuracy; and the resistor ratio used is relatively simple and reused, so that the circuit matching is convenient.

[0031] Furthermore, the low-order resistor is R, and the high-order resistor is determined by the output of the decoder. For example, if the decoder is a 3-8 decoder, the high-order resistor is 8R; if the decoder is a 2-4 decoder, the high-order resistor is 4R; if the decoder is a 4-16 decoder, the high-order resistor is 16R.

[0032] Furthermore, since the voltage output by the LDO is high and the on-resistance of a P-type MOS tube is low, the first MOS switch and the second MOS switch are preferably P-type MOS tubes.

[0033] When the output voltage of the LDO circuit deviates due to process and other reasons, it is necessary to use the resistance trimming network described in the present invention to trim it, determine the trimming range according to actual needs, and further determine the trimming control bit number n according to the overall trimming range and the trimming unit step size (precision).

[0034] For example, based on the above embodiment, it is determined that the number of adjustment control bits n=8, and the corresponding resistance adjustment network is as follows: Figure 4 As shown, the resistor trimming network has a trimming range of (0- )R, that is, 0-255R. Figure 4 As shown, the resistance trimming network includes a low resistance trimming module, a high resistance trimming module and two groups of 4-16 decoders. The low resistance trimming module includes A low-level resistor R and A first MOS switch, a high resistance trimming module includes A high-level resistor 16R and A second MOS switch. In the low-level resistance adjustment module, 15 low-level resistors R are connected in series, the initial end of the first low-level resistor R is connected to the source of the first first MOS switch, the connection node between two adjacent low-level resistors R is connected to the source of a first MOS switch, and the end of the last low-level resistor R is connected to the source of the last first MOS switch; the drains of the 16 first MOS switches are connected together. In the high-level resistance adjustment module, 15 high-level resistors 16R are connected in series; the initial end of the first high-level resistor 16R is connected to the source of the first second MOS switch, the connection node between two adjacent high-level resistors 16R is connected to the source of a second MOS switch, and the end of the last high-level resistor 16R is connected to the source of the last second MOS switch; the drains of the 16 second MOS switches are connected together. The drain of the last first MOS switch is connected to the source of the first second MOS switch to realize the connection between the low-level resistance adjustment module and the high-level resistance adjustment module. The gates of the 16 first MOS switches are respectively connected to the output ends of a group of 4-16 decoders, that is, the gates of the first MOS switches K1-K16 are respectively connected to the output ends K1-K16 of a group of 4-16 decoders; the gates of the 16 second MOS switches are respectively connected to the output ends of another group of 4-16 decoders, that is, the gates of the second MOS switches T1-T16 are respectively connected to the output ends T1-T16 of another group of 4-16 decoders; the input ends A1-A8 of the two groups of 4-16 decoders are connected to the control signals input from the outside. Two groups of 4-16 decoders control the low-order resistance trimming module and the high-order resistance trimming module respectively to form an 8-bit binary code. Therefore, during use, one group of 4-16 decoders controls the first MOS switch in the low-order resistance trimming module, and the other group of 4-16 decoders controls the second MOS switch in the high-order resistance trimming module. Since one group of 4-16 decoders will only turn on one MOS switch, the application circuit of the resistance trimming network will introduce the on-impedance of two MOS switches. During the circuit trimming process, the unit step will not change, and it will be equipped with an 8-bit controlled 0-255R resistance trimming network. The two groups of 4-16 decoders are respectively in the front and back 4 bits of the 8-bit binary code, thereby realizing the 8-bit binary code. The truth table of the first 4 bits of the 4-16 decoder is shown in Table 1.

[0035] Table 1: Truth table of the first 4 bits of the 4-16 decoder

[0036]

[0037] As can be seen from Table 1, the 4-16 decoder of the first 4 bits, i.e., the 4-16 decoder connected to the low-bit resistance trimming module, realizes the trimming control of the resistance 0-15R by connecting the external input control signal to the input terminals A1-A4 of the 4-16 decoder. The first MOS switch and the second MOS switch both use P-type MOS tubes, which helps to reduce the on-resistance of the P-type MOS tube. At this time, when the external input control signal A is displayed as 0, it is actually a high-bit signal, and when the control signal A is displayed as 1, it is actually a low-bit signal, that is, a low-level trigger. The first 4 bits of the 4-16 decoder control the resistance combination of 0-15R (i.e., the low-order resistance trimming module), that is, the first 4 bits of the 4-16 decoder control the introduction of 15 low-order resistors R; the last 4 bits of the 4-16 decoder control the control combination of the 16R resistance network (i.e., the high-order resistance trimming module), that is, the last 4 bits of the 4-16 decoder control the introduction of 15 high-order resistors 16R; every time the last 4 bits are added by 1, a high-order resistor 16R is added, thereby realizing an 8-bit 0-255R resistance trimming network.

[0038] For example, based on the above embodiment, it is determined that the number of adjustment control bits n=4, and the corresponding resistance adjustment network is as follows: Figure 4 As shown, the resistor trimming network has a trimming range of (0- )R, that is, 0-15R. Figure 2 As shown, the resistance trimming network includes a low resistance trimming module, a high resistance trimming module and two groups of 2-4 decoders. The low resistance trimming module includes A low-level resistor R and A first MOS switch, a high resistance trimming module includes A high-level resistor 4R and A second MOS switch. Among them, in the low-level resistance adjustment module, three low-level resistors R are connected in series, the initial end of the first low-level resistor R is connected to the source of the first first MOS switch, the connection node between two adjacent low-level resistors R is connected to the source of a first MOS switch, and the end of the last low-level resistor R is connected to the source of the last first MOS switch; the drains of the four first MOS switches are connected together. In the high-level resistance adjustment module, three high-level resistors 4R are connected in series; the initial end of the first high-level resistor 4R is connected to the source of the first second MOS switch, the connection node between two adjacent high-level resistors 4R is connected to the source of a second MOS switch, and the end of the last high-level resistor 4R is connected to the source of the last second MOS switch; the drains of the four second MOS switches are connected together. The drain of the last first MOS switch is connected to the source of the first second MOS switch to realize the connection between the low-level resistance adjustment module and the high-level resistance adjustment module. The gates of the four first MOS switches are respectively connected to the output ends of a group of 2-4 decoders, that is, the gates of the first MOS switches K1-K4 are respectively connected to the output ends K1-K4 of a group of 2-4 decoders; the gates of the four second MOS switches are respectively connected to the output ends of another group of 2-4 decoders, that is, the gates of the second MOS switches T1-T4 are respectively connected to the output ends T1-T4 of another group of 2-4 decoders; the input ends A1-A4 of the two groups of 2-4 decoders are connected to the control signals input from the outside. Two groups of 2-4 decoders control the low-bit resistor trimming module and the high-bit resistor trimming module respectively to form a 4-bit binary code. Therefore, during use, one group of 2-4 decoders controls the first MOS switch in the low-bit resistor trimming module, and the other group of 2-4 decoders controls the second MOS switch in the high-bit resistor trimming module. Since one group of 2-4 decoders will only turn on one MOS switch, the application circuit of the resistor trimming network will be fixedly introduced with the on-impedance of the two MOS switches. During the circuit trimming process, the unit step will not change, and thus a 4-bit controlled 0-15R resistor trimming network is configured. The two groups of 2-4 decoders are respectively located in the front and rear 4 bits of the 4-bit binary code, thereby realizing a 4-bit binary code. The 2-4 decoders of the first 4 bits, i.e., the 2-4 decoders connected to the low-bit resistor trimming module, realize the trimming control of the resistor 0-3R by connecting the external input control signal to the input terminal A1-A2 of the 2-4 decoder. The first two bits of the 2-4 decoder control the 0-3R resistance combination (i.e., the low-order resistance trimming module), that is, the first two bits of the 2-4 decoder control the introduction of three low-order resistors R; the last four bits of the 2-4 decoder control the 4R resistance network control combination (i.e., the high-order resistance trimming module), that is, the last two bits of the 2-4 decoder control the introduction of three high-order resistors 4R; every time the last four bits are added by 1, a high-order resistor 4R is added, thereby realizing a 4-bit 0-15R resistance trimming network.

[0039] For example, an embodiment of the present invention further provides a resistance adjustment network, the structure of which is as follows: Figure 3 As shown, the resistance adjustment network includes a low-order resistance adjustment module, a high-order resistance adjustment module and two groups of 3-8 decoders. The low-order resistance adjustment module includes 7 low-order resistors R and 8 first MOS switches, and the high-order resistance adjustment module includes 7 high-order resistors 8R and 8 second MOS switches. In the low-order resistance adjustment module, the 7 low-order resistors R are connected in series, the initial end of the first low-order resistor R is connected to the source of the first first MOS switch, the connection node between two adjacent low-order resistors R is connected to the source of a first MOS switch, and the end of the last low-order resistor R is connected to the source of the last first MOS switch; the drains of the 8 first MOS switches are connected together. In the high-order resistance adjustment module, the 7 high-order resistors 8R are connected in series; the initial end of the first high-order resistor 8R is connected to the source of the first second MOS switch, the connection node between two adjacent high-order resistors 8R is connected to the source of a second MOS switch, and the end of the last high-order resistor 8R is connected to the source of the last second MOS switch; the drains of the 8 second MOS switches are connected together. The drain of the last first MOS switch is connected to the source of the first second MOS switch to realize the connection between the low resistance trimming module and the high resistance trimming module. The gates of the eight first MOS switches are respectively connected to the output ends of a group of 3-8 decoders, that is, the gates of the first MOS switches K1-K8 are respectively connected to the output ends K1-K8 of a group of 3-8 decoders; the gates of the eight second MOS switches are respectively connected to the output ends of another group of 3-8 decoders, that is, the gates of the second MOS switches T1-T8 are respectively connected to the output ends T1-T8 of another group of 3-8 decoders; the input ends A1-A6 of the two groups of 3-8 decoders are connected to the control signals input from the outside. Two groups of 3-8 decoders control the low-order resistance adjustment module and the high-order resistance adjustment module respectively, forming a 6-bit binary code. Therefore, during use, one group of 3-8 decoders controls the first MOS switch in the low-order resistance adjustment module, and the other group of 3-8 decoders controls the second MOS switch in the high-order resistance adjustment module. Since one group of 3-8 decoders will only turn on one MOS switch, the application circuit of the resistance adjustment network will introduce fixed on-impedances of two MOS switches. During the circuit adjustment process, the unit step will not change, thereby forming a 6-bit controlled 0-63R resistance adjustment network. The two groups of 3-8 decoders are respectively located in the front and back 4 bits of the 6-bit binary code, thereby realizing a 6-bit binary code. Figure 3 The resistance trimming network shown has a trimming control bit number n=6, and a trimming range of 0-63R.

[0040] It is worth mentioning that, based on the above-mentioned resistor trimming network applied to LDO, an embodiment of the present invention further provides an integrated circuit, which includes the resistor trimming network applied to LDO in the above-mentioned embodiment.

[0041] Through the above examples, the resistance adjustment network applied to LDO provided by the present invention includes: a low resistance adjustment module, a high resistance adjustment module and two sets of decoders, wherein the low resistance adjustment module includes A low resistance and A first MOS switch, a high resistance trimming module includes A high resistance and A second MOS switch is provided, and the drain of the last first MOS switch in the low resistance trimming module is connected to the source of the first second MOS switch in the high resistance trimming module to realize the connection between the low resistance trimming module and the high resistance trimming module.

[0042] The external control signals are connected to the input terminals of the two sets of decoders, and the closing or opening of the plurality of first MOS switches and the plurality of second MOS switches are controlled by the external control signals, thereby changing the resistance values ​​of the low resistance trimming module and the high resistance trimming module, thereby trimming the output voltage of the LDO.

[0043] Figure 1 This is an example of an integrated circuit, which includes a resistor trimming network applied to LDO, and the circuit can achieve output voltage trimming. The circuit includes an operational amplifier, two resistors R1 and R2, the resistor trimming network TRIM of the present invention, a PMOS tube, a Miller compensation capacitor Cc, a zero adjustment resistor RZ, a load capacitor CL and an equivalent resistor ESR. Among them, the positive end of the operational amplifier is connected to the input voltage VBG, the resistor R1 is connected in series with the resistor R2, and the negative end of the operational amplifier is connected between the resistor R1 and the resistor R2; one end of TRIM is connected to the upper end of the resistor R2, and the other end of TRIM is connected to the drain of the PMOS tube; the output end of the operational amplifier is connected to the gate of the PMOS tube, and the Miller compensation capacitor Cc and the zero adjustment resistor RZ are connected between the output end of the operational amplifier and the drain of the PMOS tube, and the source of the PMOS tube is connected to its power supply voltage VDD; the other end of the resistor R1 is grounded; the load capacitor CL and the equivalent resistor ESR are connected between the drain of the PMOS tube and the ground, and the load capacitor CL and the equivalent resistor ESR are connected in series; the drain of the PMOS tube is the output voltage VREF of the circuit.

[0044] Taking the trimming of the output voltage VREF as an example, the input voltage VBG is clamped between the resistors R1 and R2 by the short-circuited positive and negative input terminals of the operational amplifier, thereby realizing the output voltage VREF=VBG*[(R2+TRIM+R1) / R1]. Since the process deviation will cause the output voltage VREF to deviate, TRIM is added to offset the deviation caused by the process through the change of TRIM. For example: when the output voltage VREF deviation caused by the process is 80mv, the unit step is required to be within 350uv, and the TRIM range can be selected to use an 8-bit 0-255R trimming range, so that the unit step is 312.5uv, which meets the design requirements.

[0045] The resistance adjustment network applied to LDO proposed in the present invention is different from the structure of the conventional binary resistance adjustment network and the switch parallel binary resistance adjustment network. The use of two sets of decoders can reduce the use of control ports. The two sets of decoders are used to control the low resistance adjustment module and the high resistance adjustment module, so that the circuit fixedly introduces the on-impedance of two switches, and the on-impedance will not change during the adjustment process, so that the unit step change of the adjustment is the same, and the TC change of the output voltage received by the switch is small, so that the adjustment accuracy is greatly improved, and the problem of excessive unit step change deviation caused by the change of the number of switch on-impedances in the traditional resistance adjustment network during the adjustment process, and the serious TC change of the output voltage caused by the introduction of too many switches. In addition, the resistance ratio used is relatively simple, so that the number of MOS switches increases relatively little during the process of improving the adjustment range, and a wide range of regulation is achieved; in addition, the resistor reuse is achieved, the area occupied by some resistors of the resistance adjustment network is reduced, and the layout matching degree is improved, which has high practicality.

[0046] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0047] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A resistance trimming network applied to LDO, characterized in that: include: A low resistance trimming module, a high resistance trimming module and two sets of decoders, wherein the low resistance trimming module includes 2 n / 2 - 1 low level resistor and 2 n / 2 A first MOS switch, the high-level resistance adjustment module includes 2 n / 2 - 1 high resistor and 2 n / 2 a second MOS switch; wherein n represents the number of adjustment control bits, and n is an even number; In the low resistance adjustment module, 2 n / 2 - 1 low-level resistor is connected in series; the initial end of the first low-level resistor is connected to the source of the first first MOS switch, the connection node between two adjacent low-level resistors is connected to the source of a first MOS switch, and the end of the last low-level resistor is connected to the source of the last first MOS switch; 2 n / 2 The drains of the first MOS switches are connected together; In the high resistance adjustment module, 2 n / 2 - 1 high-bit resistor connected in series; the initial end of the first high-bit resistor is connected to the source of the first second MOS switch, the connection node between two adjacent high-bit resistors is connected to the source of a second MOS switch, and the end of the last high-bit resistor is connected to the source of the last second MOS switch; 2 n / 2 The drains of the second MOS switches are connected together; Wherein, the drain of the last first MOS switch is connected to the source of the first second MOS switch; 2 n / 2 The gates of the first MOS switches are respectively connected to the output terminals of a group of decoders. n / 2 The gates of the second MOS switches are respectively connected to the output terminals of another set of decoders, and the input terminals of the two sets of decoders are connected to the control signals input from the outside; The low-order resistor is R, and the high-order resistor is determined by the output of the decoder; the unit resistance of the high-order resistor is 2 times the unit resistance of the low-order resistor. n / 2 times; The resistance adjustment network has an adjustment range of (0-2 n -1)R.

2. The resistance trimming network for LDO according to claim 1, characterized in that: The number of adjustment control bits n is determined by the overall range of adjustment and the unit step size of adjustment.

3. The resistance trimming network for LDO according to claim 1, characterized in that: The selection of the decoder is determined by the following method: The number of input terminals and the number of output terminals of the decoder are determined according to the number of adjustment control bits n, and the decoder is determined according to the number of input terminals and the number of output terminals.

4. The resistance trimming network for LDO according to claim 1, characterized in that: The first MOS switch and the second MOS switch are both P-type MOS tubes.

5. An integrated circuit, characterized in that: The invention comprises a resistance trimming network applied to an LDO as claimed in any one of claims 1 to 4.

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