A vertical normally-off GaN composite JFET device and its preparation method

Abstract

The present invention discloses a vertical normally-off GaN composite JFET device and a preparation method thereof, which relates to the field of semiconductor technology, and includes a drain metal, wherein an n-type SiC substrate, an n-type GaN, a first p-type GaN, a GaN channel layer, an AlGaN barrier layer, a second p-type GaN, a gate metal, an isolation dielectric, and a source metal are sequentially arranged above the drain metal. A high withstand voltage characteristic is achieved by adopting a vertical structure, which exceeds the traditional lateral GaN HEMT device. When the device is normally turned on, the two-dimensional electron gas at the interface of AlGaN and GaN and the common conduction of electrons in n-type GaN ensure low on-resistance and excellent current follow-flow capability; in addition, the on-off control of the device depends on the formation of the two-dimensional electron gas, and the generation of the two-dimensional electron gas is controlled by the gate voltage to achieve low driving loss and fast switching speed, which not only improves the efficiency of power supply applications, but also has excellent electrical characteristics.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a vertical normally-off GaN composite JFET device and a preparation method thereof. Background Art

[0002] As one of the representatives of wide bandgap semiconductor devices, GaN's HEMT device structure has the characteristics of low driving loss, low on-resistance and high operating frequency. However, compared with other wide bandgap semiconductor devices, its lateral structure limits its application in the high voltage field, and it is difficult to have the characteristics of withstand voltage above 600V and low conduction loss, low driving loss and high switching frequency.

[0003] The prior art mentions a vertically conductive GaN normally-off MISFET device and its manufacturing method. The electrons provided by the source of the device need to pass through the thickness of the heterojunction barrier layer to enter the two-dimensional electron gas region for continuous flow, and then pass through the undoped GaN layer to reach the n-type GaN layer. There is a large impedance when passing through the heterojunction barrier layer and the undoped GaN layer.

[0004] The source electrode in the present invention is directly in contact with the two-dimensional electron gas, and the electrons are directly connected to the two-dimensional electron gas from the source electrode, and the electrons are transmitted to the n-type GaN along the two-dimensional electron gas path, and the device has a small on-resistance. From the perspective of changing the lateral withstand voltage structure of the GaN device, a vertical device structure is used to improve the withstand voltage of the device, ensuring the low turn-on voltage and high switching speed characteristics of the two-dimensional electron gas, and improving the withstand voltage of the GaN switch-type device. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a vertical normally-off GaN composite JFET device and a method for preparing the same to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solution: a vertical normally-off GaN composite JFET device, comprising a drain metal, the drain metal being located at the bottom of the device, an n-type SiC substrate being disposed above the drain metal, an n-type GaN being disposed above the n-type SiC substrate, and a first p-type GaN being disposed above the n-type GaN;

[0007] A GaN channel layer is disposed above the first p-type GaN, a groove is disposed at the bottom of the GaN channel layer, an AlGaN barrier layer is disposed above the GaN channel layer, a second p-type GaN is disposed above the AlGaN barrier layer, and a gate metal is disposed above the second p-type GaN;

[0008] Isolation dielectrics are disposed on both sides of the gate metal and the second p-type GaN, and the isolation dielectrics are located above the AlGaN barrier layer. Source metals are disposed on both sides of the isolation dielectric, the AlGaN barrier layer, and the GaN channel layer, and the source metals are located above the first p-type GaN.

[0009] To further optimize the technical solution, a groove is provided above the first p-type GaN, the groove corresponds to the position of the groove of the GaN channel layer, so that the groove of the GaN channel layer is embedded in the groove, and the inclination angle of the groove of the GaN channel layer is set in the range of 60° to 90°.

[0010] To further optimize the technical solution, the thickness of the n-type SiC substrate is 2 μm, the thickness of the n-type GaN is 10 μm, the thickness of the first p-type GaN is 500 nm, the thickness of the GaN channel layer is 100 nm, the thickness of the AlGaN barrier layer is 20 nm, the thickness of the second p-type GaN layer is 100 nm, and the thickness of the gate metal is 100 nm.

[0011] Further optimizing the technical solution, the doping concentration of the n-type SiC substrate is 6×10 18 cm -3 The doping concentration of n-type GaN is 6×10 16 cm -3 , the doping concentration of the first p-type GaN is 1×10 18 cm -3 , the doping concentration of the second p-type GaN layer is 1×10 17 cm -3 .

[0012] To further optimize the technical solution, the GaN channel layer is intrinsic GaN, and the ratio of Al to GaN in the AlGaN barrier layer is in the range of 2:8 to 5:5.

[0013] To further optimize the technical solution, a two-dimensional electron gas is formed at the interface between the AlGaN barrier layer and the GaN channel layer.

[0014] Further optimize the technical solution, the withstand voltage level of the device is ≥900V, and the on-resistance of the device is ≤5×10 -4 Ω·cm.

[0015] To further optimize the technical solution, the source metal is in direct ohmic contact with the first p-type GaN, and the first p-type GaN and n-type GaN form a pn junction for conductivity, thereby forming a parasitic body diode.

[0016] A method for preparing a vertical normally-off GaN composite JFET device is prepared based on the vertical normally-off GaN composite JFET device, comprising the following steps:

[0017] S1. epitaxially grow a layer of n-type GaN on an n-type SiC substrate with a drain metal;

[0018] S2, depositing a layer of p-type GaN on the n-type GaN to form a first p-type GaN;

[0019] S3, depositing a barrier layer on the first p-type GaN, etching a through hole of the GaN channel layer groove, and etching to form a groove of the GaN channel layer, wherein the inclination of the groove is 60° to 90°;

[0020] S4, removing the barrier layer formed in step S3, depositing a new barrier layer on the first p-type GaN, etching a through hole for the GaN channel layer, and depositing a GaN channel layer;

[0021] S5, removing the barrier layer formed in step S4, depositing a new barrier layer on the GaN channel layer, etching a through hole of the AlGaN barrier layer, and depositing an AlGaN barrier layer;

[0022] S6, removing the barrier layer formed in step S5, depositing a new barrier layer on the AlGaN barrier layer, etching a through hole of a second p-type GaN, and depositing a layer of p-type GaN to form a second p-type GaN;

[0023] S7, removing the barrier layer formed in step S6, depositing a new barrier layer on the second p-type GaN layer, etching a through hole for the gate metal, and depositing the gate metal;

[0024] S8, removing the barrier layer formed in step S7, depositing a new barrier layer on the gate metal, etching a through hole for the isolation medium, and depositing an isolation medium;

[0025] S9, remove the barrier layer formed in step S8, deposit a new barrier layer on the gate metal, etch a through hole for the source metal, and deposit the source metal.

[0026] Compared with the prior art, the present invention provides a vertical normally-off GaN composite JFET device and a preparation method thereof, which has the following beneficial effects:

[0027] The vertical normally-off GaN composite JFET device and its preparation method achieve high withstand voltage characteristics by adopting a vertical structure, which exceeds the traditional lateral GaN HEMT device. When the device is normally turned on, the two-dimensional electron gas at the interface of AlGaN and GaN and the common conduction of electrons in n-type GaN ensure low on-resistance and excellent current follow-on capability. In addition, the on-off control of the device depends on the formation of the two-dimensional electron gas. The generation of the two-dimensional electron gas is controlled by the gate voltage to achieve low driving loss and fast switching speed, which not only improves the efficiency of power supply applications, but also has excellent electrical properties and is suitable for use in high-performance electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic cross-sectional view of a vertical normally-off GaN composite JFET device proposed by the present invention;

[0029] Figure 2 A schematic cross-sectional view of a device in step S1 of a method for preparing a vertical normally-off GaN composite JFET device proposed in the present invention;

[0030] Figure 3 A schematic cross-sectional view of a device in step S2 of a method for preparing a vertical normally-off GaN composite JFET device proposed in the present invention;

[0031] Figure 4 A schematic cross-sectional view of a device in step S3 of a method for preparing a vertical normally-off GaN composite JFET device proposed in the present invention;

[0032] Figure 5 A schematic cross-sectional view of a device in step S4 of a method for preparing a vertical normally-off GaN composite JFET device proposed by the present invention;

[0033] Figure 6 A schematic cross-sectional view of a device in step S5 of a method for preparing a vertical normally-off GaN composite JFET device proposed by the present invention;

[0034] Figure 7 A schematic cross-sectional view of a device in step S6 of a method for preparing a vertical normally-off GaN composite JFET device proposed by the present invention;

[0035] Figure 8 A schematic cross-sectional view of a device in step S7 of a method for preparing a vertical normally-off GaN composite JFET device proposed in the present invention;

[0036] Fig. 9 A schematic cross-sectional view of a device in step S8 of a method for preparing a vertical normally-off GaN composite JFET device proposed in the present invention;

[0037] Fig.10 It is a schematic cross-sectional view of a device in step S9 of a method for preparing a vertical normally-off GaN composite JFET device proposed in the present invention.

[0038] In the figure: 1. drain metal; 2. n-type SiC substrate; 3. n-type GaN; 4. first p-type GaN; 5. GaN channel layer; 6. AlGaN barrier layer; 7. second p-type GaN; 8. gate metal; 9. isolation dielectric; 10. source metal. DETAILED DESCRIPTION

[0039] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example

[0040] See also Figure 1 A vertical normally-off GaN composite JFET device comprises a drain metal 1, wherein the drain metal 1 is located at the bottom of the device, an n-type SiC substrate 2 is arranged above the drain metal 1, an n-type GaN 3 is arranged above the n-type SiC substrate 2, and a first p-type GaN 4 is arranged above the n-type GaN 3.

[0041] A GaN channel layer 5 is arranged above the first p-type GaN 4, a groove is arranged at the bottom of the GaN channel layer 5, an AlGaN barrier layer 6 is arranged above the GaN channel layer 5, a second p-type GaN 7 is arranged above the AlGaN barrier layer 6, and a gate metal 8 is arranged above the second p-type GaN 7.

[0042] Wherein, a two-dimensional electron gas (such as Figure 1 ).

[0043] Isolation dielectric 9 is provided on both sides of the gate metal 8 and the second p-type GaN 7, and the isolation dielectric 9 is located above the AlGaN barrier layer 6. Source metal 10 is provided on both sides of the isolation dielectric 9, the AlGaN barrier layer 6 and the GaN channel layer 5, and the source metal 10 is located above the first p-type GaN 4.

[0044] A groove is arranged above the first p-type GaN 4, and the groove corresponds to the position of the groove of the GaN channel layer 5, so that the groove of the GaN channel layer 5 is embedded in the groove, and the inclination angle of the groove of the GaN channel layer 5 is set in the range of 60° to 90°.

[0045] Among them, the thickness of the n-type SiC substrate 2 is 2μm, the thickness of the n-type GaN 3 is 10μm, the thickness of the first p-type GaN 4 is 500nm, the thickness of the GaN channel layer 5 is 100nm, the thickness of the AlGaN barrier layer 6 is 20nm, the thickness of the second p-type GaN 7 layer is 100nm, and the thickness of the gate metal 8 is 100nm.

[0046] The doping concentration of the n-type SiC substrate 2 is 6×10 18 cm -3 , forming an ohmic contact with the drain metal 1 and reducing the device on-resistance. The doping concentration of the n-type GaN 3 is 6×10 16 cm -3 , ensuring a compromise between device withstand voltage and device on-resistance. The doping concentration of the first p-type GaN 4 is 1×10 18 cm -3 , forming an ohmic contact with the source electrode while controlling the GaN channel layer 5 to control the device to be turned off when the device is not turned on. The doping concentration of the second p-type GaN 7 layer is 1×10 17 cm -3 , in order for the device gate to complete the normally-off and gate voltage control of the two-dimensional electron gas under voltage-free conditions.

[0047] Under the above parameters and doping conditions, a vertical structure is adopted, and the withstand voltage level is higher than that of traditional lateral GaN HEMT devices. The withstand voltage level of the device is ≥900V, and the on-resistance of the device is ≤5×10 -4 Ω·cm.

[0048] The GaN channel layer 5 is intrinsic GaN, and the ratio of Al to GaN in the AlGaN barrier layer 6 is in the range of 2:8 to 5:5, thereby ensuring the formation of a two-dimensional electron gas.

[0049] The source metal 10 is in direct ohmic contact with the first p-type GaN 4, and the first p-type GaN 4 and the n-type GaN 3 form a pn junction to conduct electricity and form a parasitic body diode, thereby improving the body diode freewheeling characteristics of the device when the device is not turned on in the power supply field.

[0050] The gate voltage of the device is relative to the source level. When a large positive voltage is applied to the drain of the device and zero voltage is applied to the gate of the device, the AlGaN barrier layer 6 and the GaN channel layer 5 do not form a two-dimensional electron gas and cannot continue to flow. When a +5V level is applied to the gate of the device, a two-dimensional electron gas is formed, and electrons flow from the source metals 10 on the left and right sides along the two-dimensional electron gas to the groove of the n-type GaN 3, and flow to the drain through the n-type GaN 3 and the n-type SiC substrate 2, and the device is turned on. When the device is not turned on, but current needs to be formed, the source metal 10 of the device flows downward along the first p-type GaN 4 to the n-type GaN 3 and the n-type SiC substrate 2 (parasitic body diode). Due to the large conduction voltage drop of the first p-type GaN 4, n-type GaN 3 and n-type SiC substrate 2, when the device is turned on, it does not go through this branch, but takes the two-dimensional electron gas channel.

[0051] When the device is turned on, the freewheeling channel is a two-dimensional electron gas channel formed along the interface between the AlGaN barrier layer 6 and the GaN channel layer 5 from the source metal 10, flowing toward the middle and bottom to the upper part of the n-type GaN 3, and then flowing toward the drain under the action of the source-drain voltage, forming a conductive channel composed of two-dimensional electron gas and electrons. The two-dimensional electron gas is a quasi-free electron with extremely low resistivity, so the total on-resistance of the device is low.

[0052] The conduction of the device is completed by the gate and the second p-type GaN 7 controlling the two-dimensional electron gas interface. The threshold voltage for the formation of the two-dimensional electron gas is low, and the device can be fully turned on at a relatively low voltage. In this context, the driving loss of the device is relatively low. At the same time, the device gate only needs to control the formation of the two-dimensional electron gas at the interface between the AlGaN barrier layer 6 and the GaN channel layer 5, and does not need to control the conduction characteristics of the n-type GaN 3 region. The gate charge of the device is consistent with that of the HEMT device, and the switching speed of the device can still be maintained.

[0053] In summary, due to the adoption of a vertical structure, high withstand voltage can be achieved, the on-off control of the device is controlled by whether the two-dimensional electron gas is formed or not, and it has the characteristics of low driving loss. The conductive channel of the device is jointly conducted by electrons and the two-dimensional electron gas, and the on-resistance of the device is low, and it has excellent electrical properties. Example

[0054] A method for preparing a vertical normally-off GaN composite JFET device is prepared based on the vertical normally-off GaN composite JFET device, comprising the following steps:

[0055] S1, such as Figure 2 As shown, a layer of n-type GaN 3 is epitaxially grown on an n-type SiC substrate 2 with a drain metal 1;

[0056] S2, such as Figure 3As shown, a layer of p-type GaN is deposited on the n-type GaN 3 to form a first p-type GaN 4;

[0057] S3, such as Figure 4 As shown, a barrier layer is deposited on the first p-type GaN 4, a through hole of the GaN channel layer 5 is etched, and a groove of the GaN channel layer 5 is etched, and the inclination of the groove is 60° to 90°;

[0058] S4, such as Figure 5 As shown, the barrier layer formed in step S3 is removed, a new barrier layer is deposited on the first p-type GaN 4, a through hole of the GaN channel layer 5 is etched, and the GaN channel layer 5 is deposited;

[0059] S5, such as Figure 6 As shown, the barrier layer formed in step S4 is removed, a new barrier layer is deposited on the GaN channel layer 5, a through hole of the AlGaN barrier layer 6 is etched, and the AlGaN barrier layer 6 is deposited;

[0060] S6, such as Figure 7 As shown, the barrier layer formed in step S5 is removed, a new barrier layer is deposited on the AlGaN barrier layer 6, a through hole of the second p-type GaN 7 is etched, and a layer of p-type GaN is deposited to form the second p-type GaN 7;

[0061] S7, such as Figure 8 As shown, the barrier layer formed in step S6 is removed, a new barrier layer is deposited on the second p-type GaN 7 layer, a through hole for the gate metal 8 is etched, and the gate metal 8 is deposited;

[0062] S8, such as Fig. 9 As shown, the barrier layer formed in step S7 is removed, a new barrier layer is deposited on the gate metal 8, a through hole of the isolation dielectric 9 is etched, and the isolation dielectric 9 is deposited;

[0063] S9, such as Fig.10 As shown, the barrier layer formed in step S8 is removed, a new barrier layer is deposited on the gate metal 8, a through hole for the source metal 10 is etched, and the source metal 10 is deposited.

[0064] The beneficial effects of the present invention are:

[0065] The vertical normally-off GaN composite JFET device and its preparation method achieve high withstand voltage characteristics by adopting a vertical structure, which exceeds the traditional lateral GaN HEMT device. When the device is normally turned on, the two-dimensional electron gas at the interface of AlGaN and GaN and the common conduction of electrons in n-type GaN ensure low on-resistance and excellent current follow-on capability. In addition, the on-off control of the device depends on the formation of the two-dimensional electron gas. The generation of the two-dimensional electron gas is controlled by the gate voltage to achieve low driving loss and fast switching speed, which not only improves the efficiency of power supply applications, but also has excellent electrical properties and is suitable for use in high-performance electronic devices.

[0066] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0067] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A vertical normally-off GaN composite JFET device, characterized in that: The device comprises a drain metal, wherein the drain metal is located at the bottom of the device, an n-type SiC substrate is disposed above the drain metal, an n-type GaN is disposed above the n-type SiC substrate, and a first p-type GaN is disposed above the n-type GaN; A GaN channel layer is disposed above the first p-type GaN, a groove is disposed at the bottom of the GaN channel layer, an AlGaN barrier layer is disposed above the GaN channel layer, a second p-type GaN is disposed above the AlGaN barrier layer, and a gate metal is disposed above the second p-type GaN; Isolation dielectrics are disposed on both sides of the gate metal and the second p-type GaN, and the isolation dielectrics are located above the AlGaN barrier layer; source metals are disposed on both sides of the isolation dielectric, the AlGaN barrier layer, and the GaN channel layer, and the source metals are located above the first p-type GaN; The GaN channel layer is intrinsic GaN, and the ratio of Al to GaN in the AlGaN barrier layer is in the range of 2:8 to 5:5; A two-dimensional electron gas is formed at the interface between the AlGaN barrier layer and the GaN channel layer.

2. A vertical normally-off GaN composite JFET device according to claim 1, characterized in that: A groove is arranged above the first p-type GaN, the groove corresponds to the position of the groove of the GaN channel layer, so that the groove of the GaN channel layer is embedded in the groove, and the inclination angle of the groove of the GaN channel layer is set in the range of 60° to 90°.

3. A vertical normally-off GaN composite JFET device according to claim 1, characterized in that: The thickness of the n-type SiC substrate is 2 μm, the thickness of the n-type GaN is 10 μm, the thickness of the first p-type GaN is 500 nm, the thickness of the GaN channel layer is 100 nm, the thickness of the AlGaN barrier layer is 20 nm, the thickness of the second p-type GaN layer is 100 nm, and the thickness of the gate metal is 100 nm.

4. A vertical normally-off GaN composite JFET device according to claim 1, characterized in that: The doping concentration of the n-type SiC substrate is 6×10 18 cm -3 The doping concentration of n-type GaN is 6×10 16 cm -3 , the doping concentration of the first p-type GaN is 1×10 18 cm -3 , the doping concentration of the second p-type GaN layer is 1×10 17 cm -3 .

5. The vertical normally-off GaN composite JFET device according to claim 1, characterized in that: The withstand voltage rating of the device is ≥900V and the on-resistance of the device is ≤5×10 -4 Ω·cm.

6. The vertical normally-off GaN composite JFET device according to claim 1, characterized in that: The source metal is in direct ohmic contact with the first p-type GaN, and the first p-type GaN and the n-type GaN form a pn junction for conduction, thereby forming a parasitic body diode.

7. A method for preparing a vertical normally-off GaN composite JFET device, based on the vertical normally-off GaN composite JFET device according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1. epitaxially grow a layer of n-type GaN on an n-type SiC substrate with a drain metal; S2, depositing a layer of p-type GaN on the n-type GaN to form a first p-type GaN; S3, depositing a barrier layer on the first p-type GaN, etching a through hole of the GaN channel layer groove, and etching to form a groove of the GaN channel layer, wherein the inclination of the groove is 60° to 90°; S4, removing the barrier layer formed in step S3, depositing a new barrier layer on the first p-type GaN, etching a through hole for the GaN channel layer, and depositing a GaN channel layer; S5, removing the barrier layer formed in step S4, depositing a new barrier layer on the GaN channel layer, etching a through hole of the AlGaN barrier layer, and depositing an AlGaN barrier layer; S6, removing the barrier layer formed in step S5, depositing a new barrier layer on the AlGaN barrier layer, etching a through hole of a second p-type GaN, and depositing a layer of p-type GaN to form a second p-type GaN; S7, removing the barrier layer formed in step S6, depositing a new barrier layer on the second p-type GaN layer, etching a through hole for the gate metal, and depositing the gate metal; S8, removing the barrier layer formed in step S7, depositing a new barrier layer on the gate metal, etching a through hole for the isolation medium, and depositing an isolation medium; S9, remove the barrier layer formed in step S8, deposit a new barrier layer on the gate metal, etch a through hole for the source metal, and deposit the source metal.

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