A method and device for adjusting arbitrary phase sequence of three-phase input

Abstract

The present invention belongs to the technical field of power grids, and discloses a method and device for adjusting arbitrary phase sequence of three-phase input, wherein the voltage sampling values ​​of wire one, wire two and wire three are transmitted to input port one, input port two and input port three respectively, and the voltage values ​​of input port one, input port two and input port three are analyzed and processed, and the positive and negative values ​​of voltage V2 of input port two and voltage V3 of input port three are judged when voltage V1 of input port one changes from negative phase to positive phase. If V2 is a negative value and V3 is a positive value, the input phase sequence is recorded as positive sequence; if V2 is a positive value and V3 is a negative value, the input phase sequence is recorded as reverse sequence; and the input and output sequence of wire signals is adjusted according to the phase sequence result. The beneficial effects of the present invention: the phase sequence of the input three-phase line can be judged by sampling and analyzing the voltage of the input three-phase line, and the effect of matching the input phase sequence with the output phase sequence control can be achieved by adjusting the order of input and output.

Description

Technical Field

[0001] The present invention relates to the technical field of power grids, and in particular to a method and device for adjusting an arbitrary phase sequence of a three-phase input. Background Art

[0002] In the control of three-phase power grid related fields, it is necessary to know the voltage, phase, frequency and other information of the power grid in real time. This information can be obtained by phase-locking the power grid voltage. In order to ensure that the phase lock can be performed correctly, it is necessary to first ensure that the phase sequence of the three-phase power connected is accurate. If there is a disorder, it will lead to loss of control. The conventional way is to use special instruments to detect the power grid, but this method increases the cost of use, and the operation is complicated and prone to errors. In response to the above problems, the phase sequence detection methods can usually be divided into two types: software detection and hardware detection. Hardware detection requires increased costs and product size. With the improvement of DSP performance, the advantages of software detection are becoming more and more obvious.

[0003] Therefore, it is necessary to provide a method for adjusting the arbitrary phase sequence of three-phase input, determine the phase sequence by sampling the input voltage through software, adjust the signal phase sequence and send it to the phase-locked processor, and flexibly adjust the order of the output end after phase-locked processing and loop operation to achieve the purpose of matching the input phase sequence with the output phase sequence control. Summary of the invention

[0004] The invention discloses a three-phase input arbitrary phase sequence adjustment method and device, which relate to the control of a three-phase phase-locked processor, and can effectively solve the technical problems involved in the background technology.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] A three-phase input arbitrary phase sequence adjustment method comprises the following steps:

[0007] S1, arbitrarily sort the three-phase lines and define them as wire 1, wire 2 and wire 3 respectively, and transmit the voltage sampling values ​​of wire 1, wire 2 and wire 3 to input port 1, input port 2 and input port 3 respectively;

[0008] S2, analyzing and processing the voltage values ​​of input port 1, input port 2 and input port 3, and determining the positive and negative values ​​of the voltage V2 of input port 2 and the voltage V3 of input port 3 when the voltage V1 of input port 1 changes from negative phase to positive phase;

[0009] If V2 is negative and V3 is positive, the recorded input phase sequence is positive;

[0010] If V2 is positive and V3 is negative, the recorded input phase sequence is reversed;

[0011] S3, the phase-locked processing and loop operation unit is provided with input terminals U0, U1 and U2, and correspondingly with output terminals PWM0, PWM1 and PWM2;

[0012] If the input phase sequence is positive, the information of wire one is transmitted to U0, the information of wire two is transmitted to U1, the information of wire three is transmitted to U2, the information of PWM0 is output to output port one, the information of PWM1 is output to output port two, and the information of PWM2 is output to output port three;

[0013] If the input phase sequence is reverse, the information of wire one is transmitted to U0, the information of wire two is transmitted to U2, the information of wire three is transmitted to U1, the information of PWM0 is output to output port one, the information of PWM1 is output to output port three, and the information of PWM2 is output to output port two.

[0014] Specifically, the input voltage phase sequence of input port 1, input port 2, and input port 3 is not fixed. There are 6 line sequences: ABC / BCA / CAB / ACB / CBA / BAC. According to the characteristics of the three-phase line, it can be known that the relative relationship of ABC / BCA / CAB is the same, and phase A leads phase B by 120°, and phase B leads phase C by 120°, so they are the same line sequence. Similarly, the relative relationship of ACB / CBA / BAC is the same, and phase A leads phase C by 120°, and phase C leads phase B by 120°, so they are the same phase sequence, so there are only two phase sequences for the actual three-phase input. By processing and analyzing the input voltage value, the input phase sequence of the wire can be determined, and after adjusting it, the input phase sequence can be matched with the output phase sequence.

[0015] As a preferred improvement of the present invention: in the phase-locked processing and loop operation unit, the phase sequence relationship of the input terminals U0, U1 and U2 is that U0 leads U1, and U1 leads U2.

[0016] A three-phase input arbitrary phase sequence adjustment device, comprising a voltage sampling unit, an input phase sequence adjustment unit, a phase-locked processing and loop operation unit, an output phase sequence adjustment unit, an input port 1, an input port 2, an input port 3, an output port 1, an output port 2 and an output port 3;

[0017] The voltage sampling unit is used to sample the voltage values ​​of wire 1, wire 2 and wire 3, and transmit the results to input port 1, input port 2 and input port 3;

[0018] The input phase sequence adjustment unit is connected to input port 1, input port 2 and input port 3, and is used to judge the input phase sequence, and transmit the information of wire 1, wire 2 and wire 3 to the phase-locked processing and loop operation unit according to the input phase sequence;

[0019] The phase-locked processing and loop operation unit processes and operates the information of the wire one, the wire two and the wire three, and transmits the result to the output phase sequence adjustment unit;

[0020] The output phase sequence adjustment unit transmits the calculation results of the phase-locked processing and loop calculation unit to output port one, output port two and output port three according to the input phase sequence.

[0021] The beneficial effects of the present invention are as follows:

[0022] The method is simple and stable in operation. It only needs to sample and analyze the voltage of the input three-phase line to determine the phase sequence of the input three-phase line. By adjusting the order of input and output, the input phase sequence and output phase sequence control can be matched. It has the advantages of high efficiency and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0024] Figure 1 It is a schematic diagram of the phase sequence of the three-phase input voltage;

[0025] Figure 2 It is a schematic diagram of relative voltage relationship when the voltage phase sequence is ABC;

[0026] Figure 3 It is a schematic diagram of relative voltage relationship when the voltage phase sequence is ACB;

[0027] Figure 4 This is a schematic diagram of input-output relationship when the voltage phase sequence is ABC;

[0028] Figure 5 Schematic diagram of input and output relationship when the voltage phase sequence is ACB. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0031] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0032] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0034] At present, the signals at the input and output ends of the traditional three-phase phase-locked processor are fixed, which requires a fixed phase sequence at the input end. Therefore, the present invention samples the input voltage through software to determine the phase sequence, adjusts the signal phase sequence and sends it to the phase-locked processor, and flexibly adjusts the order of the output end after phase-locked processing and loop operation to achieve the purpose of matching the input phase sequence with the output phase sequence control.

[0035] See also Figure 1-Figure 5As shown, the three-phase line connects input port 1 (ADC1), input port 2 (ADC2) and input port 3 (ADC3). The input voltage phase sequence is not fixed. There are 6 line sequences: ABC / BCA / CAB / ACB / CBA / BAC. However, in fact, the relative relationship of ABC / BCA / CAB is the same, that is, phase A leads phase B by 120°, and phase B leads phase C by 120°. Therefore, they are the same line sequence. The relative relationship of ACB / CBA / BAC is the same, that is, phase A leads phase C by 120°, and phase C leads phase B by 120°. Therefore, they are the same phase sequence. Therefore, the input phase sequence can be divided into ABC and ACB. The input voltage entering the DSP sampling channels ADC1, ADC2, and ADC3 is sampled through Figure 2 and Figure 3 The relative relationship of the voltage under the two phase sequence conditions shown in the figure is used to confirm which phase sequence it is, and the corresponding signal is sent to the input after the input phase sequence is adjusted. Figure 4 or Figure 5 In U0, U1 and U2 shown in the figure, after phase-locked processing and loop operation, the output phase sequence is adjusted to match the phase sequence of PWM0, PWM1, PWM2 with PWMA (output port one), PWMB (output port two), and PWMC (output port three) to achieve the purpose of matching the input phase sequence with the output phase sequence, as shown respectively. Figure 4 and Figure 5 shown.

[0036] The present invention provides a three-phase input arbitrary phase sequence adjustment method, comprising the following steps:

[0037] S1. Arbitrarily sort the three-phase lines and define them as wire one, wire two and wire three respectively, and transmit the voltage sampling values ​​of wire one, wire two and wire three to input port one, input port two and input port three respectively.

[0038] S2. Analyze and process the voltage values ​​of input port 1, input port 2 and input port 3 to determine the positive and negative values ​​of the voltage V2 of input port 2 and the voltage V3 of input port 3 when the voltage V1 of input port 1 changes from negative phase to positive phase; if V2 is a negative value and V3 is a positive value, then record the input phase sequence as positive sequence; if V2 is a positive value and V3 is a negative value, then record the input phase sequence as reverse sequence.

[0039] S3. The phase-locked processing and loop operation unit is provided with input terminals U0, U1 and U2, and correspondingly provided with output terminals PWM0, PWM1 and PWM2. In the phase-locked processing and loop operation unit, the phase sequence relationship of the input terminals U0, U1 and U2 is that U0 leads U1, and U1 leads U2; if the input phase sequence is a positive sequence, the information of the wire one is transmitted to U0, the information of the wire two is transmitted to U1, the information of the wire three is transmitted to U2, the information of PWM0 is output to the output port one, the information of PWM1 is output to the output port two, and the information of PWM2 is output to the output port three; if the input phase sequence is a reverse sequence, the information of the wire one is transmitted to U0, the information of the wire two is transmitted to U2, the information of the wire three is transmitted to U1, the information of PWM0 is output to the output port one, the information of PWM1 is output to the output port three, and the information of PWM2 is output to the output port two.

[0040] A three-phase input arbitrary phase sequence adjustment device comprises a voltage sampling unit, an input phase sequence adjustment unit, a phase-locked processing and loop operation unit, an output phase sequence adjustment unit, an input port one, an input port two, an input port three, an output port one, an output port two and an output port three; the voltage sampling unit is used to sample the voltage values ​​of the first wire, the second wire and the third wire, and transmit the results to the first input port, the second input port and the third input port; the input phase sequence adjustment unit is connected with the first input port, the second input port and the third input port, and is used to judge the input phase sequence, and transmit the information of the first wire, the second wire and the third wire to the phase-locked processing and loop operation unit according to the input phase sequence; the phase-locked processing and loop operation unit processes and operates the information of the first wire, the second wire and the third wire, and transmits the results to the output phase sequence adjustment unit; the output phase sequence adjustment unit transmits the operation results of the phase-locked processing and loop operation unit to the output port one, the output port two and the output port three according to the input phase sequence. Example

[0041] Three-phase alternating current is an electric power system consisting of three alternating current circuits with the same frequency, equal potential amplitude and 120° phase difference. Here they are defined as phases A, B and C. Therefore, there are six phase sequences of the three phases, but in fact there are only two phase sequences. Figure 1 As shown in the figure, the relative relationship of ABC / BCA / CAB is the same, that is, phase A leads phase B by 120°, and phase B leads phase C by 120°, so they are the same line sequence. The relative relationship of ACB / CBA / BAC is the same, that is, phase A leads phase C by 120°, and phase C leads phase B by 120°, so they are the same phase sequence.

[0042] When the three-phase voltage is connected to U0, U1, and U2 corresponding to the three-phase phase-locked processor, the working state of the three-phase phase-locked processor is as follows: Figure 4As shown, the phase sequence at this time must be guaranteed to be U0 ahead of U1, and U1 ahead of U2. When the phase sequence of the three-phase voltage entering the three-phase phase-locked processor is random, if it is still in accordance with Figure 4 If the control is performed in the order shown, there may be confusion and loss of control. Therefore, it is necessary to judge the input voltage signal sent to the phase-locked processor, and then adjust the corresponding voltage signal and send it to U0, U1, and U2 of the phase-locked processor. It has been concluded that the phase sequence of the three phases is phase sequence ABC and phase sequence ACB. By judging the relationship between the relative voltages, it is possible to distinguish which phase sequence it is. Figure 2 The relative voltage relationship when the phase sequence is ABC is shown. When the A phase voltage VA changes from negative to positive, the B phase voltage VB is negative and the C phase voltage VC is positive. At this time, VA can be sent to U0, VB to U1, and VC to U2. The output result PWM0 is updated to PWMA, PWM1 is updated to PWMB, and PWM2 is updated to PWMC, as shown in Figure 4 As shown. Figure 3 The relative voltage relationship when the phase sequence is ACB, when the A phase voltage VA changes from negative phase to positive phase, the B phase voltage VB is positive, and the C phase voltage VC is negative. At this time, VA can be sent to U0, VC to U1, and VB to U2. The output result PWM0 is updated to PWMA, PWM1 is updated to PWMC, and PWM2 is updated to PWMB, as shown in Figure 5 shown.

[0043] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the embodiments. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A three-phase input arbitrary phase sequence adjustment method, characterized in that: The following steps are involved: S1, arbitrarily sort the three-phase lines and define them as wire 1, wire 2 and wire 3 respectively, and transmit the voltage sampling values ​​of wire 1, wire 2 and wire 3 to input port 1, input port 2 and input port 3 respectively; S2, analyzing and processing the voltage values ​​of input port 1, input port 2 and input port 3, and determining the positive and negative values ​​of the voltage V2 of input port 2 and the voltage V3 of input port 3 when the voltage V1 of input port 1 changes from negative phase to positive phase; If V2 is negative and V3 is positive, the recorded input phase sequence is positive; If V2 is positive and V3 is negative, the recorded input phase sequence is reversed; S3, the phase-locked processing and loop operation unit is provided with input terminals U0, U1 and U2, and correspondingly with output terminals PWM0, PWM1 and PWM2; If the input phase sequence is positive, the information of wire one is transmitted to U0, the information of wire two is transmitted to U1, the information of wire three is transmitted to U2, the information of PWM0 is output to output port one, the information of PWM1 is output to output port two, and the information of PWM2 is output to output port three; If the input phase sequence is reverse, the information of wire one is transmitted to U0, the information of wire two is transmitted to U2, the information of wire three is transmitted to U1, the information of PWM0 is output to output port one, the information of PWM1 is output to output port three, and the information of PWM2 is output to output port two.

2. A three-phase input arbitrary phase sequence adjustment method according to claim 1, characterized in that: In the phase-locked processing and loop operation unit, the phase sequence relationship of the input terminals U0, U1 and U2 is that U0 leads U1, and U1 leads U2.

3. A three-phase input arbitrary phase sequence adjustment device, used to implement a three-phase input arbitrary phase sequence adjustment method according to claim 1, characterized in that: It includes a voltage sampling unit, an input phase sequence adjustment unit, a phase-locked processing and loop operation unit, an output phase sequence adjustment unit, an input port 1, an input port 2, an input port 3, an output port 1, an output port 2 and an output port 3; The voltage sampling unit is used to sample the voltage values ​​of wire 1, wire 2 and wire 3, and transmit the results to input port 1, input port 2 and input port 3; The input phase sequence adjustment unit is connected to input port 1, input port 2 and input port 3, and is used to judge the input phase sequence, and transmit the information of wire 1, wire 2 and wire 3 to the phase-locked processing and loop operation unit according to the input phase sequence; The phase-locked processing and loop operation unit processes and operates the information of the wire one, the wire two and the wire three, and transmits the result to the output phase sequence adjustment unit; The output phase sequence adjustment unit transmits the calculation results of the phase-locked processing and loop calculation unit to output port one, output port two and output port three according to the input phase sequence.

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