Control system, control method, medium and terminal based on programmable logic array

Abstract

The present application provides a control system, control method, medium and terminal based on a programmable logic array, wherein the control system is connected to a device to be controlled, including a programmable operation logic unit, a programmable combination logic unit and an event signal interconnection control unit; according to the acquired target control requirements, the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection control unit are configured respectively; the event signal interconnection control unit is made to output an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combination logic unit to control the device to be controlled. The present application can flexibly configure the control system according to the control requirements, thereby improving the universality of integrated circuit control.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a control system, a control method, a medium and a terminal based on a programmable logic array. Background Art

[0002] With the advancement of technology and the improvement of integrated circuit design capabilities, the use of application-specific integrated circuits (ASICs) to control motors or power supplies is becoming more and more common. ASICs are custom designed for specific applications and can provide higher performance, lower power consumption, and smaller size than general-purpose processors or microcontrollers. However, ASIC designs are highly specialized, have poor universality, and are difficult to flexibly adjust after design and production. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a control system, control method, medium and terminal based on a programmable logic array, which are used to solve the problems in the above prior art that the integrated circuit design is highly specialized, has poor universality, and is difficult to flexibly adjust functions after design and production.

[0004] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a control system based on a programmable logic array, which is connected to a device to be controlled, including: a programmable operation logic unit, a programmable combination logic unit and an event signal interconnection and intercommunication control unit; wherein the m-bit output of the programmable operation logic unit and the n-bit output of the programmable combination logic unit are respectively connected to the event signal interconnection and intercommunication control unit; the event signal interconnection and intercommunication control unit has a q-bit output, wherein the m-bit output is connected to the programmable operation logic unit, the n-bit output is connected to the programmable combination logic unit, and the c-bit output is used to connect to the device to be controlled; q, m, n, and c are all positive integers; according to the acquired target control requirements, the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection and intercommunication control unit are respectively configured; the event signal interconnection and intercommunication control unit is enabled to output an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combination logic unit, so as to control the device to be controlled.

[0005] In some embodiments of the first aspect of the present application, the programmable operation logic unit includes: a data update subunit and m operation subunits; wherein the input of each operation subunit is the output of the data update subunit, and the output of each operation subunit is respectively connected to the event signal interconnection control unit.

[0006] In some embodiments of the first aspect of the present application, the programmable operation logic unit, the programmable combinational logic unit and the event signal interconnection and intercommunication control unit are configured respectively according to the acquired target control requirements, including: according to the acquired target control requirements, through the system buses of the programmable operation logic unit, the programmable combinational logic unit and the event signal interconnection and intercommunication control unit, the lookup table of the programmable combinational logic unit, the lookup and operation information of the programmable operation logic unit and the allocation relationship between the event signal and the port of the event signal interconnection and intercommunication control unit are configured respectively; wherein the lookup table of the programmable combinational logic unit includes: a first sub-lookup table corresponding to the n-bit outputs of the programmable combinational logic unit respectively; the lookup and operation information of the programmable operation logic unit includes: a second sub-lookup table corresponding to the data update subunit, a third sub-lookup table corresponding to each operation subunit and operation mode information.

[0007] In some embodiments of the first aspect of the present application, the event signal interconnection and intercommunication control unit is enabled to generate an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combinational logic unit to control the device to be controlled. The specific process includes: if the event signal of the current clock cycle input to the event signal interconnection and intercommunication control unit meets the target control requirements, the event signal of the current clock cycle is output through one of the c-bit outputs of the event signal interconnection and intercommunication control unit to control the device to be controlled; if the event signal of the current clock cycle input to the event signal interconnection and intercommunication control unit does not meet the target control requirements, the event signal of the current clock cycle is input into the programmable operation logic unit or the programmable combinational logic unit for processing.

[0008] In some embodiments of the first aspect of the present application, the processing method of the programmable combinatorial logic unit includes: calculating the first index value of the current clock cycle based on the n-bit output signal of the current clock cycle from the event signal interconnection and intercommunication control unit; matching in the first sub-lookup table of each bit output of the programmable combinatorial logic unit based on the calculated first index value of the current clock cycle, obtaining the output signal of the current clock cycle of each bit output of the programmable combinatorial logic unit and sending it to the event signal interconnection and intercommunication control unit.

[0009] In some embodiments of the first aspect of the present application, the processing method of the programmable arithmetic logic unit includes: inputting the m-bit output signal of the current clock cycle from the event signal interconnection control unit into the data update subunit for processing, and then processing it separately by each operation subunit; wherein the processing of the data update subunit specifically includes: calculating the second index value of the current clock cycle according to the m-bit output signal of the current clock cycle from the event signal interconnection control unit; matching in the second sub-lookup table of the data update subunit according to the calculated second index value of the current clock cycle, determining the mechanism value of the current clock cycle, and then determining the update mechanism of the current clock cycle; according to the determined update mechanism of the current clock cycle, determining the y-bit output signal output by the data update subunit to each operation subunit in the next clock cycle; the processing of each operation subunit specifically includes: based on the y-bit output signal of the current clock cycle from the data update subunit and the operand of the current clock cycle of each operation subunit, according to the configured operation mode information, calculating the operation result of the current clock cycle of each operation subunit and sending it to the event signal interconnection control unit.

[0010] In some embodiments of the first aspect of the present application, the operand of the current clock cycle of each operation subunit is obtained based on an operand update rule; wherein the operand update rule includes: if a y-bit injection value is written through the system bus of the programmable operation logic unit in the previous clock cycle, the y-bit injection value is used as the operand of the current clock cycle; if the y-bit injection value is not written through the system bus of the programmable operation logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation subunit according to the second index value of the previous clock cycle is a valid high level, the y-bit output signal of the previous clock cycle of the data update subunit is used as the operand of the current clock cycle; if the y-bit injection value is not written through the system bus of the programmable operation logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation subunit according to the second index value of the previous clock cycle is not a valid high level, the operand of the previous clock cycle of the data update subunit is used as the operand of the current clock cycle.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a control method based on a programmable logic array, which is applied to the control system based on the programmable logic array, and the method includes: configuring the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection control unit respectively according to the acquired target control requirements; and allowing the event signal interconnection control unit to generate an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combination logic unit, so as to control the device to be controlled.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the method when executed by a processor.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the method.

[0014] As described above, the control system, control method, medium and terminal based on programmable logic array of the present application have the following beneficial effects:

[0015] The present application can flexibly configure the control system according to control requirements, thereby improving the universality of integrated circuit control. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a schematic diagram of the structure of a control system based on a programmable logic array in one embodiment of the present application.

[0017] Figure 2 Shown is a schematic diagram of the structure of a programmable arithmetic logic unit in an embodiment of the present application.

[0018] Figure 3 Shown is a flow chart of a control method based on a programmable logic array in one embodiment of the present application.

[0019] Figure 4 Shown is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0021] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first sub-lookup table and the second sub-lookup table are only used to distinguish different sub-lookup tables, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0022] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0023] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0024] The present application provides a control system, control method, medium and terminal based on a programmable logic array, wherein the control system is connected to a device to be controlled, including a programmable operation logic unit, a programmable combination logic unit and an event signal interconnection control unit; according to the acquired target control requirements, the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection control unit are configured respectively; the event signal interconnection control unit is made to output an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combination logic unit to control the device to be controlled. The present application can flexibly configure the control system according to the control requirements, thereby improving the universality of integrated circuit control.

[0025] To facilitate understanding of the embodiments of the present application, first Figure 1 Detailed description. Figure 1 The schematic diagram of the structure of a control system based on a programmable logic array in an embodiment of the present invention is shown. The control system 1 based on a programmable logic array in this embodiment is connected to a device to be controlled 2, and the control system 1 mainly includes:

[0026] A programmable arithmetic logic unit 11, a programmable combinational logic unit 12 and an event signal interconnection control unit 13;

[0027] The m-bit output of the programmable arithmetic logic unit 11 and the n-bit output of the programmable combinational logic unit 12 are respectively connected to the event signal interconnection control unit;

[0028] The event signal interconnection control unit 13 has a q-bit output, wherein the m-bit output is connected to the programmable operation logic unit 11, the n-bit output is connected to the programmable combinational logic unit 12, and the c-bit output is connected to the device to be controlled 2; q, m, n, c are all positive integers, q = m + n + c.

[0029] It should be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0030] In one embodiment, the types of the device to be controlled 2 include but are not limited to motors, power supplies, etc.

[0031] In one embodiment, if Figure 2As shown, the input types of the event signal interconnection control unit 13 include: the m-bit output (alu_out[m-1:0]) of the programmable operation logic unit 11, the n-bit output (comb_out[n-1:0]) of the programmable combination logic unit 12, the k-bit independent event signal input (event_in[k-1:0]) and the system bus signal of the event signal interconnection control unit 13; the event signal interconnection control unit 13 has a q-bit event signal output (event_muxout[q-1:0]); wherein q>n+m; the m-bit output of the q-bit output serves as the input (alu_in[m-1:0]) of the programmable operation logic unit 11, the n-bit output of the q-bit output serves as the input (comb_in[n-1:0]) of the programmable combination logic unit 12, and the c-bit output of the q-bit output can be used to connect to the device 2 to be controlled so as to control the device 2 to be controlled.

[0032] In one embodiment, the event signal interconnection control unit 13 further includes (n+m+k) filter subunits, each filter subunit corresponds to each bit input of the event signal interconnection control unit 13, and the input types include: output from the programmable arithmetic logic unit 11, output from the programmable combinational logic unit 12, and k-bit independent event signals. For the x-th filter subunit, filter_in[x] represents the input of the filter subunit, filter_enable[x] represents the filter enable signal of the filter subunit, and filter_out[x] represents the output of the filter subunit. When filter_enable[x] is a valid signal, the filter subunit filters filter_in[x], filter_out[x] (N) = filter_in[x] (N-2); when filter_enable[x] is an invalid signal, the filter subunit does not filter filter_in[x], filter_out[x] = filter_in[x].

[0033] It should be understood that N represents the current clock cycle, and (N-2) represents the previous two clock cycles, that is, the previous clock cycle.

[0034] It should be noted that the effective signal can be defined as a high level or a low level. The present invention does not limit this. Figure 2As shown, the programmable operation logic unit 11 includes: a data update subunit 111 and m operation subunits 112; wherein, the input (alu_in[m-1:0]) of the data update subunit 111 includes: an m-bit output (alu_in[m-1:0]) from the event signal interconnection control unit 13 and a system bus signal of the programmable operation logic unit 11; the input of each operation subunit 112 includes: an output (data_target[y-1:0]) of the data update subunit 111 and a system bus signal of the programmable operation logic unit 11; the operation result output of each operation subunit 112 is connected to the event signal interconnection control unit 13, that is, the operation result output of the m operation subunits 112 constitutes the m-bit output of the programmable operation logic unit.

[0035] In one embodiment, each operation sub-unit 112 further outputs an operand, and the operands of the first seven operation sub-units 112 among the m operation sub-units 112 are input to the data updating sub-unit 111 .

[0036] It should be understood that Figure 2 FIG. 1 shows only the connection relationship between one operation subunit 112 and the data updating subunit 111 and the event signal interconnection control unit 13. The connection relationship between the remaining operation subunits 112 and Figure 2 Same as shown in .

[0037] In one embodiment, if Figure 2 As shown, part of the operands (alu_[x]_data[y-1:0]) of the m operation sub-units 112 are connected to the input of the data update sub-unit 111; specifically, the operands (alu_[6:0]_data[y-1:0]) of the first 7 groups of the m operation sub-units 112 are connected to the input of the data update sub-unit 111.

[0038] In one embodiment, if Figure 2 As shown, the input of the programmable combinatorial logic unit 12 includes: an n-bit output (comb_in[n-1:0]) from the event signal interconnection control unit and a system bus signal of the programmable combinatorial logic unit 12; the n-bit output (comb_out[n-1:0]) of the programmable combinatorial logic unit 12 is connected to the event signal interconnection control unit 13. In one embodiment, according to the acquired target control requirements, the programmable operation logic unit, the programmable combinatorial logic unit and the event signal interconnection control unit are configured respectively; the event signal interconnection control unit is made to output an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combinatorial logic unit, so as to control the device to be controlled.

[0039] For example, if the target control requirement is to make the device to be controlled realize the function of a counter, under this condition, the event signal that meets the target control requirement is a signal that can control the device to be controlled 2 to realize the function of a counter.

[0040] In one embodiment, according to the acquired target control requirements, the programmable arithmetic logic unit, the programmable combinational logic unit and the event signal interconnection control unit are configured respectively, including:

[0041] According to the acquired target control requirements, respectively configure the lookup table of the programmable combinational logic unit, the lookup and operation information of the programmable arithmetic logic unit, and the allocation relationship between the event signal and the port of the event signal interconnection and intercommunication control unit through the system bus of the programmable arithmetic logic unit, the programmable combinational logic unit, and the event signal interconnection and intercommunication control unit;

[0042] Among them, the lookup table of the programmable combinational logic unit includes: a first sub-lookup table corresponding to the n-bit outputs of the programmable combinational logic unit; the search and operation information of the programmable operation logic unit includes: a second sub-lookup table corresponding to the data update sub-unit, a third sub-lookup table corresponding to each operation sub-unit, and operation mode information.

[0043] Specifically, the bus signals of the system bus of the programmable combinational logic unit 12 include system clock, reset, read / write control, and read / write data signals. The registers inside the programmable combinational logic unit 12 are configured through the system bus of the programmable combinational logic unit 12 to complete the configuration of the first sub-lookup table corresponding to the n-bit outputs of the programmable combinational logic unit 12. The bus signals of the system bus of the programmable operation logic unit 11 include system clock, reset, read / write control, and read / write data signals. The registers inside the programmable operation logic unit 11 are configured through the system bus of the programmable operation logic unit 11 to complete the configuration of the second sub-lookup table corresponding to the data update sub-unit 111 in the programmable operation logic unit 11, the third sub-lookup table corresponding to each operation sub-unit 112, and the operation mode information of each operation sub-unit 112.

[0044] The allocation relationship between the event signal and the port of the event signal interconnection control unit is realized by configuring the output selection control signal group output_[q-1:0]_mux[j-1:0]. The output selection control signal group output_[q-1:0]_mux[j-1:0] consists of q j-bit control signals (output_[0]_mux[j-1:0], output_[1]_mux[j-1:0], output_[2]_mux[j-1:0]…output_[q-1]_mux[j-1:0]), that is, the output event_muxout[x] of each event signal interconnection control unit corresponds to an independent output_[x]_mux[j-1:0]. q is the valid number of output event_muxout, and j is calculated by the following formula 1:

[0045] j = celling(log2(n+m+k+2)); (Formula 1)

[0046] Among them, celling() is the upward rounding function.

[0047] In one embodiment, the input of event_muxout[x] is composed of filter_out[n+m+k-1:0], a constant high level clamp_high, and a constant low level clamp_low, that is, a total of n+m+k+2 inputs.

[0048] In one embodiment, the event signal interconnection control unit generates an event signal that meets the target control requirement with the assistance of the programmable operation logic unit and the programmable combinational logic unit to control the device to be controlled, and the specific process includes:

[0049] If the event signal of the current clock cycle input to the event signal interconnection control unit meets the target control requirement, the event signal of the current clock cycle is output through one of the c-bit outputs of the event signal interconnection control unit to control the device to be controlled;

[0050] If the event signal of the current clock cycle input to the event signal interconnection control unit does not meet the target control requirement, the event signal of the current clock cycle is input to the programmable arithmetic logic unit or the programmable combinational logic unit for processing.

[0051] Specifically, the signal source of the control system based on the programmable logic array can be an independent event signal, or it can be a signal that changes in a clock cycle within the entire control system based on the programmable logic array. It should be understood that the signal source is selected according to the target control requirements. The control system based on the programmable logic array has a clock cycle. When an event signal of the current clock cycle is input to the event signal interconnection control unit, if the event signal meets the target control requirements, the event signal is assigned to one of the c-bit outputs; if the event signal does not meet the target control requirements, the event signal is input to the programmable arithmetic logic unit through one of the m-bit outputs or input to the programmable combinational logic unit through one of the n-bit outputs, and the programmable arithmetic logic unit or the programmable combinational logic unit processes the event signal so that the event signal ultimately meets the target control requirements.

[0052] In one embodiment, if Figure 2 As shown, the programmable combinatorial logic unit performs processing in the following ways:

[0053] Calculate a first index value of the current clock cycle according to an n-bit output signal of the current clock cycle from the event signal interconnection and intercommunication control unit;

[0054] According to the calculated first index value of the current clock cycle, a match is performed in the first sub-lookup table of each bit output of the programmable combinatorial logic unit to obtain the output signal of the current clock cycle of each bit output of the programmable combinatorial logic unit and send it to the event signal interconnection control unit.

[0055] It should be understood that the programmable combinatorial logic unit provides an output of any combinatorial logic, that is, the combinatorial logic output between comb_in[n-1:0] signals of any requirement can be completed through the configurable register inside the programmable combinatorial logic unit.

[0056] The following is an explanation of the specific process of processing by the programmable combinational logic unit:

[0057] The programmable combinational logic unit has n-bit outputs, each of which corresponds to a first sub-lookup table, namely comb_[0]_lut[2 n -1:0], comb_[1]_lut[2 n -1:0], comb_[2]_lut[2 n -1:0]…comb_[n-1]_lut[2 n -1:0], a total of n 2 n bit lookup table.

[0058] For the z-th bit of the n-bit output, the corresponding first sub-lookup table is represented as comb_[z]_lut[2 n -1:0].

[0059] The specific process of processing by the programmable combinatorial logic unit includes: calculating the first index value of the current clock cycle according to the n-bit output signal comb_in[n-1:0] of the current clock cycle from the event signal interconnection control unit; matching in the first sub-lookup table corresponding to the z-th output according to the calculated first index value as the lookup table index to obtain the matching result corresponding to the z-th output; and using the matching result corresponding to the z-th output as the output of the current clock cycle of the z-th bit.

[0060] For example, for the z-th bit of the n-bit output, the value of the n-bit output signal comb_in[n-1:0] in the current clock cycle is 5, and the value of comb_[z]_lut[5] is used as the output of the z-th bit in the current clock cycle.

[0061] In one embodiment, the injection value comb_out_sw[n-1:0] corresponding to each bit output may be input into the programmable logic unit through the system bus of the programmable combinatorial logic unit. For the z-th bit output, its corresponding injection value is comb_out_sw[z]. If the injection value comb_out_sw[z] is input into the programmable logic unit through the system bus in the current clock cycle, the injection value comb_out_sw[z] is used as the output of the current clock cycle of the z-th bit; otherwise, the output of the current clock cycle of the z-th bit is determined according to the above index value.

[0062] In one embodiment, for a larger n, due to comb_[z]_lut[2 n -1:0] is 2 n bits, which will occupy a lot of hardware resources. n can be divided into multiple groups. For example, the 4-bit output signal comb_in can be grouped as one. The first group is comb_in[3:0] (that is, the 0th to 3rd bits of comb_in, a total of 4 input signals), and the corresponding first sub-lookup table is comb_[3:0]_lut[2 4 -1:0], the corresponding configurable injection value is comb_out_sw[3:0]; the second group is comb_in[7:4], and the corresponding first sub-lookup table is comb_[7:4]_lut[2 4-1:0], and so on. If the last group of comb_in is less than 4 bits, the missing part can be filled with a constant low level or a constant high level. The method of using the first sub-lookup table is consistent with the above method and will not be repeated here. Each independent first sub-lookup table is 16 bits, which effectively controls the overhead of the lookup table hardware resources.

[0063] In one embodiment, if Figure 2 As shown, the programmable arithmetic logic unit performs processing in the following manner:

[0064] The m-bit output signal of the current clock cycle from the event signal interconnection control unit is input into the data updating subunit for processing, and then processed by each operation subunit respectively;

[0065] The processing of the data updating subunit specifically includes:

[0066] Calculate a second index value of the current clock cycle according to the m-bit output signal of the current clock cycle from the event signal interconnection and intercommunication control unit;

[0067] According to the calculated second index value of the current clock cycle, matching is performed in the second sub-lookup table of the data update sub-unit to determine the mechanism value of the current clock cycle, and then determine the update mechanism of the current clock cycle;

[0068] According to the determined update mechanism of the current clock cycle, determine the y-bit output signal output by the data update subunit to each operation subunit in the next clock cycle;

[0069] The processing of each operator unit specifically includes:

[0070] Based on the y-bit output signal of the current clock cycle from the data update subunit and the operand of the current clock cycle of each operation subunit, the operation result of the current clock cycle of each operation subunit is calculated according to the configured operation mode information and sent to the event signal interconnection control unit.

[0071] The following is a detailed explanation of the specific process of the programmable arithmetic logic unit:

[0072] The m-bit output of the programmable arithmetic logic unit in the current clock cycle is composed of the outputs of the m arithmetic subunits in the current clock cycle. The output of each arithmetic subunit in the current clock cycle is obtained based on the y-bit output of the data update subunit in the current clock cycle and the operand of the current clock cycle. The y-bit output of the data update subunit in the current clock cycle is determined based on the m-bit output signal of the previous clock cycle from the event signal interconnection control unit and whether the injection value is written to the system bus.

[0073] The following describes the processing performed by the data update subunit and each operation subunit in the current clock cycle:

[0074] In the current clock cycle, the data update unit calculates the second index value of the current clock cycle according to the m-bit output signal alu_in[m-1:0] from the event signal interconnection control unit in the current clock cycle. Then, according to the calculated second index value of the current clock cycle, the second sub-lookup table data_[2 m -1:0]_lut[3:0] (indicates that there are 2 m The update mechanism of the current clock cycle is determined by matching the mechanism data of the current clock cycle in the configured update mechanism rules.

[0075] For example, for data_[2 m -1:0]_lut[3:0], when the value corresponding to alu_in[m-1:0] is 7, the output value is data_[7]_lut[3:0]. data_[7]_lut[3:0] corresponds to one of the update mechanisms in the update mechanism rule. After obtaining the mechanism corresponding to data_[7]_lut[3:0], the y-bit output data_target[y-1:0] of the data update unit of the next clock cycle is updated.

[0076] In one specific embodiment, the update mechanism rules data_lut_out[3:0] has 4 valid digits, 2 4 = 16 values. Each value corresponds to an update mechanism, as follows:

[0077] 1) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle remains consistent with the current clock cycle.

[0078] 2) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[0]_data[y-1:0] output by the 0th operator unit in the current clock cycle.

[0079] 3) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[1]_data[y-1:0] output by the first operator unit in the current clock cycle.

[0080] 4) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[2]_data[y-1:0] output by the second operator unit in the current clock cycle.

[0081] 5) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[3]_data[y-1:0] output by the third operator unit in the current clock cycle.

[0082] 6) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[4]_data[y-1:0] output by the 4th operator unit in the current clock cycle.

[0083] 7) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[5]_data[y-1:0] output by the 5th operator unit in the current clock cycle.

[0084] 8) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the operand alu_[6]_data[y-1:0] output by the 6th operator unit in the current clock cycle.

[0085] 9) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the value of the current clock cycle plus 1.

[0086] 10) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the value of the current clock cycle plus 2.

[0087] 11) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the value of the current clock cycle minus 1.

[0088] 12) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the value of the current clock cycle minus 2.

[0089] 13) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the y-bit value of the current clock cycle, shifted 1 bit to the left (towards the high bit), and the low bit is filled with 0.

[0090] 14) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the y-bit value of the current clock cycle, shifted 1 bit to the left (towards the high bit), and the low bit is filled with 1.

[0091] 15) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the y-bit value of the current clock cycle, shifted 1 bit to the right (towards the lower bit), and the high bit is filled with 0.

[0092] 16) The y-bit output data_target[y-1:0] of the data update unit in the next clock cycle is updated to the y-bit value of the current clock cycle, shifted 1 bit to the right (towards the lower bit), and the high bit is filled with 1.

[0093] It should be noted that when the injection value data_sw[y-1:0] is written to the data update unit through the system bus, the y-bit output data_target[y-1:0] of the data update unit in the next clock cycle will be updated to the written injection value data_sw[y-1:0]. If the injection value is not written to the data update unit, it is updated according to the update mechanism.

[0094] In the current clock cycle, for the u-th operator unit, its input types include: the output data_target[y-1:0] from the data update subunit in the current clock cycle, the injection value alu_[u]_data_sw[y-1:0] written through the system bus, and the operation mode information configured through the system bus. The u-th operator unit calculates the operation result alu_out[u] of the u-th operator unit based on the y-bit output signal data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle according to the configured operation mode information, and sends it to the event signal interconnection control unit.

[0095] In a specific embodiment, the operation mode information of alu_[u]_mode[3:0] includes 16 operation modes, which are as follows:

[0096] 1) The operation result of the current clock cycle, alu_out[u], is a constant low level.

[0097] 2) The calculation result of the current clock cycle, alu_out[u], is a constant high level.

[0098] 3) Determine whether the output data_target[y-1:0] of the current clock cycle of the data update subunit is greater than the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit; if so, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0099] 4) Determine whether the output data_target[y-1:0] of the current clock cycle of the data update subunit is less than the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If so, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0100] 5) Determine whether the output data_target[y-1:0] of the current clock cycle of the data update subunit is equal to the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If so, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0101] 6) Determine whether the output data_target[y-1:0] of the current clock cycle of the data update subunit is greater than or equal to the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If so, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0102] 7) Determine whether the output data_target[y-1:0] of the current clock cycle of the data update subunit is less than or equal to the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If so, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0103] 8) Determine whether the output data_target[y-1:0] of the current clock cycle of the data update subunit is not equal to the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If not, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0104] 9) The calculation result of the current clock cycle, alu_out[u], is a constant low level.

[0105] 10) The calculation result of the current clock cycle, alu_out[u], is a constant high level.

[0106] 11) Perform a bitwise OR operation on the output data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If the result of the bitwise OR operation is all high bits of the y bits, alu_out[u] of the current clock cycle is a high level; otherwise, it is a low level.

[0107] 12) Perform bitwise AND of the output data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If the result of the bitwise AND is all low for the y bits, alu_out[u] of the current clock cycle is a low level; otherwise, it is a high level.

[0108] 13) Perform bitwise AND of the output data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit, and perform bitwise XOR of the y-bit result after the bitwise AND. The result after the bitwise XOR is the value of alu_out[u] of the current clock cycle.

[0109] 14) Perform a bitwise OR operation on the output data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If the result of the bitwise OR operation is all high bits of the y bits, alu_out[u] of the current clock cycle is a low level; otherwise, it is a high level.

[0110] 15) Perform bitwise AND of the output data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. If the result of the bitwise AND is all low bits of the y bits, alu_out[u] of the current clock cycle is high; otherwise, it is low.

[0111] 16) Perform bitwise AND of the output data_target[y-1:0] of the current clock cycle of the data update subunit and the operand alu_[u]_data[y-1:0] of the current clock cycle of the u-th operation subunit. Perform bitwise XOR of the y-bit result after the bitwise AND. The result after the bitwise XOR is inverted to obtain the value of alu_out[u] of the current clock cycle, that is, when the XOR result is high, alu_out[u] is low, or when the result is low, alu_out[u] is high.

[0112] The operand of the current clock cycle of each operator unit is obtained based on the operand update rule; wherein, for the u-th operator unit, its operand update rule includes:

[0113] If the y-bit injection value alu_[u]_data_sw[y-1:0] is written through the system bus of the programmable arithmetic logic unit in the previous clock cycle, the y-bit injection value alu_[u]_data_sw[y-1:0] is used as the operand of the current clock cycle;

[0114] If the y-bit injection value alu_[u]_data_sw[y-1:0] is not written through the system bus of the programmable arithmetic logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation subunit according to the second index value of the previous clock cycle is a valid high level, the y-bit output signal of the previous clock cycle of the data update subunit is used as the operand of the current clock cycle;

[0115] If the y-bit injection value alu_[u]_data_sw[y-1:0] is not written through the system bus of the programmable arithmetic logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation sub-unit according to the second index value of the previous clock cycle is not a valid high level, the operand of the previous clock cycle of the data update sub-unit is used as the operand of the current clock cycle.

[0116] In one embodiment, when m in alu_in[m-1:0] is large, the second sub-lookup table of the data update sub-unit and the third sub-lookup table of each operation sub-unit are 2 m+2 bit and 2 m bits, which will occupy a lot of hardware resources. In order to solve the problem of occupying a lot of resources, m can be divided into multiple groups, for example, every 4 alu_in is a group. The first group of inputs is alu_in[3:0] (that is, the 0th to the 3rd bit of alu_in, a total of 4 bits). There is only one data update subunit, which will be expanded into multiple groups accordingly, each group has a data update subunit, and the second sub-lookup table of the data update subunit of the first group is data_[2 4-1:0]_lut[3:0], a total of 64 bits, and the second sub-lookup table of each group of data update subunits is independently configured. Each group of corresponding operation subunits also becomes 4, and the output operation result of each group of operation subunits is 4 bits, and the operands are also 4 groups. In the original scheme, the data update unit needs 7 groups of operands of operation modules as input. In the scheme of this embodiment, if the alu_in split into each group is less than 7, such as 4 per group in the current example, the insufficient operand part can adjust the corresponding update mechanism to repeat other existing mechanisms, such as data_[x]_target[y-1:0] to keep the current cycle value unchanged, or update it to a constant value and other options. When the last group of alu_in is less than 4 bits, the insufficient part can be filled with a constant low level or a constant high level. This scheme of this embodiment can effectively reduce the huge hardware resource overhead of the lookup table when m is large.

[0117] Figure 3 is a flow chart of a control method based on a programmable logic array provided in an embodiment of the present application. Figure 3 As shown, the control method based on the programmable logic array is applied to the control system based on the programmable logic array as described in the above embodiment, and the control method includes:

[0118] Step S31: configuring the programmable arithmetic logic unit, the programmable combinational logic unit and the event signal interconnection control unit respectively according to the acquired target control requirements;

[0119] Step S32: the event signal interconnection control unit is instructed to generate an event signal that meets the target control requirement with the assistance of the programmable operation logic unit and the programmable combinational logic unit, so as to control the device to be controlled.

[0120] It should be understood that the specific implementation process of the above method has been described in detail in the above system embodiment, and for the sake of brevity, it will not be repeated here.

[0121] In one embodiment, the programmable arithmetic logic unit includes: a data update subunit and m operation subunits; wherein the input of each operation subunit is the output of the data update subunit, and the output of each operation subunit is respectively connected to the event signal interconnection control unit.

[0122] In one embodiment, according to the acquired target control requirements, the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection control unit are configured respectively, including: according to the acquired target control requirements, through the system buses of the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection control unit, the lookup table of the programmable combination logic unit, the lookup and operation information of the programmable operation logic unit and the allocation relationship between the event signal and the port of the event signal interconnection control unit are configured respectively; wherein the lookup table of the programmable combination logic unit includes: a first sub-lookup table corresponding to the n-bit outputs of the programmable combination logic unit; the lookup and operation information of the programmable operation logic unit includes: a second sub-lookup table corresponding to the data update sub-unit, a third sub-lookup table corresponding to each operation sub-unit and operation mode information.

[0123] In one embodiment, the event signal interconnection and intercommunication control unit is assisted by the programmable operation logic unit and the programmable combination logic unit to generate an event signal that meets the target control requirements to control the device to be controlled. The specific process includes: if the event signal of the current clock cycle input to the event signal interconnection and intercommunication control unit meets the target control requirements, the event signal of the current clock cycle is output through one of the c-bit outputs of the event signal interconnection and intercommunication control unit to control the device to be controlled; if the event signal of the current clock cycle input to the event signal interconnection and intercommunication control unit does not meet the target control requirements, the event signal of the current clock cycle is input to the programmable operation logic unit or the programmable combination logic unit for processing.

[0124] In one embodiment, the processing method of the programmable combinatorial logic unit includes: calculating the first index value of the current clock cycle based on the n-bit output signal of the current clock cycle from the event signal interconnection and intercommunication control unit; matching in the first sub-lookup table of each bit output of the programmable combinatorial logic unit based on the calculated first index value of the current clock cycle, obtaining the output signal of the current clock cycle of each bit output of the programmable combinatorial logic unit and sending it to the event signal interconnection and intercommunication control unit.

[0125] In one embodiment, the processing method of the programmable arithmetic logic unit includes: inputting the m-bit output signal of the current clock cycle from the event signal interconnection control unit into the data update subunit for processing, and then processing it separately through each operation subunit; wherein the processing of the data update subunit specifically includes: calculating the second index value of the current clock cycle according to the m-bit output signal of the current clock cycle from the event signal interconnection control unit; matching in the second sub-lookup table of the data update subunit according to the calculated second index value of the current clock cycle, determining the mechanism value of the current clock cycle, and then determining the update mechanism of the current clock cycle; according to the determined update mechanism of the current clock cycle, determining the y-bit output signal output by the data update subunit to each operation subunit in the next clock cycle; the processing of each operation subunit specifically includes: based on the y-bit output signal of the current clock cycle from the data update subunit and the operand of the current clock cycle of each operation subunit, according to the configured operation mode information, calculating the operation result of the current clock cycle of each operation subunit and sending it to the event signal interconnection control unit.

[0126] In one embodiment, the operand of the current clock cycle of each operation subunit is obtained based on an operand update rule; wherein the operand update rule includes: the operand of the current clock cycle of each operation subunit is obtained based on the operand update rule; wherein the operand update rule includes: if a y-bit injection value is written through the system bus of the programmable operation logic unit in the previous clock cycle, the y-bit injection value is used as the operand of the current clock cycle; if the y-bit injection value is not written through the system bus of the programmable operation logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation subunit according to the second index value of the previous clock cycle is a valid high level, the y-bit output signal of the previous clock cycle of the data update subunit is used as the operand of the current clock cycle; if the y-bit injection value is not written through the system bus of the programmable operation logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation subunit according to the second index value of the previous clock cycle is not a valid high level, the operand of the previous clock cycle of the data update subunit is used as the operand of the current clock cycle.

[0127] Figure 4 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 4As shown, the electronic terminal includes: at least one processor 401, a memory 402, at least one network interface 403 and a user interface 405. The various components in the device are coupled together through a bus system 404. It can be understood that the bus system 404 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 404 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 4 In the specification, various buses are labeled as bus systems.

[0128] The user interface 405 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0129] It is understood that the memory 402 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0130] The memory 402 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 400. Examples of these data include: any executable program for operating on the electronic terminal 400, such as an operating system 4021 and an application 4022; the operating system 4021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 4022 may include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The control method based on a programmable logic array provided in the embodiment of the present invention may be included in the application 4022.

[0131] The method disclosed in the above embodiment of the present invention can be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 401 or the instruction in the form of software. The above processor 401 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 401 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 401 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0132] In an exemplary embodiment, the electronic terminal 400 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0133] According to the method provided in the embodiment of the present application, the present application also provides a computer program product, which includes: a computer program code, when the computer program code is run on a computer, the computer executes Figure 3 The control method based on programmable logic array in the illustrated embodiment.

[0134] According to the method provided in the embodiment of the present application, the present application also provides a computer-readable storage medium, which stores a program code, and when the program code is run on a computer, the computer executes Figure 3 The control method based on programmable logic array in the illustrated embodiment.

[0135] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and / or a computer running on a processor. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0136] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0137] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0138] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0139] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0140] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0141] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0142] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0143] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0144] In summary, the present application provides a control system, control method, medium and terminal based on a programmable logic array, wherein the control system is connected to a device to be controlled, including a programmable operation logic unit, a programmable combination logic unit and an event signal interconnection control unit; according to the acquired target control requirements, the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection control unit are configured respectively; the event signal interconnection control unit is assisted by the programmable operation logic unit and the programmable combination logic unit to output an event signal that meets the target control requirements to control the device to be controlled. The present application can flexibly configure the control system according to the control requirements, thereby improving the universality of integrated circuit control. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0145] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A control system based on a programmable logic array, characterized in that: Connect with the device to be controlled, including: Programmable arithmetic logic unit, programmable combinational logic unit and event signal interconnection control unit; The m-bit output of the programmable arithmetic logic unit and the n-bit output of the programmable combinational logic unit are respectively connected to the event signal interconnection control unit; The event signal interconnection control unit has q-bit outputs, wherein the m-bit output is connected to the programmable arithmetic logic unit, the n-bit output is connected to the programmable combinational logic unit, and the c-bit output is used to connect to the device to be controlled; q, m, n, and c are all positive integers; According to the acquired target control requirements, the programmable operation logic unit, the programmable combination logic unit and the event signal interconnection and intercommunication control unit are configured respectively; the event signal interconnection and intercommunication control unit is enabled to output an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combination logic unit, so as to control the device to be controlled.

2. The control system based on programmable logic array according to claim 1, characterized in that: The programmable arithmetic logic unit comprises: a data updating subunit and m operation subunits; wherein the input of each operation subunit is the output of the data updating subunit, and the output of each operation subunit is respectively connected to the event signal interconnection control unit.

3. The control system based on programmable logic array according to claim 2, characterized in that: According to the acquired target control requirements, the programmable arithmetic logic unit, the programmable combinational logic unit and the event signal interconnection control unit are configured respectively, including: According to the acquired target control requirements, respectively configure the lookup table of the programmable combinational logic unit, the lookup and operation information of the programmable arithmetic logic unit, and the allocation relationship between the event signal and the port of the event signal interconnection and intercommunication control unit through the system bus of the programmable arithmetic logic unit, the programmable combinational logic unit, and the event signal interconnection and intercommunication control unit; Among them, the lookup table of the programmable combinational logic unit includes: a first sub-lookup table corresponding to the n-bit outputs of the programmable combinational logic unit; the search and operation information of the programmable operation logic unit includes: a second sub-lookup table corresponding to the data update sub-unit, a third sub-lookup table corresponding to each operation sub-unit, and operation mode information.

4. The control system based on programmable logic array according to claim 3, characterized in that: The event signal interconnection control unit is made to output an event signal that meets the target control requirement with the assistance of the programmable operation logic unit and the programmable combinational logic unit to control the device to be controlled, and the specific process includes: If the event signal of the current clock cycle input to the event signal interconnection control unit meets the target control requirement, the event signal of the current clock cycle is output through one of the c-bit outputs of the event signal interconnection control unit to control the device to be controlled; If the event signal of the current clock cycle input to the event signal interconnection control unit does not meet the target control requirement, the event signal of the current clock cycle is input to the programmable arithmetic logic unit or the programmable combinational logic unit for processing.

5. The control system based on programmable logic array according to claim 4, characterized in that: The programmable combinatorial logic unit performs processing in the following manner: Calculate a first index value of the current clock cycle according to an n-bit output signal of the current clock cycle from the event signal interconnection and intercommunication control unit; According to the calculated first index value of the current clock cycle, a match is performed in the first sub-lookup table of each bit output of the programmable combinatorial logic unit to obtain the output signal of the current clock cycle of each bit output of the programmable combinatorial logic unit and send it to the event signal interconnection control unit.

6. The control system based on programmable logic array according to claim 4, characterized in that: The programmable arithmetic logic unit performs processing in the following manner: The m-bit output signal of the current clock cycle from the event signal interconnection control unit is input into the data updating subunit for processing, and then processed by each operation subunit respectively; The processing of the data updating subunit specifically includes: Calculate a second index value of the current clock cycle according to the m-bit output signal of the current clock cycle from the event signal interconnection and intercommunication control unit; According to the calculated second index value of the current clock cycle, matching is performed in the second sub-lookup table of the data update sub-unit to determine the mechanism value of the current clock cycle, and then determine the update mechanism of the current clock cycle; According to the determined update mechanism of the current clock cycle, determine the y-bit output signal output by the data update subunit to each operation subunit in the next clock cycle; The processing of each operator unit specifically includes: Based on the y-bit output signal of the current clock cycle from the data update subunit and the operand of the current clock cycle of each operation subunit, the operation result of the current clock cycle of each operation subunit is calculated according to the configured operation mode information and sent to the event signal interconnection control unit.

7. The control system based on programmable logic array according to claim 6, characterized in that: The operand of the current clock cycle of each operator unit is obtained based on the operand update rule; wherein the operand update rule includes: If a y-bit injection value is written through the system bus of the programmable arithmetic logic unit in the previous clock cycle, the y-bit injection value is used as the operand of the current clock cycle; If the y-bit injection value is not written through the system bus of the programmable arithmetic logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the arithmetic subunit according to the second index value of the previous clock cycle is a valid high level, the y-bit output signal of the previous clock cycle of the data update subunit is used as the operand of the current clock cycle; If the y-bit injection value is not written through the system bus of the programmable arithmetic logic unit in the previous clock cycle and the value obtained after matching in the third sub-lookup table of the operation sub-unit according to the second index value of the previous clock cycle is not a valid high level, the operand of the previous clock cycle of the data update sub-unit is used as the operand of the current clock cycle.

8. A control method based on a programmable logic array, characterized in that: Applied to the control system based on a programmable logic array as claimed in any one of claims 1 to 7, the method comprising: According to the acquired target control requirements, the programmable arithmetic logic unit, the programmable combinational logic unit and the event signal interconnection control unit are configured respectively; The event signal interconnection control unit is enabled to output an event signal that meets the target control requirements with the assistance of the programmable operation logic unit and the programmable combinational logic unit, so as to control the device to be controlled.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to claim 8 is implemented.

10. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method of claim 8.

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