Semiconductor structure, method for manufacturing semiconductor structure and NMOS transistor

Abstract

The embodiment of the present application provides a semiconductor structure, a method for manufacturing the semiconductor structure, and an NMOS transistor, wherein a source-drain doped region and a P-type doped well region are formed in the semiconductor structure; wherein a doped transition region is formed in the region adjacent to the source-drain doped region in the P-type doped well region; wherein the doping concentration of the doped transition region is less than the doping concentration of the source-drain doped region, and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source-drain doped region; the doped transition region is doped with a first ion and a second ion; the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doped ion forming the P-type doped well region; the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion. Through the embodiment of the present application, the junction leakage suppression effect and the threshold voltage adjustment effect on the CMOS device are improved, and the difficulty of improving the performance of the CMOS device is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a semiconductor structure, a method for manufacturing a semiconductor structure, and an NMOS transistor. Background Art

[0002] In the semiconductor manufacturing process, complementary metal oxide semiconductor (CMOS) technology is an important foundation for chip design and manufacturing. CMOS technology allows the simultaneous manufacture of N-type and P-type metal oxide semiconductor field effect transistors (MOSFET) on a single chip, and realizes low power consumption and high speed logic circuits through the complementarity of N-type MOSFET and P-type MOSFET.

[0003] CMOS devices include transistors, resistors, capacitors, diodes and other devices. Different types of ion implantation can be used to form CMOS devices of different types and electrical properties, which in turn form different gate circuits and gradually form a complete CMOS chip. A CMOS chip can contain millions to billions of CMOS devices. Among them, NMOS transistors are the core components of CMOS chips, and their performance directly affects the operating efficiency, reliability and service life of the entire chip.

[0004] Leakage and threshold voltage are two key performance indicators of CMOS devices. The leakage of CMOS devices will directly affect the overall energy consumption of the CMOS chip, while the threshold voltage will directly affect the overall performance of the circuit composed of CMOS devices. Specifically, among the various factors that affect the leakage of CMOS devices, junction leakage is greatly affected by the size of the device. As the size of the device decreases, the problem of high overall leakage of CMOS devices due to severe junction leakage becomes more and more prominent.

[0005] In the prior art, a pocket implant (PKT IMP) is mainly performed between the source-drain doping region and the doped well region of the transistor to suppress junction leakage and adjust the device threshold voltage. However, in practical applications, the above method has poor effects on suppressing junction leakage and adjusting threshold voltage. Summary of the invention

[0006] In view of this, multiple embodiments of the present application provide a semiconductor structure, a method for manufacturing a semiconductor structure, and an NMOS transistor to achieve improvements in the junction leakage suppression effect and the threshold voltage adjustment effect of CMOS devices.

[0007] In one aspect, an embodiment of the present application provides a semiconductor structure; a source-drain doping region and a P-type doped well region are formed in the semiconductor structure; wherein a doped transition region is formed in a region adjacent to the source-drain doping region in the P-type doped well region; wherein the doping concentration of the doped transition region is less than the doping concentration of the source-drain doping region and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source-drain doping region; the doped transition region is doped with a first ion and a second ion; the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doped ion forming the P-type doped well region; the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion.

[0008] Optionally, the first ions are indium ions.

[0009] Optionally, the second ion is a boron difluoride ion.

[0010] Optionally, the doped transition region includes a first ion doping region doped with a first ion; wherein the first ion doping region includes a first overlapping doping region and a first non-overlapping doping region; the doping concentration of the first overlapping doping region is greater than the doping concentration of the first non-overlapping doping region, and the first overlapping doping region and the first non-overlapping doping region are arranged in order of decreasing doping concentration along a direction away from the source and drain doping regions.

[0011] Optionally, the doped transition region includes a second overlapping doped region and a second non-overlapping doped region; wherein the second overlapping doped region is doped with the first ion and the second ion, and the second non-overlapping doped region is a region in the doped transition region other than the second overlapping doped region; the second overlapping doped region is a region with the highest doping concentration in the doped transition region, and the second overlapping doped region and the second non-overlapping doped region are arranged in order of decreasing doping concentration along the direction away from the source and drain doping regions.

[0012] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the manufacturing method comprising: providing a substrate; wherein a source-drain doping region and a P-type doped well region are formed in the substrate; performing a first ion implantation and a second ion implantation on the substrate to form a semiconductor structure; wherein the semiconductor structure has a doped transition region in a region adjacent to the source-drain doping region in the P-type doped well region; the doping concentration of the doped transition region is less than the doping concentration of the source-drain doping region, and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source-drain doping region; the doped transition region is doped with a first ion and a second ion; the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doped ion forming the P-type doped well region; the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion.

[0013] Optionally, the step of performing a first ion implantation and a second ion implantation on a substrate to form a semiconductor structure includes: performing a first ion implantation on the substrate to form an intermediate structure; wherein the first ions are indium ions; performing a second ion implantation on the intermediate structure to form a semiconductor structure; wherein the second ions are boron difluoride ions.

[0014] Optionally, the step of performing a first ion implantation on the substrate to form an intermediate structure includes: performing at least two first ion implantations on the substrate to form an intermediate structure; wherein the intermediate structure has a first ion doping region doped with first ions in an area adjacent to the source and drain doping region in the P-type doped well region; the implantation dose, implantation angle and implantation energy of different first ion implantations are at least partially different; the first ion doping region includes a first overlapping doping region and a first non-overlapping doping region; the doping concentration of the first overlapping doping region is greater than the doping concentration of the first non-overlapping doping region, and the first overlapping doping region and the first non-overlapping doping region are arranged in order of decreasing doping concentration along a direction away from the source and drain doping region.

[0015] Optionally, performing a second ion implantation on the intermediate structure to form a semiconductor structure comprises the following steps: performing a second ion implantation on the intermediate structure to form a semiconductor structure; wherein a second overlapping doping region and a second non-overlapping doping region are formed in a region of the semiconductor structure adjacent to the source and drain doping region in a P-type doped well region; the implantation dose, implantation angle and implantation energy of the second ion implantation are different from the implantation dose, implantation angle and implantation energy of at least two first ion implantations; the second overlapping doping region is doped with the first ions and the second ions, and the second non-overlapping doping region is a region in the doping transition region other than the second overlapping doping region; the second overlapping doping region is a region with the highest doping concentration in the doping transition region, and the second overlapping doping region is a region in the doping transition region with the smallest distance from the source and drain doping region.

[0016] In another aspect, an embodiment of the present application provides an NMOS transistor, wherein the NMOS transistor includes the semiconductor structure described in the above embodiment or a semiconductor structure manufactured by the method for manufacturing the semiconductor structure described in the above embodiment.

[0017] In multiple embodiments provided in the present application, a doped transition region is formed in a region adjacent to a source-drain doped region in a P-type doped well region in a semiconductor structure, wherein the doping concentration of the doped transition region is less than the doping concentration of the source-drain doped region and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source-drain doped region, and the doped transition region is doped with a first ion and a second ion, wherein the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doping ion forming the P-type doped well region, and the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion, The unexpected effects achieved include: by doping the first ion in the doping transition region, the doping concentration gradient on both sides of the PN junction at the junction of the source-drain doping region and the P-type doping well region is adjusted, so that the doping concentration change on both sides of the PN junction is converted from a steep change to a gradual change, reducing the junction leakage of the CMOS device; and by doping the second ion in the doping transition region, the threshold voltage of the CMOS device is adjusted, so that the effects of the two actions can be controlled by separately controlling the ion injection parameters of the two doping ions, thereby improving the suppression effect of the junction leakage of the CMOS device and the adjustment effect of the threshold voltage, and reducing the difficulty of improving the performance of the CMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 The semiconductor structure is formed after a PKT IMP is performed as provided in the related art.

[0020] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0021] Figure 3 A schematic structural diagram of a substrate provided for one embodiment of the present application.

[0022] Figure 4 A schematic flow chart of the steps of performing a first ion implantation and a second ion implantation on a substrate is provided for one embodiment of the present application.

[0023] Figure 5 A schematic diagram of an intermediate structure provided for one embodiment of the present application.

[0024] Figure 6 A schematic structural diagram of a semiconductor structure provided for one embodiment of the present application.

[0025] Figure 7 A schematic diagram comparing the junction leakage current of the semiconductor structure provided in the embodiment of the present application with the junction leakage current of the semiconductor structure provided in the related art.

[0026] Structure number description

[0027] 100, substrate; 110, source-drain doping region; 111, source doping region; 112, drain doping region; 120, P-type doped well region; 121, pocket-shaped doping region; 122, doping transition region; 1221, first ion doping region; 12211, first overlapping doping region; 12212, first non-overlapping doping region; 1222, second overlapping doping region; 1223, second non-overlapping doping region; 130, N-type doped well region; 140, lightly doped region; 150, isolation structure; 160, gate structure; 161, gate epitaxial layer; 200, intermediate structure; 300, semiconductor structure. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0029] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0030] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0031] Suppressing leakage and adjusting threshold voltage are the keys to improving the performance of CMOS devices and CMOS chips.

[0032] First, as device size shrinks, leakage has become a bottleneck restricting the performance improvement of CMOS chips. The leakage level of CMOS devices can be measured by leakage current. A large leakage current may cause a significant increase in the power consumption of CMOS chips, resulting in serious power consumption of electronic products based on CMOS chips and a significant reduction in battery life. In the case of excessive leakage current, it may also cause the temperature of CMOS devices to rise sharply, causing thermal damage and further leading to device failure and product failure. Therefore, reducing the leakage level of CMOS devices, that is, reducing the leakage current of CMOS devices, is the key to improving the performance and reliability of CMOS chips.

[0033] Secondly, the threshold voltage can control the on and off of CMOS devices in the circuit. In digital circuits formed by CMOS devices, the choice of threshold voltage will affect static power consumption and dynamic power consumption; in analog circuits formed by CMOS devices, the threshold voltage affects the working point of the device, which in turn affects the amplification ability of the device. The appropriate threshold voltage can make the device work in the saturation region or linear region, thereby providing good gain for the circuit. In addition, the threshold voltage also has a direct impact on the noise tolerance, anti-interference ability and reliability of the circuit formed by CMOS devices.

[0034] Taking NMOS transistor as an example, the leakage mechanism of CMOS devices is analyzed below.

[0035] NMOS transistor leakage can be divided into three types according to the leakage path: source-drain leakage, gate leakage, and junction leakage. Among them, junction leakage refers to the PN junction leakage formed at the junction of the transistor source-drain doping region (SD region) and the doped well region (Well region). Specifically, due to the opposite ion implantation types of the SD region and the Well region, a PN junction will be formed at the interface where the two are in contact, and there is a large difference between the doping concentration of the SD region and the doping concentration of the Well region, resulting in a steep doping concentration difference on both sides of the PN junction, which in turn causes junction leakage. When the value of the doping concentration difference on both sides of the PN junction is small, the mechanism of junction leakage is avalanche breakdown; when the value of the doping concentration difference on both sides of the PN junction is large, the mechanism of junction leakage is Zener breakdown.

[0036] Since the short channel effect and quantum tunneling effect are key factors affecting the size of the junction leakage current, and these two effects are greatly affected by the device size. As the size of NMOS transistor devices gradually decreases, the short channel effect and quantum tunneling effect become more and more significant, further causing source-drain punch-through and junction tunneling, resulting in an increase in junction leakage current, which in turn leads to a decrease in the leakage performance of NMOS transistors. Please refer to Figure 1. In the case of a small NMOS transistor device, in order to suppress junction leakage, reduce junction leakage current, and adjust the threshold voltage of the NMOS transistor, in the related art, a PKT IMP is performed in the Well region of the NMOS transistor adjacent to the SD region to form a pocket doping region 121, and the degree of source-drain punch-through and drain-induced barrier lowering (DIBL) is controlled by controlling the injection parameters of the PKT IMP to reduce the junction leakage current. The injection parameters of the PKT IMP can be: the injected ions are In ions, the injection energy range is 58keV~62keV, and the injection dose range is 1×10 14 ions / cm²~5×10 14 ions / cm². However, since the distribution range of the pocket doping region 121 in the Well region is small, it is not enough to affect the doping concentration gradient on both sides of the PN junction. The PN junction will still leak due to the steep doping concentration difference on both sides. In addition, since only one PKT IMP is performed, the adjustment of the injection parameters is limited. Therefore, there is still a large junction leakage current in the NMOS transistor after one PKT IMP, and the threshold voltage adjustment capability of the NMOS transistor is also weak.

[0037] Therefore, it is necessary to provide a semiconductor structure, wherein a doped transition region is formed in a region adjacent to a source-drain doped region in a P-type doped well region in the semiconductor structure, wherein the doping concentration of the doped transition region is less than the doping concentration of the source-drain doped region and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source-drain doped region, and the doped transition region is doped with a first ion and a second ion, wherein the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doped ion forming the P-type doped well region; and the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion, so that By doping the first ion in the doping transition region, the doping concentration gradient on both sides of the PN junction at the junction of the source-drain doping region and the P-type doping well region is adjusted, so that the doping concentration change on both sides of the PN junction is converted from a steep change to a gradual change, thereby reducing the junction leakage of the CMOS device. By doping the second ion in the doping transition region, the threshold voltage of the CMOS device is adjusted. By doping the two ions in the doping transition region, the two functions of suppressing the junction leakage and adjusting the threshold voltage are respectively achieved, so that the ion implantation parameters of the two doping ions can be controlled respectively, thereby improving the suppression effect of the junction leakage of the CMOS device and the adjustment effect of the threshold voltage, thereby reducing the difficulty of improving the performance of the CMOS device.

[0038] See also Figures 2 to 6An embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include the following steps.

[0039] S110: providing a substrate.

[0040] See also Figure 3 The base 100 can be obtained by processing a substrate. Specifically, the substrate can be made of semiconductor material, insulating material, conductive material or any combination thereof. For example, the substrate can be made of silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC) and other materials. The substrate can be a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer is used as the substrate.

[0041] In this embodiment, a P-type doped well region 120, an N-type doped well region 130 and an isolation structure 150 may be formed in the substrate. Specifically, the P-type doped well region 120 and the N-type doped well region 130 may be used to provide electrical isolation for NMOS transistors in CMOS transistors, and the isolation structure 150 may be used to perform lateral isolation between different devices. The N-type doped well region 130, i.e., a deep N-well (DNW), may be formed at the bottom of the substrate by first implanting high-dose, high-energy N-type doping ions into the substrate. Subsequently, the P-type doped well region 120 may be formed on the side of the N-type doped well region 130 close to the substrate surface by implanting P-type doping ions, such as boron (B) ions or boron difluoride (BF2) ions. Next, the isolation structure 150 may be formed by using shallow trench isolation (STI), field oxide isolation (FOX) or local oxidation of silicon (LOCOS) or other technologies. The P-type doped well region 120 , the N-type doped well region 130 and the isolation structure 150 may all be formed by conventional techniques, and the specific formation process will not be described in detail herein.

[0042] In this embodiment, after the P-type doped well region 120, the N-type doped well region 130 and the isolation structure 150 are formed, a gate structure 160 and a gate epitaxial layer 161 formed outside the gate structure 160 can be formed on the substrate surface. Specifically, a gate dielectric layer and a gate electrode layer can be sequentially formed on the substrate surface by photolithography and etching to form the gate structure 160. The gate epitaxial layer 161 can be used to isolate the gate from the source and the drain, and protect the gate structure 160 from being damaged in subsequent process steps. The gate epitaxial layer 161 can include a gate heavy oxide layer and an offset sidewall. The gate heavy oxide layer can be formed on both sides of the gate structure 160 by re-oxidation (Re-Oxidation) of the gate structure 160. The offset sidewall can be formed outside the gate heavy oxide layer by thin film deposition and etching. The offset sidewall can be a single-layer structure or a multi-layer composite structure. The gate structure 160 and the gate epitaxial layer 161 can be formed by conventional technology, and the specific formation process is not repeated here.

[0043] In this embodiment, after the gate structure 160 and the gate epitaxial layer 161 are formed, a lightly doped drain (LDD) region 140 and a source-drain doped region 110 may be formed in the substrate. Specifically, the source-drain doped region 110 may include a source doped region 111 and a drain doped region 112. The gate epitaxial layer 161 may be used as a mask to implant N-type doping ions, such as arsenic (As) ions or phosphorus (P) ions, into the substrate to form the LDD region 140 and the source-drain doped region 110 in the substrate. The implantation dose and implantation energy of the ion implantation used to form the LDD region 140 are different from those of the ion implantation used to form the source-drain doped region 110. Taking the implantation of As ions to form the source-drain doped region 110 as an example, the implantation energy may range from 15keV to 17keV, and the implantation dose may range from 2.5×10 15 ions / cm²~3.5×10 15 ions / cm². Optionally, the implantation energy can be 15keV, 15.5keV, 16keV, 16.5keV, 17keV, and the implantation dose can be 2.5×10 15 ions / cm²、2.7×10 15 ions / cm²、3×10 15 ions / cm²、3.2×10 15 ions / cm²、3.5×10 15 ions / cm². Taking the implantation of P ions to form the source and drain doping regions 110 as an example, the implantation energy range may be 19keV to 21keV, and the implantation dose range may be 4.5×10 13 ions / cm²~5.5×10 13ions / cm². Optionally, the implantation energy can be 19keV, 19.5keV, 20keV, 20.5keV, 21keV, and the implantation dose can be 4.5×10 13 ions / cm²、4.7×10 13 ions / cm²、5×10 13 ions / cm²、5.2×10 13 ions / cm²、5.5×10 13 ions / cm². The LDD region 140 and the source-drain doping region 110 can be formed by conventional techniques, and the specific formation process will not be described in detail here.

[0044] After the above processing, a base 100 can be formed based on the substrate. Specifically, the base 100 may include a substrate, a gate structure 160 and a gate epitaxial layer 161. A source-drain doped region 110, a P-type doped well region 120, an N-type doped well region 130, an LDD region 140 and an isolation structure 150 are formed in the substrate.

[0045] S120: performing a first ion implantation and a second ion implantation on the substrate to form a semiconductor structure.

[0046] In order to reduce the junction leakage current of the PN junction formed at the junction of the P-type doped well region 120 and the source-drain doped region 110, and to improve the ability to adjust the device threshold voltage, a doped transition region 122 doped with the first ion and the second ion can be formed in the adjacent region of the PN junction, so that the first ion doping can be used to adjust the doping concentration gradient on both sides of the PN junction to slow down the doping concentration change trend on both sides of the PN junction, and the second ion doping can be used to adjust the device threshold voltage. The two functions of reducing the junction leakage current and adjusting the threshold voltage are respectively achieved by doping two kinds of ions in the P-type doped well region, so that the effects of the above two functions can be controlled by controlling the injection parameters of the two ion injections respectively.

[0047] See also Figure 6In the present embodiment, the semiconductor structure 300 has a doped transition region 122 in the region where the P-type doped well region 120 is adjacent to the source-drain doped region 110. Specifically, the region where the P-type doped well region 120 is adjacent to the source-drain doped region 110 may be an edge region of the projection of the gate structure 160 in the P-type doped well region 120. The doping concentration of the doped transition region 122 may be less than the doping concentration of the source-drain doped region 110 and greater than the doping concentration of the P-type doped well region 120, and the doping concentration of the doped transition region 122 decreases in a direction away from the source-drain doped region 110. The doping type of the doped transition region 122 may be the same as the doping type of the P-type doped well region 120, that is, the doping type of the doped transition region 122 may be P-type. Since the doping concentration of the source-drain doping region 110 is usually greater than the doping concentration of the P-type doping well region 120, a doping transition region 122 is formed in the P-type doping well region 120, and the doping concentration is between the doping concentration of the P-type doping well region 120 and the doping concentration of the source-drain doping region 110, and the doping concentration decreases in the direction away from the source-drain doping region 110, so that the doping concentration in the P region of the PN junction changes gradually, the doping concentration of the region close to the N region is larger, and the doping concentration of the region away from the N region is smaller, so that the difference between the doping concentration of the P region and the doping concentration of the N region in the PN junction can be reduced, and the concentration change trend on both sides of the PN junction can be slowed down, thereby reducing the junction leakage current. In this embodiment, each ion implantation can use the same ion implantation process, for example, PKT IMP. The implantation parameters of different ion implantations are at least partially different. Specifically, the implantation parameters may include implanted ions, implantation angles, implantation doses, and implantation energy. Among them, the implantation angle may refer to the angle between the implantation direction of the implanted ion beam and the normal of the substrate of the substrate 100, and the implantation angle range may be 0° to 30°. The implantation dose may refer to the amount of ions contained in the implantation ion beam, and the implantation energy may refer to the energy of the implantation ion beam. Since the doped transition region 122 is formed by at least two ion implantations with at least partially different implantation parameters, compared with the pocket-shaped doped region 121 in the related art, the doped transition region 122 in this embodiment has a larger distribution range in the substrate 100, has a greater impact on the gradient of the doping concentration variation on both sides of the PN junction, and has a better effect on suppressing junction leakage.

[0048] See also Figures 4 to 6 Performing a first ion implantation and a second ion implantation on a substrate to form a semiconductor structure may include the following steps.

[0049] S121: performing a first ion implantation on the substrate to form an intermediate structure.

[0050] See also Figure 5To enhance the effect of suppressing junction leakage, first ions that are not easily diffused may be implanted into the substrate of the base 100 , thereby forming a relatively stable, non-migrating first ion doping region 1221 in the P-type doped well region 120 adjacent to the source-drain doping region 110 .

[0051] In this embodiment, the step of performing a first ion implantation on the substrate to form the intermediate structure may include: performing at least two first ion implantations on the substrate to form the intermediate structure.

[0052] In order to activate the doped ions and improve the performance and reliability of the devices manufactured based on the semiconductor structure, the semiconductor structure is usually annealed after the overall structure of the semiconductor structure is formed, and the annealing may affect the distribution of the doped ions in the semiconductor substrate 100, thereby destroying the gradual concentration gradient formed in the P region of the PN junction by at least two ion implantations, resulting in a decrease in the inhibition of junction leakage. In order to reduce the influence of the annealing treatment on the distribution of the first ion doped region 1221 in the substrate of the substrate 100, in this embodiment, the relative atomic mass of the first ion can be greater than the relative atomic mass or relative molecular mass of the doped ions forming the P-type doped well region 120. Specifically, since the diffusion ability of ions with a larger relative atomic mass is weaker, after the annealing treatment, the first ion doped region 1221 can still remain at the position formed by ion implantation. Since the element with a larger atomic number has a larger relative atomic mass, the first ion can be a group III element with a larger atomic number. In this embodiment, when the doped ions of the P-type doped well region 120 are B ions or BF2, the first ion can be an indium ion. In some embodiments, the first ions may also be gallium (Ga) ions.

[0053] In this embodiment, the first ion doping region 1221 may include a first overlapping doping region 12211 and a first non-overlapping doping region 12212. Specifically, each first ion implantation may form a first ion sub-doping region in the substrate of the substrate 100, the first overlapping doping region 12211 may refer to an overlapping region of a plurality of first ion sub-doping regions, and the first non-overlapping doping region 12212 may refer to a region doped with the first ions except the first overlapping doping region 12211. Since the doping concentration of the first overlapping doping region 12211 may be a superposition of the doping concentrations of a plurality of first ion sub-doping regions, the doping concentration of the first overlapping doping region 12211 may be greater than the doping concentration of the first non-overlapping doping region 12212. Furthermore, in order to slow down the doping concentration variation trend on both sides of the PN junction, in the P region of the PN junction, the doping concentration of the region closer to the N region in the PN junction can be higher. Therefore, relative to the first non-overlapping doping region 12212 with a smaller doping concentration, the first overlapping doping region 12211 with a larger doping concentration can be closer to the source-drain doping region 110. That is, the first overlapping doping region 12211 and the first non-overlapping doping region 12212 are arranged in the order of decreasing doping concentration in the direction away from the source-drain doping region 110.

[0054] In order to achieve a balance between the junction leakage suppression effect and the process cost, in this embodiment, the number of first ion implantations can be 2 to 5 times. Specifically, the number of first ion implantations can be 2, 3, 4, or 5 times. In order to expand the distribution range of the first ion doping region 1221 in the substrate of the base 100 and improve the junction leakage suppression effect, the implantation dose, implantation angle, and implantation energy of different first ion implantations can be different, and the implantation dose, implantation angle, and implantation energy of the first ion implantation that is performed earlier in the order can be larger. Taking the execution of three first ion implantations as an example, the implantation dose range of the first first ion implantation can be 3.2×10 13 ions / cm²~3.8×10 13 ions / cm², the implantation energy range can be 48keV~52keV, the implantation angle range can be 23°~27°; the implantation dose range of the second first ion implantation can be 3.2×10 13 ions / cm²~3.8×10 13 ions / cm², the implantation energy range can be 38keV~42keV, the implantation angle range can be 13°~17°; the implantation dose range of the third first ion implantation can be 2.8×10 13 ions / cm²~3.2×10 13 ions / cm², the implantation energy range may be 28keV to 32keV, and the implantation angle range may be 8° to 12°. Optionally, the implantation dose of the first ion implantation may be 3.2×1013 ions / cm²、3.4×10 13 ions / cm²、3.5×10 13 ions / cm²、3.6×10 13 ions / cm²、3.8×10 13 ions / cm², the implantation energy can be 48keV, 49keV, 50keV, 51keV, 52keV, and the implantation angle can be 23°, 24°, 25°, 26°, 27°; the implantation dose of the second first ion implantation can be 3.2×10 13 ions / cm²、3.4×10 13 ions / cm²、3.5×10 13 ions / cm²、3.6×10 13 ions / cm²、3.8×10 13 ions / cm², the implantation energy can be 38keV, 39keV, 40keV, 41keV, 42keV, and the implantation angle can be 13°, 14°, 15°, 16°, 17°; the implantation dose of the third first ion implantation can be 2.8×10 13 ions / cm²、2.9×10 13 ions / cm²、3.0×10 13 ions / cm²、3.1×10 13 ions / cm²、3.2×10 13 ions / cm², the implantation energy can be 28keV, 29keV, 30keV, 31keV, 32keV, and the implantation angle can be 8°, 9°, 10°, 11°, 12°.

[0055] After at least two first ion implantations, an intermediate structure 200 may be formed based on the substrate 100 .

[0056] S122: performing a second ion implantation on the intermediate structure to form a semiconductor structure.

[0057] In the related art, since the doping ions of the pocket doping region 121 are In ions with weak migration ability, the pocket doping region 121 has weak ability to adjust the threshold voltage. In order to improve the ability to adjust the threshold voltage of the device, after the first ion implantation is completed and the first ion doping region 1221 is formed in the intermediate structure 200, the second ions with strong migration ability can be implanted into the intermediate structure 200.

[0058] In order to utilize the influence of annealing on the distribution of the region doped with the second ion in the substrate within the intermediate structure 200, and thereby utilize the second ion's strong migration ability to enhance the ability to adjust the device threshold voltage, in this embodiment, the second ion is different from the first ion, and the relative molecular mass of the second ion may be less than the relative atomic mass of the first ion. Specifically, on the one hand, after annealing, the distribution of the region doped with the ion with strong migration ability in the substrate may change, so that the change can be controlled by controlling the injection parameters of the ion injection to achieve the adjustment of the device threshold voltage; on the other hand, if the migration ability of the doped ion is too strong, the change may be difficult to control by controlling the injection parameters. Therefore, in order to achieve a balance between the migration ability of the doped ion and the controllability of the distribution change of the doped region after annealing, in this embodiment, when the first ion is an In ion, the second ion may be a BF2 ion.

[0059] See also Figure 6 In the present embodiment, in the semiconductor structure 300, the doping transition region 122 may include a second overlapping doping region 1222 and a second non-overlapping doping region 1223. Specifically, the second overlapping doping region 1222 may be a region doped with the first ion and the second ion, and the second non-overlapping doping region 1223 may be a region of the doping transition region 122 other than the second overlapping doping region 1222. Since the second overlapping doping region 1222 is doped with two ions, and the second non-overlapping doping region 1223 is only doped with the first ion, the second overlapping doping region 1222 is the region with the highest doping concentration in the doping transition region 122. In order to slow down the doping concentration change trend on both sides of the PN junction, in the P region of the PN junction, the doping concentration of the area closer to the N region in the PN junction can be higher. Therefore, relative to the second non-overlapping doping region 1223 with a smaller doping concentration, the second overlapping doping region 1222 with a larger doping concentration can be closer to the source and drain doping region 110, that is, the second overlapping doping region 1222 and the second non-overlapping doping region 1223 are arranged in the order of decreasing doping concentration along the direction away from the source and drain doping region 110.

[0060] In order to achieve a balance between the threshold voltage adjustment effect and the process cost, in this embodiment, only one second ion implantation may be performed. Specifically, the implantation dose, implantation angle, and implantation energy of the second ion implantation may be different from the implantation dose, implantation angle, and implantation energy of at least two first ion implantations. Since the relative molecular mass of the second ion is less than the relative atomic mass of the first ion, and in order to fully utilize the migration ability of the second ion, the implantation dose, implantation angle, and implantation energy of the second ion implantation may be smaller. For example, the implantation dose range of the second ion implantation may be 1×10 13 ions / cm²~5×10 13ions / cm², the implantation energy range may be 2.5keV to 3.5keV, and the implantation angle range may be 8° to 12°. Optionally, the implantation dose of the second ion implantation may be 1×10 13 ions / cm²、2×10 13 ions / cm²、3×10 13 ions / cm²、4×10 13 ions / cm²、5×10 13 ions / cm², the implantation energy can be 2.5keV, 2.7keV, 3keV, 3.3keV, 3.5keV, and the implantation angle can be 8°, 9°, 10°, 11°, 12°.

[0061] The researchers have experimentally measured that the threshold voltage of the semiconductor structure manufactured by the above manufacturing method can be adjusted in the range of 0.1V to 0.6V. Optionally, the threshold voltage can be 0.1V, 0.3V, 0.5V, or 0.6V.

[0062] An embodiment of the present application provides a semiconductor structure 300, in which a source-drain doped region 110 and a P-type doped well region 120 are formed; wherein a doped transition region 122 is formed in the P-type doped well region 120 in an area adjacent to the source-drain doped region 110; wherein the doping concentration of the doped transition region 122 is less than the doping concentration of the source-drain doped region 110 and greater than the doping concentration of the P-type doped well region 120, and the doping concentration of the doped transition region 122 decreases in a direction away from the source-drain doped region 110.

[0063] See also Figure 7 . The researchers and developers have experimentally measured that the junction leakage current of the semiconductor structure with a pocket-shaped doped region provided by the related art is 350pA / um, while the junction leakage current of the semiconductor structure with a doped transition region with a gradually changing concentration provided by the embodiment of the present application is 20pA / um. By comparing the two, it can be seen that compared with the semiconductor structure provided by the related art, the junction leakage current of the semiconductor structure provided by the embodiment of the present application is reduced by 94.29%, that is, the manufacturing method of the semiconductor structure provided by the embodiment of the present application can significantly reduce the junction leakage current.

[0064] In an embodiment of the present application, a doping transition region with a gradually changing concentration is formed in a region adjacent to a source-drain doping region in a P-type doping well region of a semiconductor structure, wherein the doping concentration of the doping transition region is less than the doping concentration of the source-drain doping region and greater than the doping concentration of the P-type doping well region, and the doping concentration of the doping transition region decreases in a direction away from the source-drain doping region, and the doping transition region is doped with a first ion and a second ion, wherein the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doping ion forming the P-type doping well region, and the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion, and the unexpected effects achieved include: utilizing the first ion to be doped in the doping transition region The invention realizes adjusting the doping concentration variation gradient on both sides of the PN junction at the junction of the source-drain doping region and the P-type doped well region, so that the doping concentration variation on both sides of the PN junction is converted from abrupt change to gradual change, thereby reducing the junction leakage of the NMOS transistor device and the CMOS device manufactured based on the NMOS transistor, and adjusting the threshold voltage of the CMOS device by doping the second ion in the doping transition region, and realizing the two functions of suppressing the junction leakage and adjusting the threshold voltage by doping the two ions in the doping transition region, so that the ion implantation parameters of the two doping ions can be controlled respectively to control the effects of the two functions, thereby improving the inhibition effect of the junction leakage of the CMOS device and the adjustment effect of the threshold voltage, and reducing the difficulty of improving the performance of the CMOS device.

[0065] An embodiment of the present application provides an NMOS transistor, which may include the semiconductor structure described in the above embodiment, or may include a semiconductor structure manufactured by the method for manufacturing the semiconductor structure described in the above embodiment.

[0066] Regarding the technical effects of the NMOS transistor described in the above embodiment, reference can be made to other embodiments of the present application for comparative explanation and no further details will be given here.

[0067] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0068] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0069] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0070] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0071] In several embodiments provided in this application, it should be understood that the disclosed semiconductor structure or NMOS transistor can be implemented in other ways. For example, the embodiments of the semiconductor structure or NMOS transistor described above are merely illustrative.

[0072] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: A source-drain doped region and a P-type doped well region are formed in the semiconductor structure; wherein, a doped transition region is formed in the region adjacent to the source / drain doped region in the P-type doped well region; wherein the doping concentration of the doped transition region is less than the doping concentration of the source / drain doped region and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source / drain doped region; the doped transition region is doped with a first ion and a second ion; the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doped ion forming the P-type doped well region; the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion; the doped transition region includes a first ion doped region doped with the first ion; wherein the first ion doped region includes a first overlapping doped region and a first non-overlapping doped region; the doping concentration of the first overlapping doped region is greater than the doping concentration of the first non-overlapping doped region, and the first overlapping doped region and the first non-overlapping doped region are arranged in the order of decreasing doping concentration in a direction away from the source / drain doped region.

2. The semiconductor structure according to claim 1, characterized in that: The first ions are indium ions.

3. The semiconductor structure according to claim 1, characterized in that: The second ion is a boron difluoride ion.

4. The semiconductor structure according to claim 1, characterized in that The doped transition region includes a second overlapping doped region and a second non-overlapping doped region; wherein the second overlapping doped region is doped with a first ion and a second ion, and the second non-overlapping doped region is a region of the doped transition region other than the second overlapping doped region; the second overlapping doped region is a region with the highest doping concentration in the doped transition region, and the second overlapping doped region and the second non-overlapping doped region are arranged in the order of decreasing doping concentration along the direction away from the source and drain doping region.

5. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing a substrate; wherein a source-drain doped region and a P-type doped well region are formed in the substrate; Performing at least two first ion implantations on the substrate to form an intermediate structure; wherein the intermediate structure has a first ion doping region doped with first ions in a region adjacent to the source-drain doping region in the P-type doped well region; the implantation dose, implantation angle, and implantation energy of different first ion implantations are at least partially different; the first ion doping region includes a first overlapping doping region and a first non-overlapping doping region; the doping concentration of the first overlapping doping region is greater than the doping concentration of the first non-overlapping doping region, and the first overlapping doping region and the first non-overlapping doping region are arranged in the order of decreasing doping concentration along a direction away from the source-drain doping region; A second ion implantation is performed on the intermediate structure to form the semiconductor structure; wherein the semiconductor structure has a doped transition region in the P-type doped well region and in an area adjacent to the source-drain doped region; the doping concentration of the doped transition region is less than the doping concentration of the source-drain doped region and greater than the doping concentration of the P-type doped well region, and the doping concentration of the doped transition region decreases in a direction away from the source-drain doped region; the doped transition region is doped with a first ion and a second ion; the relative atomic mass of the first ion is greater than the relative atomic mass or relative molecular mass of the doped ion forming the P-type doped well region; the second ion is different from the first ion, and the relative molecular mass of the second ion is less than the relative atomic mass of the first ion.

6. The method according to claim 5, characterized in that The first ions are indium ions; the second ions are boron difluoride ions.

7. The method according to claim 5, characterized in that The step of performing a second ion implantation on the intermediate structure to form the semiconductor structure comprises: A second ion implantation is performed on the intermediate structure to form the semiconductor structure; wherein the semiconductor structure has a second overlapping doping region and a second non-overlapping doping region in the P-type doped well region adjacent to the source-drain doping region; the implantation dose, implantation angle and implantation energy of the second ion implantation are different from the implantation dose, implantation angle and implantation energy of at least 2 times of the first ion implantation; the second overlapping doping region is doped with the first ion and the second ion, and the second non-overlapping doping region is the region of the doping transition region other than the second overlapping doping region; the second overlapping doping region is the region with the highest doping concentration in the doping transition region, and the second overlapping doping region is the region with the smallest distance from the source-drain doping region in the doping transition region.

8. An NMOS transistor, characterized in that: The NMOS transistor comprises the semiconductor structure according to any one of claims 1 to 4 or a semiconductor structure manufactured by the method for manufacturing the semiconductor structure according to any one of claims 5 to 7.

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