Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for preparing the semiconductor device, the semiconductor device comprises a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bit line connection line and a second bit line connection line, the first semiconductor structure comprises a sensing amplifier circuit, the second semiconductor structure is connected to the first semiconductor structure by bonding and comprises a first storage unit, the third semiconductor structure is connected to the second semiconductor structure by bonding and comprises a second storage unit, the first bit line connection line is associated with the first storage unit, the second bit line connection line is associated with the second storage unit, the first bit line connection line and the second bit line connection line are comparatively coupled to each other by the sensing amplifier circuit, and the length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns. The coupling capacitance of adjacent bit lines can be reduced, the anti-crosstalk capability can be improved, and the difference in signal transmission time delay can be reduced, thereby improving the stability and reliability of the device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Recently, with the multifunctionalization of information and communication devices, high-density, high-capacity and high-integration memory devices have been needed or desired. Therefore, it is proposed to use vertical channel transistors to increase the density of memory devices and vertically stack multi-layer memory devices to increase the capacity and integration of memory devices.

[0003] However, the vertically stacked memory device architecture may require a complex and crowded wiring design to connect the memory cells to the logic control circuit, such as the sense amplifier circuit. Two bit lines coupled to each other in the same sense amplifier circuit may cause different delays in signal transmission time due to the difference in length. Especially in high-speed circuits, even a slight difference may cause data reading errors, affecting the stability and reliability of the circuit. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor device and a method for preparing a semiconductor device, which have the advantages of high density, high capacity and high integration, small length difference between two bit lines coupled in the same sensing amplifier circuit compared to each other, and strong anti-interference ability.

[0005] In a first aspect, the present application provides a semiconductor device according to some embodiments, characterized in that it includes:

[0006] a first semiconductor structure comprising a sense amplifier circuit;

[0007] a second semiconductor structure, the second semiconductor structure being connected to the first semiconductor structure by bonding, the second semiconductor structure comprising a first memory cell;

[0008] a third semiconductor structure, the third semiconductor structure being connected to the second semiconductor structure by bonding, the third semiconductor structure comprising a second memory cell;

[0009] a first bit line connection line, the first bit line connection line being associated with the first memory cell;

[0010] a second bitline connection line, the second bitline connection line being associated with the second memory cell;

[0011] The first bit line connection line and the second bit line connection line are comparatively coupled to each other through the sense amplifier circuit;

[0012] A length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 micrometers.

[0013] In some embodiments, the first memory unit includes a first memory array and a second memory array, and the first memory array and the second memory array are in the same horizontal plane;

[0014] The second memory unit includes a third memory array and a fourth memory array, and the third memory array and the fourth memory array are on the same horizontal plane;

[0015] The third storage array is close to the first storage array, and the fourth storage array is close to the second storage array.

[0016] In some embodiments, the first bit line connection line is associated with the first memory array;

[0017] The second bit line connection line is associated with the third memory array.

[0018] In some embodiments, the first bit line connection line is associated with the first memory array;

[0019] The second bit line connection line is associated with the fourth memory array.

[0020] In some embodiments, the first memory cell includes a first bit line, a first transistor, and a first capacitor, wherein the first capacitor, the first transistor, and the first bit line are stacked in a direction perpendicular to the second semiconductor structure;

[0021] The second memory cell comprises a second bit line, a second transistor and a second capacitor, wherein the second bit line, the second transistor and the second capacitor are stacked in a direction perpendicular to the third semiconductor structure;

[0022] The first bit line connection line is connected to the first bit line;

[0023] The second bit line connection line is connected to the second bit line.

[0024] In some embodiments, the second semiconductor structure includes a side close to the first semiconductor structure and a side close to the third semiconductor structure;

[0025] The third semiconductor structure comprises a side close to the second semiconductor structure and a side far away from the second semiconductor structure;

[0026] The first bit line is located on a side of the second semiconductor structure close to the third semiconductor structure;

[0027] The second bit line is located on a side of the third semiconductor structure close to the second semiconductor structure.

[0028] In some embodiments, the first semiconductor structure further includes a first interconnect structure, the first interconnect structure is located on a side of the first semiconductor structure close to the second semiconductor structure, the first interconnect structure is connected to a sense amplifier circuit, and is bonded to the second semiconductor structure;

[0029] The second semiconductor structure further includes a second interconnect structure, which is located on a side of the second semiconductor structure close to the first semiconductor structure, and the second interconnect structure is bonded to the first semiconductor structure;

[0030] The second semiconductor structure further includes a third interconnect structure, the third interconnect structure including a first through-connector, a first bit line connector and a first contact, the first through-connector is connected to the second interconnect structure, the first bit line connector is respectively connected to the first bit line and the first through-connector, the first contact is located on a side of the second semiconductor structure close to the third semiconductor structure, connected to the first through-connector, and bonded to the third semiconductor structure;

[0031] The third semiconductor structure also includes a fourth interconnect structure, which includes a second through-connector, a second bit line connector and a second contact. The second contact is located on a side of the third semiconductor structure close to the second semiconductor structure and is bonded to the first contact. The second bit line connector is respectively connected to the second bit line and the second contact, and the second through-connector is connected to the second contact.

[0032] In some embodiments, the positions where the plurality of first bit line connectors are connected to the plurality of first bit lines are staggered;

[0033] Positions where the plurality of second bit line connectors are connected to the plurality of second bit lines are staggered and distributed.

[0034] In some embodiments, the effective length of the first bit line connection is equal to the effective length of the second bit line connection coupled to the same sense amplifier circuit.

[0035] In some embodiments, the third semiconductor structure further includes a lead-out structure, which is located on a side of the third semiconductor structure away from the second semiconductor structure and is connected to the second through-connector.

[0036] In a second aspect, the present application also provides a method for preparing a semiconductor device according to some embodiments, comprising:

[0037] providing a first semiconductor structure in which a sense amplifier circuit is formed;

[0038] providing a second semiconductor structure, forming a first memory cell in the second semiconductor structure;

[0039] providing a third semiconductor structure in which a second memory cell is formed;

[0040] forming a third semiconductor structure on the second semiconductor structure by bonding;

[0041] forming a second semiconductor structure on the first semiconductor structure by bonding;

[0042] forming a first bit line connection line, the first bit line connection line being associated with the first memory cell;

[0043] forming a second bit line connection line, the second bit line connection line being associated with the second memory cell;

[0044] The first bit line connection line and the second bit line connection line are comparatively coupled to each other through the sense amplifier circuit;

[0045] A length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 micrometers.

[0046] In some embodiments, providing a first semiconductor structure includes:

[0047] providing a first substrate, forming the sense amplifier circuit and the first interconnect structure on the first substrate;

[0048] Forming a first memory cell in the second semiconductor structure includes:

[0049] Providing a second substrate, forming a first bit line, a first transistor and a first capacitor on the second substrate, wherein the first bit line, the first transistor and the first capacitor are stacked in a vertical direction;

[0050] Forming a second memory cell in the third semiconductor structure includes:

[0051] A third substrate is provided, on which a second bit line, a second transistor, and a second capacitor are formed, wherein the second bit line, the second transistor, and the second capacitor are stacked in a vertical direction.

[0052] In some embodiments, forming a third semiconductor structure on the second semiconductor structure by bonding includes:

[0053] forming a first carrier and a second carrier on the second semiconductor structure and the third semiconductor structure respectively;

[0054] flipping the second semiconductor structure and the third semiconductor structure, and removing the second substrate and the third substrate;

[0055] forming a first bit line connection and a first contact in the second semiconductor structure;

[0056] forming a second bit line connection and a second contact in the third semiconductor structure;

[0057] The second semiconductor structure is turned over to bond the second semiconductor structure to the third semiconductor structure.

[0058] In some embodiments, forming a second semiconductor structure on the first semiconductor structure by bonding includes:

[0059] removing the first carrier and forming a first through-connector and a second interconnect structure in the second semiconductor;

[0060] The second semiconductor structure is turned over to bond the second semiconductor to the first semiconductor structure.

[0061] In some embodiments, after the second semiconductor and the first semiconductor structure are bonded, the method further comprises:

[0062] The third carrier is removed, and a second through-connector and a lead-out structure are formed in the third semiconductor structure.

[0063] The semiconductor structure and the preparation method thereof provided in the present application have at least the following beneficial effects:

[0064] The present application provides a semiconductor device and a method for preparing the semiconductor device. In the semiconductor device, the vertical stacking of the first semiconductor structure, the second semiconductor structure and the third semiconductor structure can improve the storage density and integration of the semiconductor device. Two bit lines coupled to the same sensing amplifier circuit are respectively associated with the second memory unit and the third memory unit, which can reduce the coupling capacitance of adjacent bit lines and improve the anti-crosstalk capability. At the same time, the length difference of the connecting wires of the two bit lines is less than or equal to 2 microns, which can effectively prevent different delays in signal transmission time and improve the stability and reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0066] Figure 1A schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0067] Figure 2 A schematic diagram of a cross-sectional view of another semiconductor device provided in an embodiment of the present application;

[0068] Figure 3 for Figure 1 A schematic diagram of a partially enlarged cross-sectional view of a semiconductor structure described in;

[0069] Figure 4 for Figure 1 A simplified schematic perspective view of a portion of a semiconductor structure as described in;

[0070] Figure 5A , 5B , 5C, 6A, 6B, 7A, 7B, 8 and 9 are a method of forming a Figure 3 Manufacturing process of semiconductor structures in

[0071] Description of reference numerals:

[0072] 101: first substrate; 102, 102A, 120B: sense amplifier circuit; 103, 103A, 103B: first interconnection structure; 1: first semiconductor structure; 201: second substrate; 2021: first bit line; 2022: first transistor; 2023: first capacitor; 203: first carrier; 2041: first bit line connection; 2042: first contact; 2043: first through connection; 2044: second interconnection structure; 2: second semiconductor structure; 202A: first memory array; 202B: second memory array; 204A, 204B: first bit line connection line; 301: third substrate; 3021: second bit line; 3022: second transistor; 3023: second capacitor; 303: second carrier; 3041: second bit line connection member; 3042: second contact member; 3043: second through connection member; 305: lead-out structure; 3: third semiconductor structure; 302A: third memory array; 302B: fourth memory array; 304A, 304B: second bit line connection lines. DETAILED DESCRIPTION

[0073] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first doping region may be referred to as a second doping region, and similarly, a second doping region may be referred to as a first doping region; the first doping region and the second doping region are different doping regions.

[0076] Spatial relational terms such as "on..." may be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "on..." will be oriented to be "below" other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0077] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present invention.

[0079] Figure 1 A schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present application. In some embodiments, the semiconductor device includes a first semiconductor structure 1, a second semiconductor structure 2, a third semiconductor structure 3, first bit line connection lines 204A, 204B and second bit line connection lines 304A, 304B, wherein the first semiconductor structure 1 includes sense amplifier circuits 102A, 102B, the second semiconductor structure 2 is connected to the first semiconductor structure 1 by bonding, and includes first storage units 202A, 202B, and the third semiconductor structure 3 is connected to the second semiconductor structure 2 by bonding, and includes a second storage unit 302 A, 302B, the first bit line connection lines 204A, 204B are associated with the first memory cells 202A, 202B, the second bit line connection lines 304A, 304B are associated with the second memory cells 302A, 302B, the first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B are comparatively coupled to each other through the sense amplifier circuits 102A, 102B, and the length difference between the first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B is less than or equal to 2 microns. The vertical stacking of the first semiconductor structure 1, the second semiconductor structure 2, and the third semiconductor structure 3 can improve the storage density and integration of the semiconductor device. The two bit lines coupled to the same sensing amplifier circuit 102A, 102B are respectively associated with the second memory unit 202A, 202B and the third memory unit 302A, 302B, which can reduce the coupling capacitance of adjacent bit lines and improve the anti-crosstalk capability. At the same time, the length difference of the connecting line of the two bit lines is less than or equal to 2 microns, which can effectively reduce the delay difference of the signal transmission time and improve the stability and reliability of the circuit.

[0080] In some embodiments of the present application, the first semiconductor structure 1, the second semiconductor structure 2 and the third semiconductor structure 3 are prepared separately and then vertically stacked by wafer bonding, chip bonding or chip-wafer bonding. The first substrate of the first semiconductor structure 1 can be a single crystal silicon wafer, a polycrystalline silicon wafer, a germanium silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon-on-insulator wafer, a germanium-on-insulator wafer, a glass wafer, a III-V compound wafer (such as silicon nitride or gallium arsenide, etc.), an oxide semiconductor wafer or other wafers formed with semiconductor devices. In addition to the sense amplifier circuit, there can also be a word line driver circuit, a power circuit, a clock circuit, and various interface circuits and other control circuits. The second semiconductor structure 2 and the third semiconductor structure 3 respectively include a first memory unit 202A, 202B and a second memory unit 302A, 302B. In general, the second semiconductor structure 2 and the third semiconductor structure 3 can be interchangeable. The naming of the second semiconductor structure 2 and the third semiconductor structure 3 is only for distinction and is not particularly limited. The substrate of the second semiconductor structure 2 and the third semiconductor structure 3 may be a single crystal silicon wafer, a polycrystalline silicon wafer, a germanium silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon on insulator wafer, a germanium on insulator wafer, a glass wafer, a III-V compound wafer (such as silicon nitride or gallium arsenide, etc.), an oxide semiconductor wafer or other wafers formed with memory cells. The memory cell may be a dynamic random access memory, a ferroelectric memory, a resistive random access memory, a magnetic random access memory or other memory cells, and the present application is described by taking a dynamic random access memory cell as an example.

[0081] In some embodiments of the present application, the first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B are relatively coupled to each other through the sense amplifier circuits 102A, 102B. The first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B are wirings with conductive properties that connect the bit lines and the sense amplifier circuits 102A, 102B, and their lengths are the shortest distances for charge transmission from the sense amplifier circuits 102A, 102B to the bit lines. The sense amplifier circuits 102A, 102B transmit the bit line amplified signals to the bit lines through the bit line connection lines, thereby controlling the memory cells. The first bit line connection lines 204A, 204B are associated with the first storage unit, and the second bit line connection lines 304A, 304B are associated with the second storage unit, which can reduce the coupling capacitance between adjacent bit lines, and at the same time prevent signal crosstalk between adjacent bit lines, thereby improving signal integrity and reliability. The length difference between the first bit line connection line 204A, 204B and the second bit line connection line 304A, 304B is less than or equal to 2 microns, and can be 1.8 microns, 1.5 microns, 1.3 microns, 1 micron, 0.8 microns, or other values ​​less than 2 microns. The smaller the length difference, the smaller the time delay difference of signal transmission in the bit line connection line, and the smaller the probability of data reading error, which can improve the stability and reliability of the circuit. The first bit line connection line 204A, 204B and the second bit line connection line 304A, 304B are formed by connecting multiple wiring layers, each of which is a material with conductive properties, for example, it can be at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The material of each wiring layer can be the same or different.

[0082] Continue to refer Figure 1In some embodiments, the first memory unit includes a first memory array 202A and a second memory array 202B, and the first memory array 202A and the second memory array 202B are on the same horizontal plane. The second memory unit includes a third memory array 302A and a fourth memory array 302B, and the third memory array 302A and the fourth memory array 302B are on the same horizontal plane. The first memory unit is located in the first semiconductor structure 2, and the second memory unit is located in the third semiconductor structure 3. The first memory array 202A and the second memory array 202B are stacked in a vertical direction with the third memory array 302A and the fourth memory array 302B. The third memory array 302A overlaps with the first memory array 202A in the vertical direction, and the fourth memory array 302B overlaps with the second memory array 202B in the vertical direction.

[0083] Continue to refer Figure 1 In some embodiments, the first bit line connection line 204A is derived from the sense amplifier circuit 102A and is associated with the first memory array 202A. The second bit line connection line 304A coupled to the sense amplifier circuit 102A in comparison with the first bit line connection line 204A is derived from the sense amplifier circuit 102A and is associated with the second memory array 302A. The first bit line connection line 204B is derived from the sense amplifier circuit 102B and is associated with the first memory array 202B. The second bit line connection line 304A coupled to the sense amplifier circuit 102B in comparison with the first bit line connection line 204B is The connection line 304B is led out from the sensing amplifier circuit 102B and is associated with the second storage array 302B. The third storage array 302A overlaps with the first storage array 202A in the vertical direction. The fourth storage array 302B overlaps with the second storage array 202B in the vertical direction. The first bit line connection line 202A and the second bit line connection line 302A are arranged in parallel. The first bit line connection line 202B and the second bit line connection line 302B are arranged in parallel. The bit line connection line circuits in the second semiconductor structure 2 and the third semiconductor structure 3 can be prepared using the same process to reduce manufacturing costs.

[0084] Figure 2A schematic diagram of a cross-sectional view of another semiconductor device provided by an embodiment of the present application, in some embodiments, a first bit line connection line 204A is led out from a sense amplifier circuit 102A and is associated with a first memory array 202A, a second bit line connection line 304A coupled to the sense amplifier circuit 102A in comparison with the first bit line connection line 204A is led out from the sense amplifier circuit 102A and is associated with a second memory array 302B, a first bit line connection line 204B is led out from the sense amplifier circuit 102B and is associated with the first memory array 202B, and a second bit line connection line 304A coupled to the sense amplifier circuit 102B in comparison with the first bit line connection line 204B is 4B is led out from the sensing amplifier circuit 102B and is associated with the second storage array 302A. The third storage array 302A overlaps with the first storage array 202A in the vertical direction. The fourth storage array 302B overlaps with the second storage array 202B in the vertical direction. The first bit line connection line 202A and the second bit line connection line 302A have different routing directions. The first bit line connection line 202B and the second bit line connection line 302B have different routing directions. The second bit line connection lines 302A and 302B are arranged in a cross-circuitous manner in the third semiconductor structure 3, which can reduce the coupling effect of the bit lines between adjacent storage arrays, improve the anti-interference ability, and enhance the stability and reliability of the semiconductor device.

[0085] Figure 3 for Figure 1 Schematic diagram of a partially enlarged cross-sectional view of the semiconductor structure described in . In some embodiments, the first memory cell includes a first bit line 2021, a first transistor 2022, and a first capacitor 2023, and the first bit line 2021, the first transistor 2022, and the first capacitor 2023 are stacked in a vertical direction. The second memory cell includes a second bit line 3021, a second transistor 3022, and a second capacitor 3023, and the second bit line 3021, the second transistor 3022, and the second capacitor 3023 are stacked in a vertical direction. The first bit line connection line is connected to the first bit line 2021, and the second bit line connection line is connected to the second bit line 3021. The first bit line 2021 is connected to the first transistor 2022 arranged in a direction perpendicular to the cross section, and the second bit line 3021 is connected to the second transistor 3022 arranged in a direction perpendicular to the cross section. The first bit line 2021 and the second bit line 3021 are made of conductive materials, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The first transistor 2022 and the second transistor 3022 are vertical channel transistors, and the channel material can be silicon (Si), polycrystalline silicon (poly-Si, p-Si), amorphous silicon (amorphous-Si, a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO) multi-compound, zinc oxide (ZnO), ITO, titanium dioxide (TiO 2 ), molybdenum disulfide (MoS 2 ), the gate may be a single gate, a double gate, a triple gate or a ring gate, and the gate material is a material with conductive properties, for example, it may be at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The first capacitor 2023 and the second capacitor 3023 are used for information storage, and can be columnar capacitors, box capacitors, barrel capacitors, blade capacitors or other capacitor structures. Similarly, the capacitor can also be a ferroelectric storage capacitor, a phase change memory, a resistive memory, a magnetic memory, and other types of storage units.

[0086] Continue to refer Figure 3 In some embodiments, the second semiconductor structure 2 includes a side close to the first semiconductor structure 1 and a side close to the third semiconductor structure 3, the third semiconductor structure 3 includes a side close to the second semiconductor structure 2 and a side away from the second semiconductor structure 2, the first bit line 2021 is located on a side of the second semiconductor structure 1 close to the third semiconductor structure 3, and the second bit line 3021 is located on a side of the third semiconductor structure 3 close to the second semiconductor structure 2. The first semiconductor structure 1 and the second semiconductor structure 2 are stacked in a manner that the first bit line 2021 and the second bit line 3021 are physically closest to each other, which is conducive to reducing the length difference between the first bit line connection line and the second bit line connection line that are relatively coupled to the same sense amplifier circuit, shortening the time delay difference of signal transmission, and improving the stability and reliability of the circuit.

[0087] Continue to refer Figure 3In some embodiments, the first semiconductor structure 1 further includes a first interconnect structure 103, the first interconnect structure 103 is located on a side of the first semiconductor structure 1 close to the second semiconductor structure 2, the first interconnect structure 103 is connected to the sense amplifier circuit 102, and is bonded to the second semiconductor structure 2. The second semiconductor structure 2 further includes a second interconnect structure 2044, the second interconnect structure 2044 is located on a side of the second semiconductor structure 2 close to the first semiconductor structure 1, and the second interconnect structure 2044 is bonded to the first semiconductor structure 1. The second semiconductor structure 2 further includes a third interconnect structure, the third interconnect structure includes a first through-connection 2043, a first bit line connection 2041, and a first contact 2042, the first through-connection 2043 is connected to the second interconnect structure 2044, the first bit line connection 2041 is connected to the first bit line 2021 and the first through-connection 2043, respectively, the first contact 2042 is located on a side of the second semiconductor structure 2 close to the third semiconductor structure 3, is connected to the first through-connection 2043, and is bonded to the third semiconductor structure 3. The third semiconductor structure 3 also includes a fourth interconnect structure, which includes a second through-connector 3043, a second bit line connector 3041 and a second contact 3042. The second contact 3042 is located on a side of the third semiconductor structure 3 close to the second semiconductor structure 2 and is bonded to the first contact 2042. The second bit line connector 3041 is respectively connected to the second bit line 3021 and the second contact 3042, and the second through-connector 3043 is connected to the second contact 3042.

[0088] Continue to refer Figure 3 In some embodiments, the first interconnect structure 103 is connected to the sense amplifier circuit 102, and then connected to the second semiconductor structure 2 by bonding. The first interconnect structure 103 may include a multi-layer wiring structure, such as 2 layers, 3 layers, 4 layers or more. The first interconnect structure 103 may be used to connect the peripheral circuits on the first semiconductor structure 1, such as the sense amplifier circuit 102, the word line driver circuit, the power supply circuit, the clock circuit, and various interface circuits and other peripheral control circuits, to the second semiconductor structure 2 and the third semiconductor structure 3, thereby improving the storage density and integration. The material of the first interconnect structure 103 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The material of each layer of wiring in the first interconnect structure 103 can be the same or different.

[0089] Continue to refer Figure 3 In some embodiments, the second interconnect structure 2044 and the third interconnect structure including the first through-connector 2043, the first bit line connector 2041 and the first contact 2042 are located in the second semiconductor structure 2. The second interconnect structure 2044 is located on a side of the second semiconductor structure 2 close to the first semiconductor structure 1 and is connected to the first semiconductor structure 1 by bonding. The second interconnect structure 2044 may include a multi-layer wiring structure, such as 2 layers, 3 layers, 4 layers or more. The control signal of the peripheral circuit in the first semiconductor structure 1 is transmitted to the second semiconductor structure 2 and the third semiconductor structure 3 through the second interconnect structure 2044. The material of the second interconnect structure 2044 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of each layer of wiring in the second interconnect structure 2044 can be the same or different. The first through-connector 2043 is connected to the second interconnect structure 2044 to transmit the control signal to the first bit line 2021 and the gate of the first transistor 2022, as well as the third semiconductor structure 3. The length and material of the first through-connector 2043 are set as needed. The first bit line connection line 2041 is connected to the first bit line 2021 and the first through-connector 2043 respectively. The first contact 2042 is located on a side of the second semiconductor structure 2 close to the third semiconductor structure 3, bonded to the third semiconductor structure, and connected to the first through-connector 2043 in the second semiconductor structure 2, and can include a multi-layer wiring structure, such as 2 layers, 3 layers, 4 layers or more. The materials of the first through-connector 2043, the first bit line connector 2041 and the first contact 20424 are conductive materials, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first through connection 2043, the first bit line connection 2041 and the first contact 2042 can be the same or different.

[0090] Continue to refer Figure 3In some embodiments, the second contact 3042 is located on a side of the third semiconductor structure 3 close to the second semiconductor structure 2 and is bonded to the first contact 2042. The second contact 3042 may include a multi-layer wiring structure, such as 2 layers, 3 layers, 4 layers or more. The control signal of the peripheral circuit in the first semiconductor structure 1 is transmitted to the third semiconductor structure 3 through the second contact 3042. The material of the second contact 3042 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The material of each layer of wiring in the second contact 3042 can be the same or different. The second bit line connector 3041 is connected to the second bit line 3021 and the second contact 3042 respectively, and performs signal control on the second bit line 3021. The second through-connector 3043 is connected to the second contact 3042, and can connect the second transistor 3022 and the second capacitor 3023. The material of the second contact 3042, the second bit line connector 3041 and the second through-connector 3043 is a material with conductive properties, for example, it can be at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the second contact 3042, the second bit line connector 3041 and the second through connector 3043 may be the same or different.

[0091] Continue to refer Figure 3In some embodiments, the third semiconductor structure 3 further includes a lead-out structure 305, which is located on a side of the third semiconductor structure 3 away from the second semiconductor structure 2 and connected to the second through-connector 3043. The lead-out structure 305 is connected to the second through-connector 3043, and can transmit power or other control signals outside the semiconductor device to the peripheral control circuit through the second through-connector 3043, the second contact 3042, the first contact 2042, the first through-connector 2043, the second interconnect structure 2044 and the first interconnect structure 103, and then the peripheral control circuit transmits the control signal to the memory array through the first interconnect structure 103, the second interconnect structure 2044, the first through-connector 2043, the first bit line connection 2041, the first contact 2042, the second contact 3042 and the second bit line connection 3041. The lead-out structure 305 may be a single layer or multiple layers. The material of the lead-out structure 305 is a conductive material, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc.

[0092] Continue to refer Figure 3 , combined with Figure 1 and Figure 2In some embodiments, the first bit line connection lines 204A and 204B include a first interconnect structure 103, a second interconnect structure 2044, a first through connection 2043, and a first bit line connection 2041, and the second bit line connection lines 304A and 304B include a first interconnect structure 103, a second interconnect structure 2044, a first through connection 2043, a first contact 2042, a second contact 3042, and a second bit line connection 3041. Or in some embodiments, the first bit line connection lines 204A, 204B include a second interconnect structure 2044, a first through connection 2043, and a first bit line connection 2041, and the second bit line connection lines 304A, 304B include a second interconnect structure 2044, a first through connection 2043, a first contact 2042, a second contact 3042 and a second bit line connection 3041, that is, the first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B are only located in the wire portions in the semiconductor structure 2 and the semiconductor structure 3. The length difference between the first bit line connection line 204A, 204B and the second bit line connection line 304A, 304B can be understood as the optimal conductive length of the first contact member 2042 and the second contact member 3042. Since the first contact member 2042 and the second contact member 3042 are connected together by bonding, the conductive length is relatively short, which can effectively reduce the length difference between the first bit line connection line 204A, 204B and the second bit line connection line 304A, 304B, shorten the time delay difference of signal transmission, and improve the stability and reliability of the circuit.

[0093] Figure 4 for Figure 1 A simplified, three-dimensional schematic diagram of a portion of the semiconductor structure described in . In some embodiments, the second semiconductor structure 2 and the third semiconductor structure 3 are stacked to improve storage density. The second semiconductor structure 2 includes a first bit line 2021, a first transistor 2022 and a first capacitor 2023, and the first bit line 2021, the first transistor 2022 and the first capacitor 2023 are stacked along a third direction (for example, the Z direction). The second semiconductor structure 3 includes a second bit line 3021, a second transistor 3022 and a third capacitor 3023, and the second bit line 3021, the second transistor 3022 and the third capacitor 3023 are stacked along a third direction (for example, the Z direction). The first bit line connection line 204A is connected to the first bit line 2021 through the first bit line connection member 2041, and the second bit line connection line 304A is connected to the second bit line 3021 through the second bit line connection member 3041.

[0094] Continue to refer Figure 4In some embodiments, a plurality of first bit lines 2021 extend along a first direction (e.g., X direction), are arranged at intervals along a second direction (e.g., Y direction), a plurality of first bit line connectors 2041 are connected to the first bit lines 2021 in correspondence, and the connection positions are staggered in the first direction (e.g., X direction), which can increase the process window of the first bit line connectors 2041, and at the same time reduce the coupling between the first bit line connectors 2041, thereby improving the stability and reliability of the circuit. Similarly, a plurality of second bit lines 3021 extend along a first direction (e.g., X direction), are arranged at intervals along a second direction (e.g., Y direction), a plurality of second bit line connectors 3041 are connected to the second bit lines 3021 in correspondence, and the connection positions are staggered in the first direction (e.g., X direction). By comparing the positions where the first bit line connector 2041 and the second bit line connector 3041 coupled to the same sensing amplifier circuit are connected to the first bit line 2021 and to each other, and overlapping in the vertical direction (e.g., Z direction), or the lengths of the first bit line connector 2041 and the second bit line connector 3041 extending along the first direction (e.g., X direction) are equal, the difference in length between the first bit line connector 204A and the second bit line connector 304A extending along the first direction (e.g., X direction) can be minimized.

[0095] Figure 5A , 5B , 5C, 6A, 6B, 7A, 7B, 8 and 9 are a method of forming a Figure 3 The manufacturing process of the semiconductor structure in the method of manufacturing the process is not exhaustive, and other operations may be performed before, after or between any of the operations shown. In addition, some operations may be performed simultaneously or in a different order than shown in the figure.

[0096] refer to Figure 5A In some embodiments, a first substrate 101 is provided, a sense amplifier circuit 102 and a word line driver circuit, a power circuit, a clock circuit, and various interface circuits and other peripheral control circuits are formed on the first substrate 101, and a first interconnection line 103 is formed on the peripheral circuit. Figure 5B and Figure 5CIn some embodiments, a second substrate 201 and a third substrate 301 are provided respectively, and a first memory unit and a second memory unit are formed on the second substrate 201 and the third substrate 301 respectively, the first memory unit includes a first bit line 2021, a first transistor 2022 and a first capacitor 2023, and the first bit line 2021, the first transistor 2022 and the first capacitor 2023 are stacked in a vertical direction, and the second memory unit includes a second bit line 3021, a second transistor 3022 and a second capacitor 3023, and the second bit line 3021, the second transistor 3022 and the second capacitor 3023 are stacked in a vertical direction. The first substrate 101, the second substrate 201 and the third substrate 301 can be a single crystal silicon substrate, a polycrystalline silicon substrate, a germanium silicon substrate, a sapphire substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (such as silicon nitride or gallium arsenide, etc.), an oxide semiconductor substrate or other substrates formed with memory units. The first substrate 101, the second substrate 201 and the third substrate 301 may be the same or different. The first memory cell and the second memory cell may be interchangeable and have no essential difference.

[0097] refer to Fig. 6A and Figure 6B In some embodiments, a first carrier 203 and a second carrier 303 are formed on the second semiconductor structure 2 and the third semiconductor structure 3, respectively. The first carrier 203 and the second carrier 303 may be a single crystal silicon substrate, a polycrystalline silicon substrate, a germanium silicon substrate, a sapphire substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (such as silicon nitride or gallium arsenide), an oxide semiconductor substrate, or other substrates formed with memory cells. The first carrier 203 and the second carrier 303 may be the same or different.

[0098] refer to Fig. 7A and Figure 7BIn some embodiments, the second semiconductor structure 2 and the third semiconductor structure 3 are flipped over respectively, and the second semiconductor substrate 201 and the third semiconductor substrate 301 are removed by cutting and grinding to expose the first bit line 2021 and the second bit line 3021 respectively, and a first bit line connector 2041 and a first contact 2042 are formed in the second semiconductor structure 2, the first bit line connector 2041 is connected to the bit line, and the first contact 2042 is connected to the first bit line connector 2041, and a second bit line connector 3041 and a second contact 3042 are formed in the third semiconductor structure 3, the second bit line connector 3041 is connected to the second bit line 3021, and the second contact 3042 is connected to the second bit line connector 3041. The first bit line connector 2041, the first contact 2042, the second bit line connector 3041 and the second contact 3042 are made of conductive materials, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first bit line connector 2041, the first contact 2042, the second bit line connector 3041 and the second contact 3042 may be the same or different.

[0099] refer to Figure 8 In some embodiments, the second semiconductor structure 2 is flipped over to bond the second semiconductor structure 2 and the third semiconductor structure 3, that is, the first contact 2042 and the second contact 3042 are connected by bonding. The first carrier 203 is removed, and a first through-connector 2043 and a second interconnect structure 2044 are formed in the second semiconductor structure 2. The first through-connector 2043 is connected to the first bit line connector 2041 and the first contact 2042, respectively, and the second interconnect structure 2044 is connected to the first through-connector 2043. The material of the first through-connector 2043 and the second interconnect structure 2044 is a material having conductive properties, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first through-connector 2043 and the second interconnect structure 2044 can be the same or different.

[0100] refer to Fig. 9In some embodiments, the bonding body of the second semiconductor structure 2 and the third semiconductor structure 3 is flipped to bond the second semiconductor structure 2 to the first semiconductor structure 1, that is, the first interconnection structure 103 and the second interconnection structure 2044 are connected by bonding, the second carrier 303 is removed, and a second through-connector 3043 and a lead-out structure 305 are formed in the third semiconductor structure, the second through-connector 3043 is connected to the second contact 3042, and the lead-out structure 305 is located on the surface of the third semiconductor structure and connected to the second through-connector 3043. The material of the second through-connector 3043 and the lead-out structure 305 is a material with conductive properties, for example, it can be at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the second through connector 3043 and the lead-out structure 305 can be the same or different.

[0101] By using the interconnection structure and the through-connector process in the second semiconductor structure 2 and the third semiconductor structure 3, respectively, it is not necessary to use the silicon through-hole process, which reduces the difficulty of process manufacturing, and the formed semiconductor device occupies a small space and has a high storage density. In addition, the back of the second semiconductor structure 2 and the third semiconductor structure 3 is cut and polished to expose the bit line, so that the thickness of the entire second semiconductor structure 2 and the third semiconductor structure 3 is minimized, and then the bit line connector and the back-end connection are formed on the bit line, which can improve the integration of the semiconductor device.

[0102] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor structure comprising a sense amplifier circuit; a second semiconductor structure, the second semiconductor structure being connected to the first semiconductor structure by bonding, the second semiconductor structure comprising a first memory cell; a third semiconductor structure, the third semiconductor structure being connected to the second semiconductor structure by bonding, the third semiconductor structure comprising a second memory cell; a first bit line connection line, the first bit line connection line being associated with the first memory cell; a second bitline connection line, the second bitline connection line being associated with the second memory cell; The first bit line connection line and the second bit line connection line are coupled to the same sense amplifier circuit in comparison with each other; The difference in length between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns; The first memory cell comprises a first bit line, a first transistor and a first capacitor, wherein the first capacitor, the first transistor and the first bit line are stacked in a vertical direction; The second memory cell comprises a second bit line, a second transistor and a second capacitor, wherein the second bit line, the second transistor and the second capacitor are stacked in a vertical direction; The first bit line connection line is connected to the first bit line; The second bit line connection line is connected to the second bit line; The second semiconductor structure includes a side close to the first semiconductor structure and a side close to the third semiconductor structure; The third semiconductor structure comprises a side close to the second semiconductor structure and a side far away from the second semiconductor structure; The first bit line is located on a side of the second semiconductor structure close to the third semiconductor structure; The second bit line is located on a side of the third semiconductor structure close to the second semiconductor structure.

2. The semiconductor device according to claim 1, wherein: The first memory unit includes a first memory array and a second memory array, wherein the first memory array and the second memory array are on the same horizontal plane; The second memory unit includes a third memory array and a fourth memory array, and the third memory array and the fourth memory array are on the same horizontal plane; The third storage array is close to the first storage array, and the fourth storage array is close to the second storage array.

3. The semiconductor device according to claim 2, characterized in that The first bit line connection line is associated with the first memory array; The second bit line connection line is associated with the third memory array.

4. The semiconductor device according to claim 2, characterized in that The first bit line connection line is associated with the first memory array; The second bit line connection line is associated with the fourth memory array.

5. The semiconductor device according to claim 1, wherein: The first semiconductor structure further includes a first interconnect structure, the first interconnect structure is located on a side of the first semiconductor structure close to the second semiconductor structure, the first interconnect structure is connected to a sense amplifier circuit, and is bonded to the second semiconductor structure; The second semiconductor structure further includes a second interconnect structure, which is located on a side of the second semiconductor structure close to the first semiconductor structure, and the second interconnect structure is bonded to the first semiconductor structure; The second semiconductor structure further includes a third interconnect structure, the third interconnect structure including a first through-connector, a first bit line connector and a first contact, the first through-connector is connected to the second interconnect structure, the first bit line connector is respectively connected to the first bit line and the first through-connector, the first contact is located on a side of the second semiconductor structure close to the third semiconductor structure, connected to the first through-connector, and bonded to the third semiconductor structure; The third semiconductor structure also includes a fourth interconnect structure, which includes a second through-connector, a second bit line connector and a second contact. The second contact is located on a side of the third semiconductor structure close to the second semiconductor structure and is bonded to the first contact. The second bit line connector is respectively connected to the second bit line and the second contact, and the second through-connector is connected to the second contact.

6. The semiconductor device according to claim 5, characterized in that The positions where the plurality of first bit line connectors are connected to the plurality of first bit lines are staggered and distributed; Positions where the plurality of second bit line connectors are connected to the plurality of second bit lines are staggered and distributed.

7. The semiconductor device according to claim 5 or 6, characterized in that: The effective length of the first bit line connection is equal to the effective length of the second bit line connection coupled to the same sense amplifier circuit.

8. The semiconductor device according to claim 5, characterized in that The third semiconductor structure further includes a lead-out structure, which is located on a side of the third semiconductor structure away from the second semiconductor structure and connected to the second through-connector.

9. A method for preparing a semiconductor device, characterized in that: providing a first semiconductor structure in which a sense amplifier circuit is formed; providing a second semiconductor structure, forming a first memory cell in the second semiconductor structure; providing a third semiconductor structure in which a second memory cell is formed; forming a third semiconductor structure on the second semiconductor structure by bonding; forming a second semiconductor structure on the first semiconductor structure by bonding; forming a first bit line connection line, the first bit line connection line being associated with the first memory cell; forming a second bit line connection line, the second bit line connection line being associated with the second memory cell; The first bit line connection line and the second bit line connection line are coupled to the same sense amplifier circuit in comparison with each other; The difference in length between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns; The first memory cell comprises a first bit line, a first transistor and a first capacitor, wherein the first capacitor, the first transistor and the first bit line are stacked in a vertical direction; The second memory cell comprises a second bit line, a second transistor and a second capacitor, wherein the second bit line, the second transistor and the second capacitor are stacked in a vertical direction; The first bit line connection line is connected to the first bit line; The second bit line connection line is connected to the second bit line; The second semiconductor structure includes a side close to the first semiconductor structure and a side close to the third semiconductor structure; The third semiconductor structure comprises a side close to the second semiconductor structure and a side far away from the second semiconductor structure; The first bit line is located on a side of the second semiconductor structure close to the third semiconductor structure; The second bit line is located on a side of the third semiconductor structure close to the second semiconductor structure.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: Providing a first semiconductor structure, forming a sense amplifier circuit in the first semiconductor structure includes: providing a first substrate, forming the sense amplifier circuit and the first interconnect structure on the first substrate; Forming a first memory cell in the second semiconductor structure includes: Providing a second substrate, forming a first bit line, a first transistor and a first capacitor on the second substrate, wherein the first bit line, the first transistor and the first capacitor are stacked in a vertical direction; Forming a second memory cell in the third semiconductor structure includes: A third substrate is provided, on which a second bit line, a second transistor, and a second capacitor are formed, wherein the second bit line, the second transistor, and the second capacitor are stacked in a vertical direction.

11. The method for manufacturing a semiconductor device according to claim 10, wherein forming a third semiconductor structure on the second semiconductor structure by bonding comprises: forming a first carrier and a second carrier on the second semiconductor structure and the third semiconductor structure respectively; flipping the second semiconductor structure and the third semiconductor structure, and removing the second substrate and the third substrate; forming a first bit line connection and a first contact in the second semiconductor structure; forming a second bit line connection and a second contact in the third semiconductor structure; The second semiconductor structure is turned over to bond the second semiconductor structure to the third semiconductor structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein forming a second semiconductor structure on the first semiconductor structure by bonding comprises: removing the first carrier and forming a first through-connector and a second interconnect structure in the second semiconductor structure; The second semiconductor structure is turned over to bond the second semiconductor structure to the first semiconductor structure.

13. The method for preparing a semiconductor device according to claim 12, further comprising: after the second semiconductor structure and the first semiconductor structure are bonded together: The third carrier is removed, and a second through-connector and a lead-out structure are formed in the third semiconductor structure.

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