A method for sending pattern files in multiple channels based on temporary cache

Abstract

The present invention provides a method for sending a pattern file in multiple channels based on temporary caching, comprising a host computer, the host computer sends a pattern file to a motherboard, the motherboard is respectively connected to a plurality of daughterboards, the pattern file includes a plurality of pattern sub-files, the motherboard receives and temporarily caches the pattern file, the motherboard parses the pattern file to determine a pin title and a plurality of rows of data, the row data includes a plurality of unit vectors in the same arrangement order as the pin title; the pin title and the channel of the corresponding daughterboard distribute the unit vectors in the row data to the corresponding channel of the corresponding daughterboard according to the arrangement order of the pin title, and the row vectors are distributed in sequence using the same method until all the row vectors are sent, thereby realizing the synchronous sending of a plurality of pattern sub-files. The present invention distributes the pattern file according to the parsing result by temporarily caching a pattern file containing a plurality of pattern sub-files, thereby realizing the synchronous sending of the pattern sub-files of different chips.

Description

Technical Field

[0001] The present invention relates to the technical field of pattern file sending, and in particular to a method for sending pattern files in multiple channels based on temporary cache. Background Art

[0002] With the development of automation in the electronic industry, the demand for chips in various industries is increasing. Along with the mass production of chips, the characteristics and functions of the chips need to be tested in detail before they are officially sold and applied.

[0003] In the prior art, a pattern file only records the test vectors of all pins of a chip under test. After the pattern file is sent to the motherboard, the daughterboard connected to the motherboard can only synchronously test the same model of the chip under test. When testing multiple models of chips under test, the pattern file needs to be sent multiple times, and then each model of the chip under test is tested separately, which has low test efficiency. Summary of the invention

[0004] In view of this, the problem to be solved by the present invention is to provide a method for multi-channel distribution of pattern files based on temporary cache, which can synchronously distribute pattern sub-files of different chips under test and realize synchronous testing of different chips under test.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for multi-channel sending of pattern files based on temporary cache, comprising a host computer, the host computer sends the pattern file to a motherboard, the motherboard is respectively connected to a plurality of daughterboards, the pattern file includes a plurality of pattern sub-files, the motherboard receives and temporarily caches the pattern file, the pattern file includes a vector file, the vector file includes a header line and a plurality of row vectors, the motherboard parses the vector file to determine the pin title and a plurality of row data, the row data includes a plurality of unit vectors corresponding to the arrangement order of the pin title;

[0006] Different pin titles correspond to different sub-board channels. The unit vectors in the row data are distributed to the corresponding sub-board channels according to the arrangement order of the pin titles. The row vectors are distributed in sequence using the same method until all row vectors are issued, thereby realizing the synchronous issuance of multiple pattern sub-files.

[0007] Furthermore, the title row includes an execution code title, a timestamp title, and several pin titles, and the row vector includes an execution code, a timestamp name, and several unit vectors, and the arrangement order is consistent with the title order.

[0008] Furthermore, the pattern file includes a Pin file and a timestamp file, wherein the Pin file records a pin title and sub-board channel information corresponding to the pin title, and the timestamp file records a timestamp name and timestamp information corresponding to the timestamp name.

[0009] Furthermore, the motherboard distributes the timestamp file to all the daughterboards.

[0010] Furthermore, the chips under test on each of the daughter boards are not completely the same.

[0011] Furthermore, each of the unit vectors occupies the same number of bytes, and each of the timeset names occupies the same number of bytes.

[0012] The advantages and positive effects of the present invention are:

[0013] By temporarily storing a pattern file containing multiple pattern sub-files to the motherboard, the motherboard parses the pattern file to determine the sending path of the unit vector, timeset information, and execution code in the row data, and distributes the unit vector, timeset information, and execution code according to the sending path, multiple different pattern sub-files can be sent simultaneously, thereby improving the testing efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0015] Figure 1 It is an overall system diagram of a method for sending pattern files in multiple channels based on temporary cache according to the present invention;

[0016] Figure 2 It is a vector file diagram of a method for sending pattern files in multiple channels based on temporary cache of the present invention;

[0017] Figure 3 It is a timestamp file diagram of a method for sending pattern files in multiple channels based on temporary cache in the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] The present invention provides a method for sending pattern files in multiple channels based on temporary cache, such as Figure 1 As shown, the chip testing system includes: a host computer, a motherboard and a daughterboard. The host computer is used to edit or modify the pattern file and send it to the motherboard. The motherboard temporarily stores and parses the pattern file and determines the distribution path and distribution content based on the parsing results. The motherboard is connected to several daughterboards to communicate with different daughterboards. The daughterboard receives the data sent by the motherboard and forms a pattern subfile.

[0021] When actually testing the chip, the chips under test on each daughter board may not be exactly the same. The motherboard distributes the pattern sub-file to the corresponding daughter board. The daughter board parses the pattern sub-file and outputs the test vector to test the performance of the chip under test.

[0022] The pattern file includes vector files, Pin files and timestamp files. The vector file includes several rows of data and header rows. The header row includes the execution code header, the timestamp header and several pin headers. The row data includes the execution code, the timestamp name and several unit vectors. The number of unit vectors is the same as the number of pin headers. The order of the execution code, the timestamp name and several unit vectors is the same as the order of the execution code header, the timestamp header and several pin headers.

[0023] The Pin file includes several pin titles and the sub-board channel information corresponding to the pin titles. The motherboard can determine the sub-board channel corresponding to each pin title by parsing the Pin file, so that the motherboard can determine the execution code, timeset name, and the distribution path of the unit vector based on the pin title. The timeset file includes several timeset names and the timeset information corresponding to the timeset name. The motherboard distributes the timeset file to different sub-boards, and the sub-boards parse the received pattern sub-files based on the timeset file.

[0024] The process of sending the pattern file in multiple channels is as follows: the motherboard sends the timestamp file to all daughterboards, the motherboard receives and parses the vector file in the pattern file to obtain the execution code title, timestamp title, and several pin titles, and determines the order of the execution code, timestamp name, and several unit vectors in the row data according to the order of the titles. The motherboard parses the pin file to determine the daughterboard channel defined by the pin title, distributes each unit vector in the row data to the corresponding daughterboard channel, and distributes the timestamp name and execution code to all daughterboard channels according to the daughterboard channel.

[0025] After completing the distribution of a single row of data, use the same method to distribute the execution code, timeset name, and unit vector in all rows of data in sequence until all rows of data are distributed.

[0026] like Figure 2 As described above, the execution code includes none (output a level, 1 for high level or 0 for low level), keepalive (keep output), repeat (repeat output), etc., the timeset name includes TS1, TS2, and the unit vector includes 0 (set to 0), 1 (set to 1), X (compare), L (voltage pull down), H (voltage pull up), etc. The execution code title includes opcode, and the timeset title includes timeset. Figure 3 As shown, this is the timestamp file.

[0027] The pin headers include A0, A1, A2, A3...A14, A15, A15, etc. Each pin header corresponds to a daughter board channel, for example: A0 corresponds to channel 1 of the first daughter board, A1 corresponds to channel 2 of the first daughter board...A8 corresponds to channel 1 of the second daughter board...A15 corresponds to channel 8 of the second daughter board.

[0028] An embodiment of the present application is: the motherboard parses the Pin file to determine the delivery path of each Pin title.

[0029] When the motherboard parses the header line in the vector file, it determines the opcode (execution code header), timestamp (timeset header), A0, A1, A2, A3…A14, A15, A16 and the order of arrangement. The execution code, timestamp name, and unit vector are recorded in the fixed position and fixed byte segment in the row data, and the order is consistent with the header.

[0030] One row of data includes: none, TS2, 1, H, 0, 1, 1…1, 1, L. None is sent down through the 16 daughter board channels corresponding to A0, A1…A15, TS2 is sent down through the 16 daughter board channels corresponding to A0, A1…A15, 1 is sent down to channel 1 of the first daughter board through the daughter board channel corresponding to A0, H is sent down to channel 2 of the first daughter board through the sending channel corresponding to A1, 0 is sent down to channel 3 of the first daughter board through the sending channel corresponding to A2…L is sent to channel 8 of the second daughter board through the sending channel corresponding to A15.

[0031] Use the same method to distribute the execution code, timestamp name, and unit vector in all rows of data, and then distribute the timestamp file to all sub-boards to complete the synchronous distribution of the pattern sub-file. The sub-board parses the timestamp file and can output the test vector during the distribution of the pattern sub-file to test the chip performance, save test time, and improve test efficiency. In particular, when there is no jump instruction in the execution code of the pattern sub-file, the test action can be performed while being distributed.

[0032] To increase the distribution speed, the unit vectors in each row of data occupy the same number of bytes and are in a fixed position. The timestamp name in each row of data occupies the same number of bytes and is in a fixed position. When distributing vector files, you only need to parse the header name and execution code.

[0033] An embodiment of the present application is that the execution code, timestamp name and unit vector in each row of data occupy the same number of bytes and have a fixed position, and correspond to the order of the title name, and the distribution of the vector file can be achieved by only parsing the title name.

[0034] One embodiment of the present application is: the timestamp file includes the timestamp name and timestamp information, and the execution code, timestamp name and unit vector in each row of data occupy the same number of bytes and are fixed in position. When distributing the pattern file, the title name and timestamp name are parsed, and the timestamp information is distributed to all sub-board channels according to the timestamp name. When distributing the pattern sub-file, the test vector is output to test the chip performance and improve the chip testing efficiency.

[0035] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent.

Claims

1. A method for sending pattern files in multiple channels based on temporary cache, characterized in that: The method comprises a host computer, wherein the host computer sends a pattern file to a motherboard, wherein the motherboard is respectively connected to a plurality of daughterboards, wherein the pattern file comprises a plurality of pattern sub-files, wherein the motherboard receives and temporarily caches the pattern file, wherein the pattern file comprises a vector file, wherein the vector file comprises a header line and a plurality of row vectors, wherein the motherboard parses the vector file to determine a pin title and a plurality of row data, wherein the row data comprises a plurality of unit vectors corresponding to an arrangement order of the pin titles, wherein the pattern file comprises a pin file, wherein the pin file records the pin title and the daughterboard channel information corresponding to the pin title; Different pin titles correspond to different sub-board channels. The unit vectors in the row data are distributed to the corresponding sub-board channels according to the arrangement order of the pin titles. The row vectors are distributed in sequence using the same method until all row vectors are distributed, thereby realizing the synchronous distribution of multiple pattern sub-files. The title row includes an execution code title, a timestamp title, and several pin titles. The row vector includes an execution code, a timestamp name, and several unit vectors, and the arrangement order is consistent with the title order. The test vector is output while distributing the pattern sub-file. The sub-board parses the pattern sub-file and outputs the test vector to test the chip performance and improve the chip test efficiency. The motherboard parses the Pin file to determine the daughterboard channel corresponding to each pin title, so that the motherboard can determine the execution code, timeset name, and the sending path of the unit vector according to the pin title, and distribute the unit vector, timeset information, and execution code according to the sending path.

2. A method for sending pattern files in multiple channels based on temporary cache according to claim 1, characterized in that: The pattern file includes a timestamp file, and the timestamp file records a timestamp name and timestamp information corresponding to the timestamp name.

3. A method for sending pattern files in multiple channels based on temporary cache according to claim 2, characterized in that: The motherboard distributes the timestamp file to all daughterboards.

4. The method for sending pattern files in multiple channels based on temporary cache according to claim 1, characterized in that: The chips under test on each of the daughter boards are not completely the same.

5. The method for sending pattern files in multiple channels based on temporary cache according to claim 1, characterized in that: Each of the unit vectors occupies the same number of bytes, and each of the timeset names occupies the same number of bytes.

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