A method for preparing a surface acoustic wave device and a surface acoustic wave device

Abstract

The present invention discloses a preparation method of a surface acoustic wave device and a surface acoustic wave device, and relates to the technical field of radio frequency devices. The present invention firstly dopes deep energy level impurities during the growth process of single crystal silicon or silicon carbide to obtain doped silicon or doped silicon carbide doped with deep energy level impurities, and uses the doped silicon or doped silicon carbide as a supporting substrate, and then prepares silicon dioxide on the doped silicon or doped silicon carbide as the supporting substrate to form a temperature compensation layer, and then prepares a piezoelectric single crystal film on the temperature compensation layer to form a piezoelectric layer, and deposits interdigital electrodes on the piezoelectric layer. When the present invention prepares a supporting substrate based on single crystal silicon or silicon carbide with the same resistivity, no additional process is required, and the effect of suppressing the parasitic surface conductivity effect is improved. Therefore, the requirement for the suppression effect of the same parasitic surface conductivity effect is reduced, and the requirement for the resistivity of single crystal silicon or silicon carbide is reduced, thereby reducing the requirement for the growth process of single crystal silicon or silicon carbide and improving the applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency devices, and in particular to a preparation method of a surface acoustic wave device and a surface acoustic wave device. Background Art

[0002] Currently, due to the parasitic surface conductivity (PSC) effect, the performance of RF devices based on silicon (Si)-based surface acoustic wave (SAW) devices is greatly reduced.

[0003] The piezoelectric substrate of the surface acoustic wave device usually uses high-resistance silicon as the supporting substrate, and a temperature compensation layer formed by silicon dioxide (SiO2) is prepared on the high-resistance silicon. However, the fixed charge at the Si-SiO2 interface will attract free carriers to the vicinity of the interface, thereby inducing a conductive layer, reducing the effective resistivity of the supporting substrate Si, which is the PSC effect, and increasing the RF loss of the SAW device.

[0004] In the prior art, an additional trap-rich layer (trap-rich) is generally inserted between Si and SiO2, such as a polysilicon layer, to suppress the PSC effect and improve the performance of the SAW device. In addition, for RF devices, if the substrate resistivity is above 3kΩcm, its RF loss can usually be ignored. Since the supporting substrate formed of semi-insulating silicon carbide (SiC) has a resistivity of more than 1e10Ωcm, there are also silicon carbide-based SAW devices in the prior art. Conventional SiC-based SAW device composite substrates are usually composed of three parts, from top to bottom, namely, a piezoelectric layer, a SiO2 temperature compensation layer, and a SiC supporting substrate.

[0005] However, when preparing SAW devices with silicon-based supporting substrates and suppressing the PSC effect, not only do additional processes need to be performed, but also, despite the use of a trap-rich layer, a high concentration of free carriers are still concentrated at the trap-rich layer / silicon interface, which has limited improvement on PSC. Silicon carbide-based SAW devices are also affected by the PSC effect, which increases the RF loss of SAW devices and reduces the performance of SAW devices. Currently, high-resistivity Si or SiC is still required as a supporting substrate, which has poor applicability. Summary of the invention

[0006] Based on this, it is necessary to provide a method for preparing a surface acoustic wave device and a surface acoustic wave device in order to solve the above technical problems.

[0007] The present invention adopts the following technical solutions:

[0008] The present invention provides a method for preparing a surface acoustic wave device. First, deep energy level impurities are doped during the growth process of single crystal silicon or silicon carbide to obtain doped silicon or doped silicon carbide doped with deep energy level impurities, and the doped silicon or doped silicon carbide is used as a supporting substrate. Then, silicon dioxide is prepared on the doped silicon or doped silicon carbide serving as the supporting substrate to form a temperature compensation layer. After that, a piezoelectric single crystal film is prepared on the temperature compensation layer to form a piezoelectric layer, and interdigital electrodes are deposited on the piezoelectric layer.

[0009] The present invention provides a surface acoustic wave device, which comprises, from bottom to top, a supporting substrate, a temperature compensation layer, a piezoelectric layer and interdigital electrodes, wherein the temperature compensation layer is located on the supporting substrate, the piezoelectric layer is located on the temperature compensation layer, the interdigital electrodes are deposited on the piezoelectric layer, the supporting substrate is doped silicon or doped silicon carbide doped with deep energy level impurities, the doped silicon or doped silicon carbide is obtained by doping deep energy level impurities during the growth process of single crystal silicon or silicon carbide, the temperature compensation layer is silicon dioxide, and the piezoelectric layer is a piezoelectric single crystal film.

[0010] At least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:

[0011] By doping deep energy level impurities during the growth process of single crystal silicon or silicon carbide, the deep energy level impurities are uniformly distributed in the obtained doped silicon or doped silicon carbide, and the free carriers in the doped silicon or doped silicon carbide are captured by the uniformly distributed deep energy level impurities. When a supporting substrate is prepared based on single crystal silicon or silicon carbide with the same resistivity, no additional process is required, and the effect of suppressing the PSC effect is improved. The demand for the same PSC effect suppression effect reduces the requirement for the resistivity of single crystal silicon or silicon carbide, thereby reducing the requirement for the growth process of single crystal silicon or silicon carbide and improving applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0013] Figure 1 A schematic flow chart of a method for preparing a surface acoustic wave device provided by the present invention;

[0014] Figure 2 A schematic diagram of a process flow of a SAW device manufactured based on ion beam slicing and bonding technology provided by the present invention, Figure 2 (a) is a schematic diagram of SiO2 deposition, and (b) is a schematic diagram of He + Schematic diagram of ion implantation to form a piezoelectric layer, (c) schematic diagram of piezoelectric layer bonding, (d) schematic diagram of annealing and splitting, and (e) schematic diagram of chemical mechanical polishing;

[0015] Figure 3A schematic diagram of a surface acoustic wave device provided by the present invention Figure 1 ;

[0016] Figure 4 A schematic diagram of a surface acoustic wave device provided by the present invention Figure 2 ;

[0017] Figure 5 A schematic diagram of a surface acoustic wave device provided by the present invention Figure 3 ;

[0018] Figure 6 A schematic diagram of the effect of donor impurity concentration on the resistivity of single crystal Si during the growth process of single crystal Si provided by the present invention;

[0019] Figure 7 A schematic diagram showing a comparison of the free carrier concentration near the interface when a support substrate is prepared based on single crystal Si with a resistivity of 10 kΩ∙cm and a support substrate is prepared based on doped silicon provided by the present invention;

[0020] Figure 8 A schematic diagram of effective resistivity at 2 GHz under deep level doping for single crystal silicon with different resistivity provided by the present invention;

[0021] Fig. 9 A schematic diagram of the Bode Q peak of a SAW device under deep level doping for single crystal silicon with different resistivities provided by the present invention;

[0022] Fig.10 A schematic diagram of the PSC effect suppression effect of different schemes of a silicon-based substrate provided by the present invention;

[0023] Fig.11 Schematic diagram of the effect of effective donor concentration on SiC resistivity during growth;

[0024] Fig.12 The change of Fermi level of SiC with different resistivity before and after vanadium doping is shown;

[0025] Fig.13 The variation of carrier concentration with depth near the interface of high-purity SiC and vanadium-doped SiC under the influence of PSC is shown;

[0026] Fig.14 The variation of carrier concentration with depth near the interface of SiC+poly-Si structure under the influence of PSC is shown;

[0027] Fig.15 The variation of effective resistivity with frequency of high-purity SiC, SiC+poly-Si, and vanadium-doped SiC under the influence of PSC is compared;

[0028] Fig.16The effective resistivity of SiC with different initial resistivity is shown, and PSC is suppressed by vanadium doping and poly-Si addition respectively.

[0029] Fig.17 The figure shows the change of Bode Q peak with initial SiC resistivity for SiC with different initial resistivity, which is suppressed by vanadium doping and poly-Si addition, respectively. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] At present, due to the fixed charge at the Si / Si-SiO2 interface, free carriers are attracted to the vicinity of the interface, which reduces the effective resistivity of the supporting substrate and increases the RF loss of the device.

[0032] The technical solutions provided by various embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0033] Figure 1 The present invention is a schematic flow chart of a method for preparing a surface acoustic wave device, which specifically includes the following steps:

[0034] S101: doping deep energy level impurities during the growth process of single crystal silicon or silicon carbide to obtain doped silicon or doped silicon carbide doped with deep energy level impurities, and using the doped silicon or doped silicon carbide to prepare a supporting substrate.

[0035] S102: preparing silicon dioxide on a supporting substrate to form a temperature compensation layer.

[0036] S103: preparing a piezoelectric single crystal thin film on the temperature compensation layer to form a piezoelectric layer, and depositing interdigital electrodes on the piezoelectric layer.

[0037] The performance of SAW devices based on bulk lithium niobate (LiNbO3) or lithium tantalate (LiTaO3) is limited, and the performance of SAW devices can be further improved by using micron-scale piezoelectric films and non-piezoelectric substrate bonding schemes. SAW devices made based on ion beam dicing bonding technology have excellent performance. Figure 2 It is a schematic diagram of the process flow of a SAW device manufactured based on smart-cut in the present invention. Figure 2 The part marked (a) is the SiO2 deposition diagram, and the part marked (b) is the He +Schematic diagram of ion implantation to form a piezoelectric layer, part (c) is a schematic diagram of piezoelectric layer bonding, part (d) is a schematic diagram of annealing and splitting, and part (e) is a schematic diagram of chemical mechanical polishing. The resulting surface acoustic wave device is shown in Figure 1. Figure 3 As shown, Figure 3 A schematic diagram of a surface acoustic wave device in the present invention Figure 1 ,Depend on Figure 3 It can be seen that the surface acoustic wave device provided by the present invention comprises, from bottom to top, doped silicon doped with deep energy level impurities as a supporting substrate, a temperature compensation layer, a piezoelectric layer and interdigital electrodes.

[0038] The bottom layer of doped silicon is obtained by doping deep energy level impurities during the growth of single crystal silicon. Further, in one or more embodiments of the present invention, in step S101, during the growth of n-type single crystal silicon with a resistivity of 10 kΩ∙cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon is greater than or equal to 3e16 / cm 3 Deep energy level impurities, such as vanadium (V), are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.34eV~0.56 eV below the top of the conduction band of the doped silicon. Among them, the donor ionization concentration of the n-type single crystal silicon is 4.6e11 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.44eV below the conduction band. Based on this, doped silicon is prepared as a supporting substrate, thereby effectively suppressing PSC. It should be noted that the closer the position of the doping element is to the top of the conduction band of the single crystal silicon, the worse the effect of the SAW device on suppressing the PSC effect.

[0039] Further, in one or more embodiments of the present invention, in step S101, during the growth of n-type single crystal silicon with a resistivity of 5 kΩ∙cm, the concentration of the doping element at the Fermi level in the band gap of the single crystal silicon may be greater than or equal to 5e16 / cm 3 Deep energy level impurities, such as manganese (Mn) and chromium (Cr), are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.35eV-0.56 eV below the top of the conduction band of the doped silicon. Among them, the donor ionization concentration of the n-type single crystal silicon is 9.2e11 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.42eV below the conduction band. Based on this, doped silicon is prepared as a supporting substrate, thereby effectively suppressing PSC. It should be noted that the closer the position of the doping element is to the top of the conduction band of the single crystal silicon, the worse the effect of the SAW device on suppressing the PSC effect.

[0040] Further, in one or more embodiments of the present invention, in step S101, during the growth of single crystal silicon with a resistivity of 2 kΩ∙cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon may be greater than or equal to 8e16 / cm 3Deep energy level impurities, such as scandium (Sc), are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.37eV-0.56 eV below the top of the conduction band of the doped silicon. Among them, the donor ionization concentration of the n-type single crystal silicon is 2.3e12 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.39 eV below the conduction band. Based on this, doped silicon is prepared as a supporting substrate, thereby effectively suppressing PSC. It should be noted that the closer the position of the doping element is to the top of the conduction band of the single crystal silicon, the worse the effect of the SAW device on suppressing the PSC effect.

[0041] For n-type doped Si, doping energy levels below the Fermi level have no effect, and above the Fermi level, the farther away from the Fermi level, the worse the effect.

[0042] Of course, the support substrate can also be prepared based on doped silicon carbide. In one or more embodiments of the present invention, during the growth of silicon carbide, an element concentration of 5e14 / cm 3 ~1e18 / cm 3 The vanadium (V) element within the range makes the effective donor concentration of doped silicon carbide less than 1e6 / cm 3 , and the energy level of the vanadium element is above the Fermi level in the forbidden band of silicon carbide. Thus, doped silicon carbide is formed, and the doped silicon carbide doped with deep energy level impurities is used as a supporting substrate. The resulting surface acoustic wave device is as follows Figure 4 As shown, Figure 4 A schematic diagram of a surface acoustic wave device in the present invention Figure 2 .Depend on Figure 4 It can be seen that in one or more embodiments of the present invention, the surface acoustic wave device may include a supporting substrate, a temperature compensation layer, a piezoelectric layer and interdigital electrodes formed of doped silicon carbide from bottom to top.

[0043] Among them, by controlling the elements and element concentrations of deep energy level impurities doped during the growth of silicon carbide, the deep energy level impurities in silicon carbide can be evenly distributed. On the other hand, when doping vanadium, the deep energy level acceptor center formed by vanadium in silicon carbide is usually located 0.8eV below the top of the conduction band. By controlling the element concentration of the doped vanadium element, it can be ensured that the energy level of vanadium in the doped silicon carbide after doping is above the Fermi level, that is, the effective donor concentration of doped silicon carbide should be less than 1e6 / cm 3 , so that the resistivity remains above 1e10Ω∙cm. At this time, the energy level of the vanadium element is above the Fermi level in the silicon carbide band gap and can serve as an effective trap center.

[0044] The preparation of the remaining temperature compensation layer, piezoelectric layer and interdigital electrodes has been relatively mature, and the present invention will not elaborate on this.

[0045] In addition, in one or more embodiments of the present invention, a trap-rich layer can be formed by depositing a polysilicon (poly-Si) layer on top of the formed silicon carbide crystal. Among them, silicon carbide crystal has the advantages of high thermal conductivity and high sound velocity. The high thermal conductivity and high sound velocity of SiC crystal can greatly improve the thermal and acoustic performance of SAW devices.

[0046] In the process of growing polysilicon on top of the formed silicon carbide crystal, the grain size and structure of the polysilicon can be adjusted by controlling the growth conditions (such as temperature, pressure, gas flow rate, etc.), thereby affecting the characteristics of the trap layer. In one or more embodiments of the present invention, the grain size of the polysilicon can be less than or equal to 5 microns. The free carriers in the silicon carbide are captured by the inherent fractures in the polysilicon, thereby suppressing the PSC effect. The resulting surface acoustic wave device is as follows Figure 5 As shown, Figure 5 A schematic diagram of a surface acoustic wave device in the present invention Figure 3 ,Depend on Figure 5 It can be seen that the surface acoustic wave device provided by the present invention may include a supporting substrate, a temperature compensation layer, a piezoelectric layer and interdigital electrodes formed from bottom to top by silicon carbide and a trap-rich layer.

[0047] based on Figure 1 The method for preparing the surface acoustic wave device shown in the figure first dopes deep energy level impurities during the growth process of single crystal silicon or silicon carbide to obtain doped silicon or doped silicon carbide doped with deep energy level impurities, and use the doped silicon or doped silicon carbide to prepare a supporting substrate, then prepare silicon dioxide on the doped silicon as the supporting substrate to form a temperature compensation layer, then prepare a piezoelectric single crystal film on the silicon dioxide to form a piezoelectric layer, and deposit interdigital electrodes on the piezoelectric layer. Based on this, doped silicon or doped silicon carbide is prepared to prepare a supporting substrate, thereby effectively suppressing PSC.

[0048] Based on the above-mentioned method for preparing a surface acoustic wave device, the present invention further provides a surface acoustic wave device, comprising: a supporting substrate, a temperature compensation layer, a piezoelectric layer and interdigital electrodes; the temperature compensation layer is located on the supporting substrate, the piezoelectric layer is located on the temperature compensation layer, and the interdigital electrodes are deposited on the piezoelectric layer;

[0049] The supporting substrate is doped silicon or doped silicon carbide doped with deep energy level impurities, and the doped silicon or doped silicon carbide is obtained by doping deep energy level impurities during the growth process of single crystal silicon or silicon carbide. The temperature compensation layer is silicon dioxide, and the piezoelectric layer is a piezoelectric single crystal film.

[0050] Figure 6 Schematic diagram of the effect of donor impurity concentration on the resistivity of single crystal Si during the growth process of single crystal Si in the present invention, Figure 6 In the figure, the horizontal axis represents the concentration of ionized donor impurities introduced during the growth of single crystal Si, and the vertical axis represents the resistivity of single crystal Si. Figure 6It can be seen that as the concentration of the introduced ionized donor impurities increases, the resistivity of single crystal Si decreases.

[0051] Figure 7 It is a schematic diagram comparing the free carrier concentration near the interface when a supporting substrate is prepared based on single crystal Si with a resistivity of 10 kΩ∙cm and a supporting substrate is prepared based on doped silicon obtained by doping deep energy level impurities during the growth process of single crystal Si with a resistivity of 10 kΩ∙cm in the present invention, Figure 7 In the figure, the horizontal axis represents the distance from the SiO2 / Si interface (positive in the direction of Si), and the vertical axis represents the concentration of free carriers. Figure 7 It can be seen that the use of doped Si greatly reduces the free carrier concentration near the SiO2 / Si interface.

[0052] Figure 8 Schematic diagram of effective resistivity corresponding to a single crystal Si growth process with different donor concentrations after doping with an element whose impurity energy level is at the Fermi level of single crystal silicon in the present invention, Figure 8 In the figure, the horizontal axis represents the resistivity of the single crystal Si obtained in the corresponding growth process, and the vertical axis represents the effective resistivity at 2 GHz, which is used to measure the RF loss of the bonding substrate. Figure 8 It can be seen that the higher the resistivity of the single crystal Si obtained in the corresponding growth process, the higher the effective resistivity of the bonded substrate; and when the resistivity of single crystal silicon is around 1 kΩ∙cm, the effective resistivity value is as high as 10 kΩ∙cm, and the resistivity requirement for single crystal silicon is reduced to around 1 kΩ∙cm.

[0053] Generally, the single crystal silicon substrate preparation process can be divided into the Czochralski method and the floating zone melting method. The Czochralski method is also called the Czochralski (CZ) method. The resistivity of single crystal silicon grown by the CZ method is usually around 1 kΩ∙cm, but single crystal silicon of a larger size can be grown, such as single crystal silicon with a diameter of 300 mm. The floating zone melting method can grow single crystal silicon with a resistivity of more than 5 kΩ∙cm, but the maximum diameter of single crystal silicon grown based on the floating zone melting method is 200 mm. Based on the scheme of introducing deep energy level impurity doping in the single crystal silicon growth process used in the present invention, the demand for the single crystal silicon growth process is reduced, and a larger supporting substrate can be formed.

[0054] Fig. 9 The Bode Q peak diagram of the SAW device corresponding to the element doped with the impurity energy level at the Fermi level of single crystal silicon for a single crystal Si growth process with different donor concentrations in the present invention is shown in FIG. Fig. 9 In the figure, the horizontal axis represents the resistivity of the single crystal Si obtained in the corresponding growth process, and the vertical axis represents the Bode Q peak value of the SAW resonator. Fig. 9It can be seen that the higher the resistivity of the single crystal Si obtained in the corresponding growth process, the higher the Bode Q peak of the SAW resonator; the resistivity requirement for single crystal silicon is reduced to about 1 kΩ∙cm, which reduces the demand for the single crystal silicon growth process.

[0055] Fig.10 Schematic diagram of the inhibitory effect of a different scheme in the present invention on the PSC effect. Fig.10 In the figure, the horizontal axis represents the distance from the SiO2 / Si interface (positive in the direction of Si), and the vertical axis represents the concentration of free carriers. Fig.10 It can be seen that when using a silicon + polysilicon structure, although the carrier concentration decreases near the polysilicon region, as the distance from the interface increases and the carrier concentration gradually penetrates into the silicon substrate, it rises again. The use of the doped silicon support substrate in the present invention can keep the free carrier concentration at a low level.

[0056] Fig.11 Schematic diagram of the effect of effective donor concentration on the resistivity of SiC crystal during the growth process. Fig.11 In the figure, the horizontal axis represents the effective donor concentration introduced during the growth of SiC crystal, and the vertical axis represents the resistivity of SiC crystal. Fig.11 It can be seen that as the concentration of introduced effective donors increases, the resistivity of the SiC crystal decreases.

[0057] Fig.12 Shows the change in Fermi level of SiC crystals with different resistivities before and after vanadium doping. Fig.12 In the figure, the horizontal axis represents the resistivity of SiC crystal before vanadium doping, and the vertical axis represents the distance between the Fermi level and the top of the conduction band. Fig.12 It can be seen that after vanadium doping, the electron concentration in doped SiC decreases because the deep energy level vanadium captures the electrons in the doped SiC as an acceptor energy level, so the distance between the Fermi level and the top of the conduction band increases. When the resistivity of the SiC crystal obtained in the corresponding growth process is in the range of 1e1-1e13Ω∙cm, the Fermi level of the doped SiC after vanadium doping is below the vanadium level, and vanadium can act as an effective deep energy level trap.

[0058] Fig.13 The variation of carrier concentration with depth near the interface of high-purity SiC and vanadium-doped SiC under the influence of PSC is shown. Fig.13 In the figure, the horizontal axis represents the distance from the bottom of the silicon dioxide, and the vertical axis represents the concentration of carriers. The effective donor concentration of the high-purity SiC used is 1e4 / cm 3 , the resistivity is 1e12Ω∙cm; when the effective donor concentration is 1e15 / cm 3 During the growth of SiC crystal, 5e17 / cm 3 After adding vanadium, its resistivity is 1e12Ω∙cm; Fig.13 It shows that when using high-purity SiC and vanadium-doped SiC with the same resistivity, under the influence of PSC, the carrier concentration of vanadium-doped SiC near the SiO2 interface is greatly reduced, which improves the inhibition effect of PSC effect. In order to achieve the same inhibition effect, the growth process requirements for doped silicon carbide are lower.

[0059] Fig.14 The variation of carrier concentration with depth near the interface of SiC+poly-Si structure under the influence of PSC is shown. Fig.14 In the figure, the horizontal axis represents the distance from the bottom of silicon dioxide, and the vertical axis represents the concentration of carriers. Fig.14 It shows that although the carrier concentration is at an extremely low level below poly-Si, a high number of free carriers are enriched in poly-Si.

[0060] Fig.15 The change of effective resistivity with frequency under the influence of PSC was compared between high-purity SiC, SiC+poly-Si, and vanadium-doped SiC. The resistivity of high-purity SiC, SiC in SiC+poly-Si, and vanadium-doped SiC are all 1e12Ω∙cm. Fig.15 In the figure, the horizontal axis represents the frequency, and the vertical axis represents the effective resistivity which is a measure of the RF loss of the substrate. Fig.15 It shows that due to the influence of PSC, the effective resistivity of the high-purity SiC structure is only about 200Ω∙cm when the frequency is above 0.5GHz; using the SiC+poly-Si structure, the effective resistivity in the frequency band above 0.5GHz can be increased to about 10kΩ∙cm; using vanadium-doped SiC, the effective resistivity can be increased to more than 200kΩ∙cm.

[0061] Fig.16 It shows that for SiC growth processes with different resistivities, PSC is suppressed by vanadium doping and poly-Si addition, respectively, and its effective resistivity changes with the resistivity of the SiC crystal obtained in the corresponding growth process. Fig.16 In the figure, the horizontal axis represents the resistivity of the SiC crystal obtained in the corresponding growth process, and the vertical axis represents the effective resistivity that measures the RF loss of the substrate. The effective resistivity of the vanadium-doped method is higher than that of the poly-Si method, and reaches its peak value at a smaller resistivity of the SiC crystal obtained in the corresponding growth process.

[0062] Fig.17 It shows that for SiC growth processes with different resistivities, PSC is suppressed by vanadium doping and poly-Si addition, and the Bode Q peak value changes with the resistivity of the SiC crystal obtained in the corresponding growth process. Fig.17In the figure, the horizontal axis represents the resistivity of the SiC crystal obtained in the corresponding growth process, and the vertical axis represents the Bode Q peak of the SAW resonator. The Bode Q peak of the SAW device using the vanadium doping method is higher than that of the poly-Si method, and its peak value is reached at a smaller resistivity of the SiC crystal obtained in the corresponding growth process.

[0063] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present invention.

Claims

1. A method for preparing a surface acoustic wave device, characterized in that: include: doping deep energy level impurities during the growth process of single crystal silicon or silicon carbide to obtain doped silicon or doped silicon carbide doped with deep energy level impurities, and using the doped silicon or doped silicon carbide to prepare a supporting substrate; Preparing silicon dioxide on a supporting substrate to form a temperature compensation layer; A piezoelectric single crystal film is prepared on the temperature compensation layer to form a piezoelectric layer, and interdigital electrodes are deposited on the piezoelectric layer; The method of doping deep energy level impurities during the growth process of single crystal silicon to obtain doped silicon doped with deep energy level impurities comprises: During the growth of single crystal silicon with a resistivity of 10 kΩ·cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon is greater than or equal to 3e16 / cm 3 deep energy level impurities are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.34eV to 0.56eV below the top of the conduction band of the doped silicon; wherein the single crystal silicon is n-type single crystal silicon, and the donor ionization concentration of the n-type single crystal silicon is 4.6e11 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.44 eV below the conduction band; or, During the growth of single crystal silicon with a resistivity of 5 kΩ·cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon is greater than or equal to 5e16 / cm 3 deep energy level impurities are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.35eV-0.56eV below the top of the conduction band of the doped silicon; wherein the single crystal silicon is n-type single crystal silicon, and the donor ionization concentration of the n-type single crystal silicon is 9.2e11 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.42 eV below the conduction band; or, During the growth of single crystal silicon with a resistivity of 2 kΩ·cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon is greater than or equal to 8e16 / cm 3 deep energy level impurities are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.37eV-0.56eV below the top of the conduction band of the doped silicon; wherein the single crystal silicon is n-type single crystal silicon, and the donor ionization concentration of the n-type single crystal silicon is 2.3e12 / cm 3 , the Fermi level of the n-type single crystal silicon is located 0.39 eV below the conduction band.

2. The method for preparing a surface acoustic wave device according to claim 1, characterized in that: Doping deep energy level impurities during the growth process of the silicon carbide to obtain doped silicon carbide doped with deep energy level impurities specifically includes: During the growth of silicon carbide, the concentration of doped elements is 5e14 / cm 3 ~1e18 / cm 3 The vanadium element within the range makes the effective donor concentration of doped silicon carbide less than 1e6 / cm 3 , and the energy level of vanadium is above the Fermi level in the band gap of silicon carbide.

3. A surface acoustic wave device, characterized in that: include: Support substrate, temperature compensation layer, piezoelectric layer and interdigital electrodes; The temperature compensation layer is located on the supporting substrate, the piezoelectric layer is located on the temperature compensation layer, and the interdigital electrodes are deposited on the piezoelectric layer; The support substrate is doped silicon or doped silicon carbide doped with deep energy level impurities, and the doped silicon or doped silicon carbide is obtained by doping deep energy level impurities during the growth process of single crystal silicon or silicon carbide; The temperature compensation layer is silicon dioxide, and the piezoelectric layer is a piezoelectric single crystal film; The doped silicon is a silicon having a doping element concentration greater than or equal to 3e16 / cm at the Fermi level in the band gap of the single crystal silicon during the growth process of the single crystal silicon with a resistivity of 10 kΩ·cm. 3 deep energy level impurities are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.34eV to 0.56eV below the top of the conduction band of the doped silicon; wherein the single crystal silicon is n-type single crystal silicon, and the donor ionization concentration of the n-type single crystal silicon is 4.6e11 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.44 eV below the conduction band; or, During the growth of single crystal silicon with a resistivity of 5 kΩ·cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon is greater than or equal to 5e16 / cm 3 deep energy level impurities are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.35eV-0.56eV below the top of the conduction band of the doped silicon; wherein the single crystal silicon is n-type single crystal silicon, and the donor ionization concentration of the n-type single crystal silicon is 9.2e11 / cm 3 , the Fermi level of the n-type single crystal silicon is 0.42 eV below the conduction band; or, During the growth of single crystal silicon with a resistivity of 2 kΩ·cm, the concentration of doping elements at the Fermi level in the band gap of the single crystal silicon is greater than or equal to 8e16 / cm 3 deep energy level impurities are added to obtain doped silicon doped with deep energy level impurities, so that the energy level of the deep energy level impurities is located 0.37eV-0.56eV below the top of the conduction band of the doped silicon; wherein the single crystal silicon is n-type single crystal silicon, and the donor ionization concentration of the n-type single crystal silicon is 2.3e12 / cm 3 , the Fermi level of the n-type single crystal silicon is located 0.39 eV below the conduction band.

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