Device testing apparatus and method

Abstract

The present application provides a device testing device and method, which relates to the field of device testing technology, wherein the device includes: a main controller, a driving module, wherein the main controller is used to receive a test vector file sent by a host computer to test the device under test; the main controller is connected to a test board through the driving module, the main controller is used to select a target driving unit to communicate with the device under test, and the main controller is also used to perform a backcheck on the device under test according to an output response signal of the device under test, the target driving unit is a driving circuit matched with the device under test, and the driving module includes a plurality of driving circuits supporting different serial port communication modes; wherein the device under test includes at least one of the following: a UART serial port device, an SPI serial port device, an IIC serial port device, a CAN serial port device, and an SWD serial port device. The implementation of the technical solution provided by the present application significantly improves the versatility and flexibility of the test device.

Description

Technical Field

[0001] The present application relates to the field of device testing technology, and in particular to a device testing apparatus and method. Background Art

[0002] With the development of new energy vehicles and aerospace technology, higher requirements are placed on the stability and reliability of automotive-grade or military-grade components and integrated circuits. Device testing can screen out unqualified products. For the testing of serial communication interface devices (such as UART, IIC, SPI, CAN, SWD, etc.), different test devices need to be provided for devices of different serial port types. Some devices cannot even determine the operating results. For example, the existing solution mainly generates 0 and 1 signals based on graphic files and applies them to the device under test. The output of the device can be viewed through an oscilloscope, but the device output cannot be effectively detected. For asynchronous communication methods such as UART and CAN communication, the excitation signal does not have a synchronized clock, and it is impossible to accurately determine when the device will reply, so it is impossible to effectively compare the device output and determine the operating results. It can be seen that the test device in the relevant technology has poor compatibility and cannot effectively test various types of serial port devices. Summary of the invention

[0003] In order to solve the above technical problems, the present application provides a device testing apparatus and method.

[0004] In the first aspect, the present application provides a device testing device, including: a main controller, a drive module, wherein the main controller is communicatively connected to a host computer, and the main controller is used to receive a test vector file sent by the host computer, wherein the test vector file is used to instruct to test the device under test; the main controller is connected to a test board through the drive module, and the main controller is used to select a target drive unit to communicate with the device under test, and the main controller is also used to perform backcheck on the device under test according to an output response signal of the device under test, wherein the device under test is located on the test board, the target drive unit is a drive circuit matching the device under test, the drive module includes the target drive unit, and the drive module includes multiple drive circuits supporting different serial port communication modes; wherein the device under test includes at least one of the following: a UART serial port device, an SPI serial port device, an IIC serial port device, a CAN serial port device, and a SWD serial port device.

[0005] By adopting the above technical scheme, the device test device can be connected to the host computer through the main controller, receive the test vector file sent by the host computer, and instruct to test the device to be tested, and the device to be tested can be a device of any serial communication mode. The main controller selects the target drive unit corresponding to the device to be tested from the drive module, and communicates with the device to be tested on the test board through the target drive unit. The device test device can dynamically test UART serial port devices, SPI serial port devices, IIC serial port devices, CAN serial port devices and SWD serial port devices, that is, the device test device can be applied to various types of serial port devices, improve the versatility of the device test device, and judge the state of the device by checking its output response signal, so as to achieve the purpose of effectively testing the device to be tested, and improve the accuracy and efficiency of the device test. The device test device of the technical scheme integrates a variety of drive circuits, automatically selects the target drive unit matching the device to be tested, and automatically judges the test results, which effectively solves the technical problems such as poor compatibility of multi-type serial port device testing, great difficulty in testing asynchronous communication devices, inaccurate test result judgment, and low test automation, improves the test efficiency and accuracy, and significantly improves the versatility and flexibility of the test equipment.

[0006] Optionally, the driving module includes a first group of multi-way switches and a group of driving units, wherein each multi-way switch in the first group of multi-way switches corresponds to a level conversion unit in a group of level conversion units, and the main controller is electrically connected to the test board through each multi-way switch and a corresponding level conversion unit. Each multi-way switch in the first group of multi-way switches is used to transmit a test signal between the main controller and the device under test, and the level conversion unit is used to perform level conversion processing on the test signal, wherein the test signal includes an excitation test signal or an output response signal for the device under test.

[0007] By adopting the above technical solution, the first group of multi-way switches cooperates with a group of level conversion units, so that the main controller can be electrically connected to the device under test on the test board through the multi-way switches and the corresponding level conversion units, and realize effective excitation testing of the device under test and output response signal feedback, thereby realizing effective testing of different serial communication interface devices. Through the level conversion unit, it is ensured that the signal generated by the main controller can adapt to the device under test with different level requirements, and accurate transmission and reception of signals are achieved. The introduction of the multi-way switch allows the main controller to flexibly select the signal path according to the test requirements, support a variety of test scenarios and devices under test, and improve the flexibility and adaptability of the test system. Traditional test devices may need to be equipped with a special test interface board for each device under test, which increases the complexity and cost of the device. The device testing device of this technical solution can achieve the purpose of reducing the complexity and cost of the device.

[0008] Optionally, the first group of multi-way switches includes a first 8-channel switch, a second 8-channel switch, a third 8-channel switch and a fourth 8-channel switch, a group of driving units includes a first level conversion unit, a second level conversion unit, a third level conversion unit and a fourth level conversion unit, and the target driving unit includes at least one of the following: when the device under test is an SPI serial port device, the target driving unit includes: a first 8-channel switch, a second 8-channel switch, a third 8-channel switch, a fourth 8-channel switch, a first level conversion unit, a second level conversion unit, a third level conversion unit and a fourth level conversion unit, wherein the common input and output terminals of the first 8-channel switch are electrically connected to the first pin of the main controller, and the multi-way input and output terminals of the first 8-channel switch are electrically connected to the first pin of the main controller. The common input and output terminals of the second 8-channel switch are electrically connected to the second pin of the main controller, and the multiple input and output terminals of the second 8-channel switch are electrically connected to the test board through the second level conversion unit; the common input and output terminals of the third 8-channel switch are electrically connected to the third pin of the main controller, and the multiple input and output terminals of the third 8-channel switch are electrically connected to the test board through the third level conversion unit; the common input and output terminals of the fourth 8-channel switch are electrically connected to the fourth pin of the main controller, and the multiple input and output terminals of the fourth 8-channel switch are electrically connected to the test board through the fourth level conversion unit, the first pin of the main controller is used to output the SPI_CS signal, and the second pin of the main controller is used to output the SPI _CLK signal, the third pin of the main controller is used to receive the SPI_MISO signal, the fourth pin of the main controller is used to output the SPI_MOSI signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test through the target drive unit in a time-sharing manner; when the device under test is an IIC serial port device, the target drive unit includes: a first 8-channel switch and a second 8-channel switch, wherein the common input and output ends of the first 8-channel switch are electrically connected to the first pin of the main controller, the common input and output ends of the second 8-channel switch are electrically connected to the second pin of the main controller, the first pin of the main controller is used to transmit the IIC_SDA signal, and the second pin of the main controller is used to output the IIC_C LK signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit; in the case where the device under test is a SWD serial port device, the target drive unit includes: a first 8-channel switch and a second 8-channel switch, wherein the common input and output end of the first 8-channel switch is electrically connected to the first pin of the main controller, and the common input and output end of the second 8-channel switch is electrically connected to the second pin of the main controller, the first pin of the main controller is used to transmit the SWD_IO signal, and the second pin of the main controller is used to output the SWD_CLK signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit;In the case where the device under test is a UART serial port device, the target drive unit includes: a third 8-channel switch and a fourth 8-channel switch, wherein the common input and output end of the third 8-channel switch is electrically connected to the third pin of the main controller, the common input and output end of the fourth 8-channel switch is electrically connected to the fourth pin of the main controller, the third pin of the main controller is used to receive a UART_RX signal, and the fourth pin of the main controller is used to output a UART_TX signal. The test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit. ;

[0009] By adopting the above technical solution, the device test device can realize efficient testing of the device under test in different serial communication modes through the first group of multi-way switches and a group of level conversion units. In the case of SPI serial port devices, four 8-channel switches and four level conversion units are used in conjunction to realize time-sharing polling test of 8 devices under test, thereby improving test efficiency and accuracy. In the case of IIC serial port devices, two 8-channel switches (such as the first 8-channel switch and the second 8-channel switch) enable the main controller to transmit IIC_SDA and IIC_CLK signals respectively, thereby completing the time-sharing polling test of 8 devices under test. In the case of SWD serial port devices, two 8-channel switches (such as the first 8-channel switch and the second 8-channel switch) are also used to realize the transmission of SWD_IO and SWD_CLK signals, completing the time-sharing polling test of 8 devices under test. In the case of UART serial port devices, the third 8-channel switch and the fourth 8-channel switch are used for the transmission of UART_RX and UART_TX signals respectively, ensuring efficient time-sharing polling test of 8 devices under test. That is, for different types of serial port devices, the first group of multi-way switches and a group of level conversion units in the device test device of the present technical solution can be shared, thereby reducing the design cost of the device. The time-sharing polling mechanism enables the main controller to efficiently test multiple devices under test on the test board one by one, thereby improving the test efficiency; by reusing the pin resources of the main controller, additional hardware requirements are reduced, thereby reducing the overall cost of the system.

[0010] Optionally, the driving module also includes a second group of multi-way switches and a CAN PHY chip, wherein the main controller is connected to the second group of multi-way switches through the CAN PHY chip, the CAN PHY chip is used to convert the single-ended driving signal into a differential signal, and each multi-way switch in the second group of multi-way switches is connected to the test board.

[0011] By adopting the above technical solution, the main controller converts the single-ended drive signal into a differential signal through the CAN PHY chip, and connects it to the test board through the second set of multiplexers, thereby achieving the purpose of effectively testing the CAN serial port device. The use of the CAN PHY chip enables the test device to support the testing of differential bus communication interface devices, improving the scope of application and accuracy of the test. Each multiplexer transmits the test signal between the main controller and the device under test, ensuring the accuracy and reliability of the signal.

[0012] Optionally, the second group of multi-way switches includes a fifth 8-channel switch and a sixth 8-channel switch, wherein, when the device under test is a CAN serial port device, the target drive unit includes: a fifth 8-channel switch and a sixth 8-channel switch, wherein the data receiving pin of the CAN PHY chip is electrically connected to the fifth pin of the main controller, the data sending pin of the CAN PHY chip is electrically connected to the sixth pin of the main controller, the high signal pin of the CAN PHY chip is electrically connected to the common input and output end of the fifth 8-channel switch, the low signal pin of the CAN PHY chip is electrically connected to the common input and output end of the sixth 8-channel switch, the fifth pin of the main controller is used to output an excitation test signal, the sixth pin of the main controller is used to receive an output response signal of the CAN serial port device, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in a time-sharing manner through the target drive unit.

[0013] By adopting the above technical solution, the test device can realize effective testing of CAN serial port devices. Specifically, the main controller is connected to the fifth 8-channel switch and the sixth 8-channel switch in the second group of multiplexers through the CAN PHY chip, so that the excitation test signal can be converted into a differential signal and transmitted to the device under test through the fifth 8-channel switch and the sixth 8-channel switch. This method enables the test device to accurately control the excitation test signal of the CAN serial port device, and to perform a backcheck on the device by receiving the output response signal, thereby accurately judging the state of the device. The setting of the fifth 8-channel switch and the sixth 8-channel switch enables the device to poll the 8 devices under test on the test board in a time-sharing manner, thereby improving the test efficiency.

[0014] Optionally, the main controller is further used to generate a communication timing signal based on the test vector file, and communicate with the device under test based on the communication timing signal, wherein the communication timing signal serves as an excitation test signal for the device under test.

[0015] By adopting the above-mentioned technical scheme, the main controller can generate a communication timing signal based on the test vector file, and communicate with the device under test based on the communication timing signal, wherein the communication timing signal serves as an excitation test signal for the device under test, thereby realizing effective testing of various serial communication interface devices and improving the accuracy and efficiency of the test.

[0016] Optionally, the driving module further includes a gold finger, which is arranged on a side of the driving module close to the test board, and the driving module is connected to the test board via the gold finger.

[0017] By adopting the above technical solution, the gold finger is set on the side of the driving module close to the test board, and the driving module is connected to the test board through the gold finger, thereby achieving a stable electrical connection between the device under test and the driving module, thereby improving the reliability and accuracy of the test.

[0018] Optionally, the gold finger includes M groups of contact points, K contact points in each group of contact points are electrically connected to K test pins of the device under test, and K contact points in each group of contact points are electrically connected to a level conversion unit of the target drive unit, wherein M is a positive integer greater than or equal to 1, and K is a positive integer greater than or equal to 2.

[0019] By adopting the above technical solution, the design of the gold finger can realize the compatibility test of various serial communication interface devices. Specifically, the K contact points in each group of contact points can be electrically connected to the K test pins of the device under test, thereby ensuring the accuracy of signal transmission of different test pins and improving the reliability of the test. At the same time, each group of contact points is electrically connected to a level conversion unit of the target drive unit, so that the signal can be accurately converted between different level standards, ensuring the consistency and effectiveness of communication between different devices.

[0020] In a second aspect of the present application, a device testing method is also provided, which is applied to any of the device testing devices mentioned above, and includes: a main controller receives a communication mode setting instruction sent by a host computer; the main controller controls the power-on of a target drive unit based on the communication mode setting instruction, wherein the communication mode setting instruction is used to instruct the main controller to select a drive unit that matches the communication mode of the device to be tested, and the device to be tested is located on a test board; the main controller generates a communication timing signal based on the test vector file when receiving a test vector file sent by the host computer, wherein the test vector file is used to instruct the device to be tested to be tested; the main controller sends a target communication signal to the device to be tested through the target drive unit, wherein the target communication signal is obtained by the target drive unit processing the communication timing signal, and the target communication signal matches the device to be tested; the main controller receives an output response signal returned by the device to be tested, and performs a backcheck on the device to be tested based on the output response signal to obtain a test result.

[0021] By adopting the above technical solution, the device testing method can enable the main controller to receive the communication mode setting instruction of the host computer and control the target drive unit to power on, select the matching drive unit according to the device to be tested, and ensure that the main controller can send the target communication signal matching the device to be tested through the target drive unit. This method realizes the effective test of the device to be tested under different serial port communication modes by generating a communication timing signal and performing a backcheck according to the output response signal, thereby ensuring the accuracy of the test result. The main controller receives the communication mode setting instruction sent by the host computer, and selects the drive unit matching the communication mode of the device to be tested to power on according to the instruction. This method ensures that the test device can be compatible with the devices to be tested in different communication modes, thereby improving the versatility and flexibility of the test. The device to be tested can be any of the following: UART serial port device, SPI serial port device, IIC serial port device, CAN serial port device and SWD serial port device, that is, the device testing device and the device testing method are applicable to various serial port devices, thereby improving the applicability of the device testing device and the testing method. It effectively solves technical problems such as poor compatibility of testing multiple types of serial port devices, difficulty in testing asynchronous communication devices, inaccurate test result judgment, and low degree of test automation, improves test efficiency and accuracy, and significantly improves the versatility and flexibility of test equipment.

[0022] Optionally, the above method also includes: uploading the test results to a host computer for display by the host computer.

[0023] By adopting the above technical solution, the test results are uploaded to the host computer for display by the host computer, thereby realizing visualization of the test results, making it easier for users to intuitively monitor and analyze the status or quality of the device under test.

[0024] In a third aspect of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the program, any of the above method steps is implemented.

[0025] In a fourth aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the instructions are executed, any of the above method steps is performed.

[0026] In summary, one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0027] 1. The device test device of this technical solution integrates multiple drive circuits, automatically selects the target drive unit that matches the device to be tested, and automatically determines the test results, which effectively solves the technical problems such as poor compatibility of multi-type serial port device testing, great difficulty in testing asynchronous communication devices, inaccurate test result judgment, and low test automation, thereby improving test efficiency and accuracy and significantly improving the versatility and flexibility of the test equipment;

[0028] 2. Through the level conversion unit, it is ensured that the signal generated by the main controller can adapt to the devices under test with different level requirements, realize accurate transmission and reception of signals, support a variety of test scenarios and devices under test, improve the adaptability of the test system, and can also achieve the purpose of reducing the complexity and cost of the device;

[0029] 3. Through the time-sharing polling mechanism, the main controller can efficiently test multiple devices under test on the test board one by one, thereby improving the test efficiency. By reusing the pin resources of the main controller, additional hardware requirements are reduced, thereby reducing the overall cost of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is an overall framework diagram of a device testing device provided in an embodiment of the present application;

[0031] Figure 2 It is a structural frame of a driving module provided in an embodiment of the present application. Figure 1 ;

[0032] Figure 3 It is a structural frame of a driving module provided in an embodiment of the present application. Figure 2 ;

[0033] Figure 4 is a flow chart of a device testing method provided in an embodiment of the present application;

[0034] Figure 5 This is an overall flow chart of a serial port device test provided by an embodiment of the present application;

[0035] Figure 6 is a block diagram of a device testing system provided in an embodiment of the present application;

[0036] Figure 7 It is a schematic diagram of a device test in CAN mode provided in an embodiment of the present application;

[0037] Figure 8 It is a schematic diagram of device testing in other modes provided in the embodiments of the present application. DETAILED DESCRIPTION

[0038] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0039] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0040] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0041] The present application provides a device testing apparatus, referring to Figure 1 , Figure 1 : is an overall framework diagram of a device testing device provided in an embodiment of the present application, the device comprises: a main controller, a driving module, wherein:

[0042] The main controller is connected to the host computer for communication, and the main controller is used to receive the test vector file sent by the host computer, wherein the test vector file is used to instruct to test the device under test;

[0043] The main controller is connected to the test board through the drive module. The main controller is used to select a target drive unit to communicate with the device under test. The main controller is also used to perform a backcheck on the device under test according to an output response signal of the device under test. The device under test is located on the test board. The target drive unit is a drive circuit that matches the device under test. The drive module includes the target drive unit. The drive module includes multiple drive circuits that support different serial port communication modes.

[0044] The device under test includes at least one of the following: a UART serial port device, an SPI serial port device, an IIC serial port device, a CAN serial port device, and a SWD serial port device.

[0045] In the above embodiment, the device test device can be connected to the host computer through the main controller, receive the test vector file sent by the host computer, and instruct to test the device to be tested. The device to be tested can be a device of any serial communication mode. The main controller selects the target drive unit corresponding to the device to be tested from the drive module, and communicates with the device to be tested on the test board through the target drive unit. The device test device can dynamically test UART serial port devices, SPI serial port devices, IIC serial port devices (or I2C serial port devices), CAN serial port devices and SWD serial port devices, that is, the device test device can be applied to various types of serial port devices, improve the versatility of the device test device, and judge the state of the device by checking its output response signal, so as to achieve the purpose of effectively testing the device to be tested and improve the accuracy and efficiency of device testing. The device test device in this embodiment integrates multiple drive circuits, automatically selects the target drive unit that matches the device to be tested, and automatically judges the test results, which effectively solves the technical problems such as poor compatibility of multiple types of serial port devices, great difficulty in testing asynchronous communication devices, inaccurate test result judgment, and low test automation, improves test efficiency and accuracy, and significantly improves the versatility and flexibility of the test equipment. The test schemes in the related art are usually designed for specific types of serial port devices, lacking extensive support for different types of serial port devices (such as UART, SPI, IIC, CAN, SWD, etc.), which results in the need for frequent replacement or adjustment of test equipment to adapt to different types of devices, increasing the cost and complexity of testing. Existing test schemes often rely on manual observation of oscilloscopes and other methods to judge test results. This method is not only inefficient, but also easily affected by human factors, resulting in inaccurate test results. The device can achieve compatible testing of multiple types of serial port devices such as UART, SPI, IIC, CAN, SWD, etc. by integrating multiple drive circuits that support different serial port communication modes, significantly improving the versatility and flexibility of the test equipment. The device can accurately capture and compare the response output of the device through real-time communication between the main controller and the device under test. It is particularly suitable for testing asynchronous communication interface devices such as UART and CAN, which improves the accuracy and reliability of the test. The test device automatically analyzes and judges the test results through the main controller, reducing manual intervention, improving test efficiency and accuracy, and reducing the impact of human factors on the test results. The entire test process is controlled by the host computer. By sending test vector files and receiving feedback from the main controller, the test process is automatically controlled, which significantly shortens the test cycle, improves test efficiency, and meets the needs of large-scale production testing.

[0046] It should be noted that the device test in the present application is not limited to a specific test type, and may be a conventional performance test, or an unconventional test, or an aging test, or other tests.

[0047] In an optional embodiment, the driving module includes a first group of multi-way switches and a group of driving units, wherein each multi-way switch in the first group of multi-way switches corresponds to a level conversion unit in a group of level conversion units, and the main controller is electrically connected to the test board through each multi-way switch and a corresponding level conversion unit. Each multi-way switch in the first group of multi-way switches is used to transmit a test signal between the main controller and the device under test, and the level conversion unit is used to perform level conversion processing on the test signal, wherein the test signal includes an excitation test signal or an output response signal for the device under test.

[0048] In the above embodiment, the first group of multi-way switches cooperates with a group of level conversion units, so that the main controller can be electrically connected to the device under test on the test board through the multi-way switches and the corresponding level conversion units, and realize effective excitation testing of the device under test and output response signal return detection, thereby realizing effective testing of different serial communication interface devices. Through the level conversion unit, it is ensured that the signal generated by the main controller can adapt to the device under test with different level requirements, and the accurate transmission and reception of the signal is realized. The introduction of the multi-way switch enables the main controller to flexibly select the signal path according to the test requirements, support a variety of test scenarios and devices under test, and improve the flexibility and adaptability of the test system. In device testing, different devices under test (DUT, Device Under Test) may require different levels of excitation test signals or output response signals. The signal level generated by the main controller may not match the interface level of the device under test, resulting in the signal cannot be correctly transmitted or received. By introducing the level conversion unit, this compatibility problem is solved. Traditional test devices can only target specific types of serial port devices and can only use fixed signal paths, which limits the flexibility and efficiency of the test. By using a multi-way switch, the main controller is allowed to dynamically select the signal path according to the test requirements, thereby improving the flexibility and efficiency of the test. Traditional test devices may need to be equipped with a dedicated test interface board for each device to be tested, which increases the complexity and cost of the device. The device test device in this embodiment can achieve the purpose of reducing the complexity and cost of the device. Through modular design, including configurable multi-way switches and level conversion units, this embodiment provides a more universal and economical solution.

[0049] In an optional embodiment, the driving module includes a first group of multi-way switches and a group of driving units, specifically, Figure 2As shown, the first group of multi-way switches includes a first 8-channel switch, a second 8-channel switch, a third 8-channel switch and a fourth 8-channel switch, a group of driving units includes a first level conversion unit, a second level conversion unit, a third level conversion unit and a fourth level conversion unit, and the target driving unit includes at least one of the following: when the device under test is an SPI serial port device, the target driving unit includes: a first 8-channel switch, a second 8-channel switch, a third 8-channel switch, a fourth 8-channel switch, a first level conversion unit, a second level conversion unit, a third level conversion unit and a fourth level conversion unit, wherein the common input and output terminals of the first 8-channel switch are electrically connected to the first pin of the main controller, and the multi-way input and output terminals of the first 8-channel switch are electrically connected to the first pin of the main controller. The common input and output terminals of the second 8-channel switch are electrically connected to the second pin of the main controller, and the multiple input and output terminals of the second 8-channel switch are electrically connected to the test board through the second level conversion unit; the common input and output terminals of the third 8-channel switch are electrically connected to the third pin of the main controller, and the multiple input and output terminals of the third 8-channel switch are electrically connected to the test board through the third level conversion unit; the common input and output terminals of the fourth 8-channel switch are electrically connected to the fourth pin of the main controller, and the multiple input and output terminals of the fourth 8-channel switch are electrically connected to the test board through the fourth level conversion unit, the first pin of the main controller is used to output the SPI_CS signal, and the second pin of the main controller is used to output the SPI _CLK signal, the third pin of the main controller is used to receive the SPI_MISO signal, the fourth pin of the main controller is used to output the SPI_MOSI signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test through the target drive unit in a time-sharing manner; when the device under test is an IIC serial port device, the target drive unit includes: a first 8-channel switch and a second 8-channel switch, wherein the common input and output ends of the first 8-channel switch are electrically connected to the first pin of the main controller, the common input and output ends of the second 8-channel switch are electrically connected to the second pin of the main controller, the first pin of the main controller is used to transmit the IIC_SDA signal, and the second pin of the main controller is used to output the IIC_C LK signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit; in the case where the device under test is a SWD serial port device, the target drive unit includes: a first 8-channel switch and a second 8-channel switch, wherein the common input and output end of the first 8-channel switch is electrically connected to the first pin of the main controller, and the common input and output end of the second 8-channel switch is electrically connected to the second pin of the main controller, the first pin of the main controller is used to transmit the SWD_IO signal, and the second pin of the main controller is used to output the SWD_CLK signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit;In the case where the device under test is a UART serial port device, the target drive unit includes: a third 8-channel switch and a fourth 8-channel switch, wherein the common input and output end of the third 8-channel switch is electrically connected to the third pin of the main controller, the common input and output end of the fourth 8-channel switch is electrically connected to the fourth pin of the main controller, the third pin of the main controller is used to receive a UART_RX signal, and the fourth pin of the main controller is used to output a UART_TX signal. The test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit. ;

[0050] In the above embodiment, the device testing device can realize efficient testing of the device under test in different serial communication modes through the first group of multi-way switches and a group of level conversion units. In the case of SPI serial port devices, four 8-channel switches and four level conversion units are used in combination to realize time-sharing polling test of 8 devices under test, thereby improving test efficiency and accuracy. In the case of IIC serial port devices, two 8-channel switches (such as the first 8-channel switch and the second 8-channel switch) enable the main controller to transmit IIC_SDA and IIC_CLK signals respectively, thereby completing the time-sharing polling test of 8 devices under test. In the case of SWD serial port devices, two 8-channel switches (such as the first 8-channel switch and the second 8-channel switch) are also used to realize the transmission of SWD_IO and SWD_CLK signals, completing the time-sharing polling test of 8 devices under test. In the case of UART serial port devices, the third 8-channel switch and the fourth 8-channel switch are used for the transmission of UART_RX and UART_TX signals respectively, ensuring efficient time-sharing polling test of 8 devices under test. That is, for different types of serial port devices, the first group of multiplexers and a group of level conversion units in the device test device of this embodiment can achieve the purpose of sharing, thereby achieving the effect of reducing the design cost of the device. The time-sharing polling mechanism enables the main controller to efficiently test multiple devices under test on the test board one by one, thereby improving the test efficiency; by reusing the pin resources of the main controller, additional hardware requirements are reduced, and the overall cost of the system is reduced. The device test device (or test system) needs to support multiple different types of serial port devices, each of which has its own specific signal transmission protocol and pin configuration. By flexibly configuring the first group of multiplexers and a group of level conversion units, the compatibility problem of multiple types of serial port devices in the test device is solved. When there are multiple devices under test on the test board, how to efficiently test each device under test one by one is a key issue. By means of time-sharing polling, limited main controller pin resources are used to achieve effective testing of multiple devices under test. The embodiment of the present application allows the test device to flexibly configure the drive unit according to the type and number of devices under test through modular design, thereby improving the flexibility and scalability of the test device.

[0051] It should be noted that, in this embodiment, only an 8-channel switch is used as an example for explanation. In practical applications, a 16-channel switch (or a switch with other number of channels) may also be selected. In addition, an 8-channel switch may also be called an 8-channel multi-way switch, or a single-ended 8-channel multi-way switch, such as CD4051, or a multi-way check switch, etc., that is, the multi-way switch may also be called a multi-way check switch. Each of the above 8-channel switches is used to transmit a signal, and each 8-channel switch has a total of 8 channels, so 8 devices under test can be polled and tested; optionally, in practical applications, more 8-channel switches may be cascaded, for example, 5, so that 40 devices under test can be polled and tested. Of course, the corresponding level conversion unit also needs to be increased, and it can be flexibly expanded according to similar concepts, which will not be repeated here.

[0052] In an optional embodiment, the driving module also includes a second group of multi-way switches and a CAN PHY chip, wherein the main controller is connected to the second group of multi-way switches through the CAN PHY chip, the CAN PHY chip is used to convert the single-ended driving signal into a differential signal, and each multi-way switch in the second group of multi-way switches is connected to the test board.

[0053] In the above embodiment, the main controller converts the single-ended drive signal into a differential signal through the CAN PHY chip, and connects it to the test board through the second group of multiplexers, thereby achieving the purpose of effectively testing the CAN serial port device. The use of the CAN PHY chip enables the test device to support the test of differential bus communication interface devices, thereby improving the scope of application and accuracy of the test. Each multiplexer transmits the test signal between the main controller and the device to be tested, thereby ensuring the accuracy and reliability of the signal. By introducing the CAN PHY chip, the single-ended drive signal issued by the main controller is converted into a differential signal for transmission, so that the device test device can be applied to the CAN serial port device. Due to its inherent anti-interference ability and stronger signal integrity, the differential signal can maintain the stability and accuracy of the signal over a longer distance, thereby improving the reliability and performance of the overall test device. By utilizing the design of the second group of multiplexers, flexible switching and control of multiple test points can be achieved, which not only simplifies the hardware structure of the test device, but also improves the adaptability of the test device to different test scenarios or requirements, making the test device more flexible and efficient. Through modular design, the test device can be easily expanded or maintained when necessary. For example, when additional test points need to be added, only the corresponding multi-way switches and connecting lines need to be added without large-scale modification or replacement of the entire test device.

[0054] In an optional embodiment, if Figure 3As shown, the second group of multi-way switches includes a fifth 8-channel switch and a sixth 8-channel switch, wherein, in the case where the device under test is a CAN serial port device, the target drive unit includes: a fifth 8-channel switch and a sixth 8-channel switch, wherein the data receiving pin of the CAN PHY chip is electrically connected to the fifth pin of the main controller, the data sending pin of the CAN PHY chip is electrically connected to the sixth pin of the main controller, the high signal pin of the CAN PHY chip is electrically connected to the common input and output end of the fifth 8-channel switch, the low signal pin of the CAN PHY chip is electrically connected to the common input and output end of the sixth 8-channel switch, the fifth pin of the main controller is used to output an excitation test signal, the sixth pin of the main controller is used to receive an output response signal of the CAN serial port device, and the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit.

[0055] In the above embodiment, the test device can realize effective testing of CAN serial port devices. Specifically, the main controller is connected to the fifth 8-channel switch and the sixth 8-channel switch in the second group of multi-way switches through the CAN PHY chip, so that the excitation test signal can be converted into a differential signal and transmitted to the device under test through the fifth 8-channel switch and the sixth 8-channel switch. In this way, the test device can accurately control the excitation test signal of the CAN serial port device, and realize the return check of the device by receiving the output response signal, so as to accurately judge the state of the device. The setting of the fifth 8-channel switch and the sixth 8-channel switch enables the device to poll the 8 devices under test on the test board in time-sharing, thereby improving the test efficiency. By configuring the fifth 8-channel switch and the sixth 8-channel switch, the test device can simultaneously support the test of 8 CAN serial port devices. This multi-channel design significantly improves the test efficiency and shortens the test cycle, and is particularly suitable for the test requirements of large-scale production lines. The data receiving pin and data transmitting pin of the CANPHY chip are electrically connected to the corresponding pins of the main controller, ensuring the accurate transmission of the excitation test signal and the timely reception of the output response signal of the CAN serial port device; at the same time, the high signal pin and the low signal pin are respectively connected to the common input and output terminals of the two 8-channel switches, realizing the transmission of differential signals, further improving the integrity and reliability of the signal. The main controller polls the 8 devices under test in time-sharing through the target drive unit. This time-sharing test strategy not only makes full use of the resources of the main controller, but also avoids signal interference and conflict during the test process. In addition, the design also facilitates programmable control of the test process, realizes automated testing, and further improves the accuracy and efficiency of the test.

[0056] In an optional embodiment, the main controller is further used to generate a communication timing signal based on the test vector file, and communicate with the device under test based on the communication timing signal, wherein the communication timing signal serves as an excitation test signal for the device under test.

[0057] In the above embodiment, the main controller can generate a communication timing signal based on the test vector file, and communicate with the device under test based on the communication timing signal, wherein the communication timing signal is used as an excitation test signal for the device under test, thereby realizing effective testing of various serial communication interface devices and improving the accuracy and efficiency of the test. In a complex test environment, manually generating and sending test signals is not only inefficient, but also prone to errors. In the test and verification process, manual testing is often difficult to achieve consistency. By automatically generating communication timing signals based on the test vector file by the main controller and communicating with the device under test, the automation of the test is realized, which not only improves the test efficiency, but also reduces the possibility of human error. The test vector file usually contains detailed test conditions and expected results. The main controller accurately generates communication timing signals based on these files to ensure the accuracy and effectiveness of the test. At the same time, this method is also convenient for programming control of the test process to achieve more complex test scenarios. Since the test signal is automatically generated based on the test vector file, the test conditions are consistent and repeatable, which helps to analyze the repeatability and traceability of the test results and improve the reliability and credibility of the test. By introducing the function of automatically generating communication timing signals by the main controller, key issues such as automated testing, precise control of test signals, and repeatability and traceability of the test process are solved, thereby improving the degree of automation, accuracy, effectiveness and reliability of the test.

[0058] In an optional embodiment, the driving module further includes a gold finger, which is arranged on a side of the driving module close to the test board, and the driving module is connected to the test board via the gold finger.

[0059] In the above embodiment, the gold finger is arranged on one side of the driving module close to the test board, and the driving module is connected to the test board through the gold finger, so as to realize the stable electrical connection between the device to be tested and the driving module, and improve the reliability and accuracy of the test. In a high-frequency, high-speed or high-demand test environment, the connection between the driving module and the test board needs to have a high degree of stability and reliability to ensure the accurate transmission of the test signal and the smooth progress of the test; during the signal transmission process, the quality of the connection interface directly affects the integrity and quality of the signal, and the traditional connection method may cause signal distortion or loss due to problems such as poor contact and signal attenuation; as a professional connection element, the gold finger is designed to ensure close contact with the test board and reduce signal transmission problems caused by poor contact or looseness, which helps to improve the stability and reliability of the test and ensure the accuracy of the test results. Gold fingers usually have good electrical conductivity and signal transmission characteristics, which can reduce the attenuation and distortion of the signal during transmission and ensure the integrity and accuracy of the test signal. This is particularly important for high-frequency, high-speed or high-precision testing.

[0060] In an optional embodiment, the gold finger includes M groups of contact points, K contact points in each group of contact points are electrically connected to K test pins of the device under test, and K contact points in each group of contact points are electrically connected to a level conversion unit of the target drive unit, wherein M is a positive integer greater than or equal to 1, and K is a positive integer greater than or equal to 2.

[0061] In the above embodiment, the design of the gold finger can realize the compatibility test of various serial communication interface devices. Specifically, the K contact points in each group of contact points can be electrically connected to the K test pins of the device under test, thereby ensuring the accuracy of signal transmission of different test pins and improving the reliability of the test. At the same time, each group of contact points is electrically connected to a level conversion unit of the target drive unit, so that the signal can be accurately converted between different level standards, ensuring the consistency and effectiveness of communication between different devices. Through the design of M groups of contact points on the gold finger, the K contact points in each group of contact points are electrically connected to the K test pins of the device under test, which can effectively support the test requirements of multi-pin devices under test. This design enables the test system to easily cope with devices under test with multiple test pins, improving the flexibility and efficiency of the test. The K contact points in each group of contact points are electrically connected to a level conversion unit of the target drive unit, which means that each test pin can be independently converted. This design ensures the accuracy and reliability of the test signal during transmission, while simplifying the connection structure and improving the efficiency and stability of the test. Assume that M=8, K=4, that is, there are 8 groups of contact points on the gold finger, and each group of contact points may include 4 contact points (or pins), such as PIN1, PIN2, PIN3 and PIN4, because the test pins of the aforementioned serial port devices are at most 4, that is, SPI serial port devices, and other serial port devices (such as UART, IIC, CAN, SWD, etc.) only need 2 pins, so that different types of serial port devices can also share the contact points (or pins) on the gold finger when testing, for example: PIN1 can be used as SPI_CS / IIC_SDA / SWDIO, PIN2 can be used as SPI_CLK / IIC_SCL / SWCLK, PIN3 can be used as SPI_MISO / UART_RX / CAN_H, PIN2 can be used as SPI_MOSI / UART_TX / CAN_L, that is, when different serial port devices are installed on the test board, each contact point in each group of contact points is used to transmit the corresponding signal or data. Of course, M is not limited to 8, and can also be other values, such as 40, or 80, or 160, or others.

[0062] The present application also provides a device testing method, which is applied to the device testing apparatus of any of the above embodiments. Figure 4 As shown, Figure 4This is a flow chart of a device testing method provided by an embodiment of the present application, and the process includes:

[0063] S401, the main controller receives a communication mode setting instruction sent by the host computer;

[0064] S402, the main controller controls the target drive unit to be powered on based on the communication mode setting instruction, wherein the communication mode setting instruction is used to instruct the main controller to select a drive unit that matches the communication mode of the device under test, and the device under test is located on the test board;

[0065] S403, when the main controller receives the test vector file sent by the host computer, it generates a communication timing signal based on the test vector file, wherein the test vector file is used to instruct to test the device under test;

[0066] S404, the main controller sends a target communication signal to the device under test through the target drive unit, wherein the target communication signal is obtained by the target drive unit processing the communication timing signal, and the target communication signal matches the device under test;

[0067] S405 , the main controller receives an output response signal returned by the device under test, and performs back-check on the device under test based on the output response signal to obtain a test result.

[0068] In the above embodiment, the device testing method enables the main controller to receive the communication mode setting instruction of the host computer and control the target drive unit to power on, select the matching drive unit according to the device to be tested, and ensure that the main controller can send the target communication signal matching the device to be tested through the target drive unit. This method realizes the effective test of the device to be tested under different serial port communication modes by generating a communication timing signal and performing a checkback according to the output response signal, thereby ensuring the accuracy of the test result. The main controller receives the communication mode setting instruction sent by the host computer, and selects the drive unit matching the communication mode of the device to be tested to power on according to the instruction. This method ensures that the test device can be compatible with the devices to be tested in different communication modes, thereby improving the versatility and flexibility of the test. The device to be tested can be any of the following: UART serial port device, SPI serial port device, IIC serial port device, CAN serial port device and SWD serial port device, that is, the device testing device and the device testing method are applicable to various serial port devices, thereby improving the applicability of the device testing device and the testing method. The invention effectively solves the technical problems such as poor compatibility of testing multiple types of serial port devices, great difficulty in testing asynchronous communication devices, inaccurate test result judgment, and low test automation, improves test efficiency and accuracy, and significantly improves the versatility and flexibility of test equipment. The test schemes in the related art are usually designed for specific types of serial port devices, lacking extensive support for different types of serial port devices (such as UART, SPI, IIC, CAN, SWD, etc.), which results in the need for frequent replacement or adjustment of test equipment to adapt to different types of devices, increasing the test cost and complexity. Existing test schemes often rely on manual observation of oscilloscopes and other methods to judge test results. This method is not only inefficient, but also easily affected by human factors, resulting in inaccurate test results. The device can realize compatible testing of multiple types of serial port devices such as UART, SPI, IIC, CAN, SWD, etc. by integrating multiple drive circuits that support different serial port communication modes, significantly improving the versatility and flexibility of test equipment. The device can accurately capture and compare the response output of the device through real-time communication between the main controller and the device under test, which is particularly suitable for testing asynchronous communication interface devices such as UART and CAN, and improves the accuracy and reliability of the test. The test device automatically analyzes and judges the test results through the main controller, reducing manual intervention, improving test efficiency and accuracy, and reducing the impact of human factors on the test results. The entire test process is controlled by the host computer. By sending test vector files and receiving feedback from the main controller, the test process is automatically controlled, significantly shortening the test cycle, improving test efficiency, and meeting the needs of large-scale production testing.

[0069] In an optional embodiment, the method further includes: uploading the test result to a host computer so that the host computer can display it.

[0070] In the above embodiment, the test results are uploaded to the host computer so that the host computer can display them, which realizes the visualization of the test results and facilitates the user to intuitively monitor and analyze the state or quality of the device under test. By uploading the test results to the host computer and displaying them using the graphical interface or data processing capabilities of the host computer, the tester can intuitively see the various data and charts generated during the test. This visual display method not only improves the readability of the test results, but also facilitates the tester to conduct in-depth analysis and comparison of the test results.

[0071] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0072] There are many problems with device testing in related technologies: (1) Existing devices cannot effectively determine the device return results during dynamic testing. Existing devices generally use FPGA to generate 0 or 1 signals based on graphic files and apply them to the device under test. The entire board of devices is aged in parallel, and each device has an output feedback check. For synchronous communication interface (such as SPI) devices, the communication clock is provided by FPGA, so the device output can be accurately compared; but for asynchronous communication interfaces (such as UART, IIC, CAN, SWD, etc.), there is no synchronous communication clock, and it is impossible to accurately determine when the device will reply, and it is impossible to effectively compare the device output. (2) Existing devices cannot age differential bus communication interface (such as RS485, CAN, etc.) devices. Existing devices generally generate signal amplitudes of single-ended drive signals relative to the ground through FPGA, and cannot generate differential signals. Devices with RS485 and CAN interfaces require external PHY chips to communicate. (3) Existing devices cannot obtain the register values ​​of the device under test. Existing device technology can only generate synchronous drive signals, and the entire board of devices are dynamically aged synchronously, but it cannot effectively obtain the register values ​​of the device.

[0073] The embodiment of the present application provides a device testing apparatus and method, which is suitable for various types of serial port devices. The present application adopts an MCU controller with an ARM core as the main control to handle communication with the host computer, including communication mode setting, test vector reception and storage, test signal generation and device output signal feedback, test result uploading, etc. Figure 5 This is an overall flow chart of a serial port device test provided by an embodiment of the present application, which specifically includes the following contents:

[0074] Step 1: The host computer sends the communication mode setting, and the controller controls the corresponding circuit to power on and select this communication mode; for example, the communication mode with the device under test is set to any one of UART, IIC, SPI, CAN and SWD;

[0075] Step 2: The host computer sends the aging test vector file, and the controller stores it after receiving it;

[0076] Step 3: The controller simulates the corresponding communication timing according to the selected communication mode, and selects the device to be tested by time-sharing polling through the analog switch. The controller communicates with each device in turn, and can set parameters for the device, modify register configuration, and read registers, etc. It can obtain the test status of each device in real time and upload the results to the host computer for display.

[0077] Figure 6 is a block diagram of a device testing system provided in an embodiment of the present application, such as Figure 6 As shown, the system includes a host computer, a main controller, a drive module and a test board, wherein the drive module includes Figure 6 Each group of multiplexer switches, CAN PHY chips and each group of drive circuits, Figure 6 The devices under test DUT1-40 are placed on the test board. The first group of multiplexer switches can include five 8-way check switches, which are equivalent to the aforementioned 8-channel switches. The number of multiplexer switches included in each group can be set according to actual test needs. If each group of multiplexer switches includes five 8-way check switches, the 40 devices under test on the test board can be polled.

[0078] The driver board (i.e. the circuit board of the driver module) has a total of 160 gold finger signal PINs, and 4 pins can be independently assigned to each DUT. The main controller has 6 pins for communication, of which COM_IO1, COM_IO2, COM_IO3, and COM_IO4 can realize communication tests in UART, IIC, SPI, and SWD modes through mode configuration; CAN_TX and CAN_RX can realize communication tests in CAN mode. In these 5 communication modes, the pins are reused, and the specific reuse is as follows:

[0079] COM_IO1: SPI_CS / IIC_SDA / SWDIO (I / O)

[0080] COM_IO2: SPI_CLK / IIC_SCL / SWCLK(O)

[0081] COM_IO3: SPI_MISO / UART_RX / CAN_H(I)

[0082] COM_IO4: SPI_MOSI / UART_TX / CAN_L(O)

[0083] The six pins COM_IO1, COM_IO2, COM_IO3, COM_IO4, CAN_TX, and CAN_RX of the main controller correspond to the aforementioned first pin, second pin, third pin, fourth pin, fifth pin, and sixth pin respectively.

[0084] Combination Figure 7 , Figure 8 Different modes of device testing are described.

[0085] Figure 8 U1-U4 respectively represent a multi-way check switch, specifically an 8-way check switch, A, B, and C in U1 represent digital control terminals, which are used to control the channel selection, and U5-U8 respectively represent a level conversion unit or a level conversion chip, or a level conversion circuit.

[0086] In UART mode, EN1_3 and EN1_4 are enabled, and the DPS1 voltage is set to a voltage consistent with the logic high level of the device under test. The hardware UART of the main controller generates the corresponding read and write timing, selects the device to be communicated through the multiplexer (i.e., the multi-way multiplexer switch), and the signal is driven to perform signal level conversion. The excitation signal passes through the gold finger to the RX pin of the DUT on the test board, and the TX pin outputs a response signal to the main controller for feedback, thereby realizing the test of the device of the UART communication interface.

[0087] In IIC mode, EN1_1 and EN1_2 are enabled, DPS1 sets the working voltage, the main controller simulates the IIC read and write timing, selects the device to be communicated through the analog switch, selects the device to be communicated through the multiplexer, and the signal is driven to perform signal level conversion. DUTx_IO1 is connected to the IIC_SDA of the device, and DUTx_IO2 is connected to the IIC_SCL of the device. DUTx_IO1 is a bidirectional IO port, which can realize the test of the device with IIC communication interface. DUTx represents any one of DUT1-DUT8.

[0088] In SPI mode, EN1_1, EN1_2, EN1_3, and EN1_4 are all enabled, DPS1 sets the operating voltage, the main controller simulates the SPI read and write timing, selects the device to be communicated through the analog switch, selects the device to be communicated through the multiplexer, the signal is driven to perform signal level conversion, DUTx_IO1 is connected to the device's SPI_CS, DUTx_IO2 is connected to the device's SPI_CLK, DUTx_IO3 is connected to the device's SPI_MISO, and DUTx_IO4 is connected to the device's SPI_MOSI, which can realize the test of devices with SPI communication interface.

[0089] In SWD mode, EN1_1 and EN1_2 are enabled, DPS1 sets the operating voltage, and the main controller simulates SWD timing to communicate with the device under test. ARM core MCUs all have SWD burning and debugging interfaces. By simulating SWD timing, the device under test can be firmware burned and built-in self-test and register value reading can be performed.

[0090] Figure 7 U9-U10 respectively represent a multi-way check switch, specifically an 8-way check switch. A, B, and C in U9 and U10 represent digital control terminals, which are used to control the channel selection. CAN1 corresponds to the aforementioned CAN PHY chip, which is used to convert single-ended drive signals and differential signals.

[0091] In CAN communication mode, the power supply of the drive circuit is partially turned off, corresponding to Figure 8 U5-U8 are all turned off, and the main controller generates the differential pair signals CANH and CANL of the CAN bus through CAN PHY, corresponding to the aforementioned CAN_H, CAN_L, EN2_1, EN2_2 enable, and communicates with each device in a time-sharing manner through a low-on resistance multiplexer to implement the test of the device of the CAN communication interface.

[0092] Through the embodiments of the present application, the problem that the operation results cannot be effectively judged in the dynamic test of the existing equipment is solved; the problem that the existing equipment cannot test the differential bus communication interface (such as RS485, CAN, etc.) type devices is solved; and the problem that the existing equipment cannot obtain the register value of the device to be tested is solved.

[0093] The present application also provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed, any one of the method steps described above is executed.

[0094] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0096] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0097] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0098] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0099] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, mobile hard drives, magnetic disks or optical disks.

[0100] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present disclosure.

[0101] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A device testing apparatus, characterized in that: include: Main controller, drive module, where The main controller is connected to the host computer for communication, and the main controller is used to receive a test vector file sent by the host computer, wherein the test vector file is used to instruct to test the device under test; The main controller is connected to the test board through the driving module, the main controller is used to select a target driving unit to communicate with the device under test, and the main controller is also used to perform a backcheck on the device under test according to an output response signal of the device under test, wherein the device under test is located on the test board, the target driving unit is a driving circuit matching the device under test, the driving module includes the target driving unit, and the driving module includes a plurality of driving circuits supporting different serial port communication modes; Wherein, the devices under test include: UART serial port devices, SPI serial port devices, IIC serial port devices, CAN serial port devices, SWD serial port devices; The driving module includes a first group of multi-way switches and a group of driving units, wherein each multi-way switch in the first group of multi-way switches corresponds to a level conversion unit in the group of driving units, the main controller is electrically connected to the test board through each of the multi-way switches and a corresponding level conversion unit, each multi-way switch in the first group of multi-way switches is used to transmit a test signal between the main controller and the device under test, and the level conversion unit is used to perform level conversion processing on the test signal, wherein the test signal includes an excitation test signal for the device under test or the output response signal; The first group of multi-way switches includes a first 8-channel switch, a second 8-channel switch, a third 8-channel switch and a fourth 8-channel switch, the group of driving units includes a first level conversion unit, a second level conversion unit, a third level conversion unit and a fourth level conversion unit, and the target driving unit includes: In the case where the device under test is the SPI serial port device, the target drive unit includes: the first 8-channel switch, the second 8-channel switch, the third 8-channel switch, the fourth 8-channel switch, the first level conversion unit, the second level conversion unit, the third level conversion unit and the fourth level conversion unit, wherein the common input and output ends of the first 8-channel switch are electrically connected to the first pin of the main controller, and the multi-way input and output ends of the first 8-channel switch are electrically connected to the test board through the first level conversion unit; the common input and output ends of the second 8-channel switch are electrically connected to the second pin of the main controller, and the multi-way input and output ends of the second 8-channel switch are electrically connected to the test board through the second level conversion unit; the common input and output ends of the third 8-channel switch are electrically connected to the first .... The third pin of the main controller is electrically connected, and the multi-way input and output ends of the third 8-channel switch are electrically connected to the test board through the third level conversion unit; the common input and output ends of the fourth 8-channel switch are electrically connected to the fourth pin of the main controller, and the multi-way input and output ends of the fourth 8-channel switch are electrically connected to the test board through the fourth level conversion unit, the first pin of the main controller is used to output the SPI_CS signal, the second pin of the main controller is used to output the SPI_CLK signal, the third pin of the main controller is used to receive the SPI_MISO signal, and the fourth pin of the main controller is used to output the SPI_MOSI signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit; In the case where the device under test is the IIC serial port device, the target drive unit includes: the first 8-channel switch and the second 8-channel switch, wherein the common input and output end of the first 8-channel switch is electrically connected to the first pin of the main controller, and the common input and output end of the second 8-channel switch is electrically connected to the second pin of the main controller, the first pin of the main controller is used to transmit the IIC_SDA signal, and the second pin of the main controller is used to output the IIC_CLK signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit; In the case where the device under test is the SWD serial port device, the target drive unit includes: the first 8-channel switch and the second 8-channel switch, wherein the common input and output end of the first 8-channel switch is electrically connected to the first pin of the main controller, the common input and output end of the second 8-channel switch is electrically connected to the second pin of the main controller, the first pin of the main controller is used to transmit the SWD_IO signal, and the second pin of the main controller is used to output the SWD_CLK signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time-sharing manner through the target drive unit; In the case where the device under test is the UART serial port device, the target drive unit includes: the third 8-channel switch and the fourth 8-channel switch, wherein the common input and output end of the third 8-channel switch is electrically connected to the third pin of the main controller, and the common input and output end of the fourth 8-channel switch is electrically connected to the fourth pin of the main controller, the third pin of the main controller is used to receive a UART_RX signal, and the fourth pin of the main controller is used to output a UART_TX signal, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in a time-sharing manner through the target drive unit.

2. The device according to claim 1, characterized in that The driving module also includes a second group of multi-way switches and a CAN PHY chip, wherein the main controller is connected to the second group of multi-way switches through the CAN PHY chip, the CAN PHY chip is used to convert a single-ended driving signal into a differential signal, and each multi-way switch in the second group of multi-way switches is connected to the test board.

3. The device according to claim 2, characterized in that The second set of multiplex switches includes a fifth 8-channel switch and a sixth 8-channel switch, wherein: In the case where the device under test is the CAN serial port device, the target drive unit includes: the fifth 8-channel switch and the sixth 8-channel switch, wherein the data receiving pin of the CAN PHY chip is electrically connected to the fifth pin of the main controller, the data sending pin of the CAN PHY chip is electrically connected to the sixth pin of the main controller, the high signal pin of the CAN PHY chip is electrically connected to the common input and output end of the fifth 8-channel switch, the low signal pin of the CAN PHY chip is electrically connected to the common input and output end of the sixth 8-channel switch, the fifth pin of the main controller is used to output the excitation test signal, and the sixth pin of the main controller is used to receive the output response signal of the CAN serial port device, the test board includes 8 devices under test, and the main controller is used to poll each of the 8 devices under test in time sharing through the target drive unit.

4. The device according to any one of claims 1 to 3, characterized in that The main controller is also used to generate a communication timing signal based on the test vector file, and communicate with the device under test based on the communication timing signal, wherein the communication timing signal serves as an excitation test signal for the device under test.

5. The device according to claim 4, characterized in that The driving module further comprises a gold finger, which is arranged at a side of the driving module close to the test board, and the driving module is connected to the test board via the gold finger.

6. The device according to claim 5, characterized in that The gold finger includes M groups of contact points, K contact points in each group of contact points are electrically connected to K test pins of the device under test, and the K contact points in each group of contact points are electrically connected to a level conversion unit of the target drive unit, wherein M is a positive integer greater than or equal to 1, and K is a positive integer greater than or equal to 2.

7. A device testing method, characterized in that: The device testing device according to any one of claims 1 to 6 comprises: The main controller receives a communication mode setting instruction sent by the host computer; The main controller controls powering on the target drive unit based on the communication mode setting instruction, wherein the communication mode setting instruction is used to instruct the main controller to select a drive unit that matches the communication mode of the device under test, and the device under test is located on the test board; The main controller generates a communication timing signal based on the test vector file when receiving the test vector file sent by the host computer, wherein the test vector file is used to instruct to test the device under test; The main controller sends a target communication signal to the device under test through the target drive unit, wherein the target communication signal is obtained by the target drive unit processing the communication timing signal, and the target communication signal matches the device under test; The main controller receives an output response signal returned by the device under test, and performs a back check on the device under test based on the output response signal to obtain a test result.

8. The method according to claim 7, characterized in that The method further includes: uploading the test result to the host computer so that the host computer can display it.

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