A universal chip acquisition system

Abstract

The present application relates to the field of chip technology, and in particular to a universal chip acquisition system, the system comprising: a chip management module contained in a target chip, M target modules and their corresponding acquisition module sets, wherein the acquisition module set comprises an acquisition management module, an acquisition access module and an acquisition monitoring module, the acquisition monitoring module monitors abnormal information and sends it to the chip management module, the chip management module determines the configuration value according to the abnormal information and is configured by the acquisition management module, the acquisition access module parses the access request, executes the access process, returns the access result, and dynamically determines the acquisition status of the target module by monitoring the abnormal information of the target module, so that the entire target chip will not be unavailable due to the abnormality of a certain target module, and ensures that the target module can respond to the access request normally through the acquisition access module, thereby greatly improving the reliability of the chip, and can manage the target module according to the demand, thereby greatly improving the flexibility of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a universal chip acquisition system. Background Art

[0002] With the rapid development of chip technology, the functions of chips are increasing, and the performance of chips is getting higher and higher. The existing method of improving chip performance generally adopts multi-module integration design, that is, integrating several or even hundreds of single modules into the chip to achieve chip performance improvement. For example, in order to improve the overall computing performance, the chip will integrate hundreds or thousands of computing units, and in order to increase the interconnection bandwidth, the chip will contain several interconnection modules.

[0003] The advantage of the above method is that the chip has strong scalability. Regardless of the size of the chip system, or the performance, it can be integrated into multiple modules to meet the needs. Therefore, the above method is widely used in high-performance chips such as CPU and GPU.

[0004] However, in order to achieve high performance, the number of integrated single modules will increase. The more modules integrated in the chip, the higher the probability of defects, which will lead to lower chip yield. Once a single module has a problem, the entire chip will not work and the entire chip will become a waste. In addition, the flexibility of chip integration is poor. Faced with different performance requirements, chips are generally always integrated according to the highest performance, that is, the largest number of modules. This will result in other requirements such as mid- and low-end products being unable to be flexibly met. If the chip is redesigned to reduce the number of integrated modules, the chip design cycle will be longer. If high-performance chips are used directly for mid- and low-end needs, the chip power consumption will be too large and the chip's competitiveness will decline.

[0005] Therefore, how to manage the modules integrated in the chip to improve the availability and flexibility of the chip has become an urgent problem to be solved. Summary of the invention

[0006] In view of the above technical problems, the technical solution adopted by the present invention is:

[0007] A universal chip acquisition system, the system comprises: a chip management module contained in a target chip, M target modules and their corresponding acquisition module sets, wherein the acquisition module set comprises an acquisition management module, an acquisition access module and an acquisition monitoring module, and M is a positive integer.

[0008] The acquisition monitoring module is used to monitor the abnormal information of the corresponding target module and send the abnormal information to the chip management module.

[0009] The chip management module is used to determine the configuration value of the corresponding acquisition register according to the abnormal information after receiving the abnormal information.

[0010] The acquisition management module corresponds to an acquisition register, and the acquisition management module is used to configure the corresponding acquisition register. When the configuration value of the acquisition register is a first preset value, the target module corresponding to the acquisition management module is in a first acquisition state, and the data and clock in the target module are no longer flipped. When the configuration value of the acquisition register is a second preset value, the target module corresponding to the acquisition management module is in a second acquisition state, and the data and clock in the target module are flipped normally.

[0011] The acquisition access module is used to parse the access request, execute a preset access process, and return an access result corresponding to the access request when the corresponding target module receives the access request.

[0012] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, a universal chip acquisition system provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0013] The present invention provides a universal chip acquisition system, the system comprising: a chip management module included in a target chip, M target modules and their corresponding acquisition module sets, wherein the acquisition module set comprises an acquisition management module, an acquisition access module and an acquisition monitoring module, M is a positive integer, the acquisition monitoring module is used to monitor abnormal information of the corresponding target module, and send the abnormal information to the chip management module, the chip management module is used to determine the configuration value of the corresponding acquisition register according to the abnormal information after receiving the abnormal information, the acquisition management module corresponds to the acquisition register, the acquisition management module is used to configure the corresponding acquisition register, when the configuration value of the acquisition register is a first preset value, the target module corresponding to the acquisition management module is in a first acquisition state, and the data and clock in the target module are no longer flipped, when the configuration value of the acquisition register is a second preset value, the target module corresponding to the acquisition management module is in a second acquisition state, and the data and clock in the target module flip normally, and the acquisition access module is used to parse the access request when the corresponding target module receives the access request, execute a preset access process, and return the access result corresponding to the access request.

[0014] It can be seen that by monitoring the abnormal information of the target module and dynamically determining the acquisition status of the target module, the entire target chip will not be unavailable due to the abnormality of a certain target module. The acquisition access module can ensure that the target module can respond normally to access requests in any state, thereby greatly improving the reliability of the chip. The target module can be managed according to needs, greatly improving the flexibility of the chip in various scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of the architecture of a general chip acquisition system provided by an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of the architecture of a collection management module in a general chip collection system provided by an embodiment of the present invention;

[0018] Figure 3 A first schematic diagram of the architecture of a collection access module in a general chip collection system provided by an embodiment of the present invention;

[0019] Figure 4 A second schematic diagram of the architecture of a collection access module in a general chip collection system provided by an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of a general chip acquisition system during execution provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0022] This embodiment provides a general chip acquisition system. Figure 1, is a schematic diagram of the architecture of a general chip acquisition system provided by an embodiment of the present invention, the system comprising: a chip management module included in a target chip, M target modules and their corresponding acquisition module sets, wherein the acquisition module set comprises an acquisition management module, an acquisition access module and an acquisition monitoring module, and M is a positive integer;

[0023] The acquisition monitoring module is used to monitor the abnormal information of the corresponding target module and send the abnormal information to the chip management module;

[0024] The chip management module is used to determine the configuration value of the corresponding acquisition register according to the abnormal information after receiving the abnormal information;

[0025] The acquisition management module corresponds to the acquisition register, and the acquisition management module is used to configure the corresponding acquisition register. When the configuration value of the acquisition register is a first preset value, the target module corresponding to the acquisition management module is in a first acquisition state, and the data and clock in the target module are no longer flipped. When the configuration value of the acquisition register is a second preset value, the target module corresponding to the acquisition management module is in a second acquisition state, and the data and clock in the target module are flipped normally.

[0026] The acquisition access module is used to parse the access request, execute a preset access process, and return an access result corresponding to the access request when the corresponding target module receives the access request.

[0027] Among them, the target chip can integrate M target modules. The type of the target module can be a computing unit, an interconnection module, etc. The implementer can determine the type of the target module according to actual needs. Each target module has a corresponding set of acquisition modules.

[0028] Specifically, the acquisition monitoring module actively monitors the state of the target module. If an abnormality occurs in the target module, the abnormality information is reported to the chip management module. Otherwise, no report is made.

[0029] After the chip management module determines the configuration value of the corresponding acquisition register, the acquisition management module configures the acquisition register according to the configuration value.

[0030] In one implementation, the implementer may directly set the configuration value according to actual needs, and then the acquisition management module configures the acquisition register according to the configuration value.

[0031] When the target module is in the first acquisition state, the data and clock in the target module no longer flip. In this state, all data of the target module remain unchanged and no longer flip. The corresponding dynamic power consumption is basically zero, and the clock of the target module enters the gated state and no longer flips.

[0032] When the target module is in the second acquisition state, the data and clock in the target module are flipped normally. In this state, all data and logic of the target module are processed normally, and the clock flip of the target module provides a normal clock for the target module.

[0033] See also Figure 2 , is a schematic diagram of the architecture of a collection management module in a general chip collection system provided in an embodiment of the present invention.

[0034] In a specific implementation manner, the abnormal information includes read data abnormality, read data return status abnormality, write data return status abnormality and no return abnormality;

[0035] The acquisition monitoring module is also used to count the number of abnormalities of the abnormal information when monitoring the abnormal information of the corresponding target module;

[0036] Correspondingly, the acquisition monitoring module sends the abnormal information and its corresponding abnormal number to the chip management module.

[0037] Among them, the exception information includes but is not limited to read data exception, read data return status exception, write data return status exception and no return exception, etc. The read data exception may refer to the data read from the target module being different from the expected value, the read data return status exception may refer to the read data return status being different from the first default normal state, the write data return status exception may refer to the read data return status being different from the second default normal state, the no return exception may refer to no return after a certain period of time, the first default normal state and the second default normal state may both be zero in this embodiment, and the time required for judging the no return exception can be configured by the implementer.

[0038] Specifically, when the abnormal information of the corresponding target module is monitored, the collection and monitoring module increases the abnormal number of the abnormal information by one to update the abnormal number, and then sends the abnormal information and its corresponding abnormal number to the chip management module.

[0039] In a specific implementation, determining the configuration value of the corresponding acquisition register according to the abnormal information includes:

[0040] According to the abnormal information and its corresponding abnormal number, a configuration value of a corresponding acquisition register is determined.

[0041] Among them, determining the configuration value of the corresponding acquisition register according to the exception information and its corresponding exception number can effectively improve the flexibility and effectiveness of the acquisition operation control of the target module and can adapt to various acquisition needs.

[0042] In a specific implementation, determining the configuration value of the corresponding acquisition register according to the abnormal information and its corresponding abnormal number includes:

[0043] If the abnormal information is consistent with the preset reference information, determining that the configuration value of the corresponding acquisition register is the first preset value;

[0044] If the abnormal information is inconsistent with the preset reference information and the number of abnormalities corresponding to the abnormal information is greater than or equal to the preset reference threshold corresponding to the abnormal information, determining that the configuration value of the corresponding acquisition register is the first preset value;

[0045] Otherwise, it is determined that the configuration value of the corresponding acquisition register is the second preset value.

[0046] Among them, the reference information may refer to abnormal information with a higher severity. For example, a no-return abnormality may cause the chip to hang, so the reference information is set to include a no-return abnormality. The reference information may be configured by the implementer. The preset reference threshold may be used to determine whether collection and processing are required when the target module has abnormal information with a lower severity.

[0047] Specifically, in this embodiment, the first preset value may be 1, and the second preset value may be 0. The implementer may adjust the values ​​of the first preset value and the second preset value according to actual conditions. It should be noted that the default value of the acquisition register corresponding to the target module is the second preset value.

[0048] In a specific implementation manner, when the corresponding target module receives the access request, parsing the access request, executing a preset access process, and returning an access result corresponding to the access request includes:

[0049] When the corresponding target module is in the first acquisition state and the access request is parsed as a read request, a read completion state and a third preset value are returned as the access result, and the access request is discarded;

[0050] When the corresponding target module is in the first acquisition state, and the access request is parsed as a write request, a write completion state is returned as the access result, and the access request is discarded.

[0051] The third preset value may be set by the implementer, for example, to 0, 1 or other values.

[0052] Specifically, when the target module is in the first acquisition state, the read request will return a read completion state and a third preset value, and the write request will return a write completion state. The access request will be discarded and will no longer continue to access the target module, but the access request can still obtain the access result normally. Therefore, when the target module is accessed after being in the first acquisition state, the target chip can still work normally without hanging, thereby improving the availability of the chip.

[0053] See also Figure 3 , is a first architecture diagram of an acquisition access module in a general chip acquisition system provided in an embodiment of the present invention, and the first architecture diagram corresponds to a case where the target module is in a first acquisition state.

[0054] In a specific implementation manner, when the corresponding target module receives the access request, parsing the access request, executing a preset access process, and returning an access result corresponding to the access request also includes:

[0055] When the corresponding target module is in the second acquisition state and the access request is parsed as a read request, a read operation is performed on the target module, and a read operation result and a read completion status are returned as the access result;

[0056] When the corresponding target module is in the second acquisition state, and the access request is parsed as a write request, a write operation is performed on the target module, and a write completion state is returned as the access result.

[0057] Among them, when the target module is in the second acquisition state and the access request is parsed as a read request, the read request is sent to the target module, a read operation is performed on the target module, and the read data is normally returned as the read operation result, and the read operation result and the read completion status are used as the access result.

[0058] When the target module is in the second acquisition state, and the access request is parsed as a write request, the write request is sent to the target module, the data in the target module is updated normally, and the write completion state is used as the access result.

[0059] See also Figure 4 , is a second architecture diagram of an acquisition access module in a general chip acquisition system provided in an embodiment of the present invention, and the second architecture diagram corresponds to a case where the target module is in a second acquisition state.

[0060] In a specific implementation, the chip management module is further used to determine the configuration value of the acquisition register corresponding to each target module according to the first performance indicator I of the target chip and the second performance indicator J of the target module.

[0061] Among them, the first performance indicator I may refer to the performance indicator required by the target chip, which can be determined based on factors such as the application scenario of the target chip. The second performance indicator J may refer to the performance indicator that a single target module can provide. It should be noted that in this embodiment, it is assumed that the differences between the performance indicators that each target module can provide can be ignored. Therefore, the second performance indicator J is used to represent the performance indicator that a single target module can provide.

[0062] In addition to collecting data on the target module based on the abnormal information of the target module, the chip management module can also collect data on the target module from the performance aspect according to the first performance indicator I of the target chip and the second performance indicator J of the target module, so that the performance requirements and the performance provided by the target chip can be adapted to each other, avoiding the situation where the scene cannot be adapted due to factors such as chip power consumption. For example, for mid- and low-end chips, the performance requirements are low, and the expected operating power consumption is also low. If a chip with a high module integration number is used, it will result in excess performance and excessive power consumption. If a chip with a low module integration number is used, the chip needs to be redesigned. The present embodiment can make a chip with a high module integration number adapt to the requirements of mid- and low-end chips, and can ensure that both performance and power consumption are adapted to the chip requirements. There is no need to design the chip multiple times. Only one design is required to achieve chip serialization and meet different performance requirements, thereby improving the flexibility of the chip.

[0063] In a specific implementation, determining the configuration value of the acquisition register corresponding to each target module according to the first performance indicator I of the target chip and the second performance indicator J of the target module includes:

[0064] Determine the number K of target modules in the second acquisition state;

[0065] If (J-1)×K≥I, then the configuration values ​​of the acquisition registers corresponding to R target modules in the target modules in the second acquisition state are set to the first preset value, and R satisfies the condition: K-(I / J)-1<R≤K-(I / J) and R is a positive integer.

[0066] Among them, (J-1)×K≥I indicates that the performance indicators provided by the target module have far exceeded the performance requirements of the target chip. At this time, the configuration values ​​of the acquisition registers corresponding to the R target modules in the second acquisition state can be set to the first preset value, thereby reducing the performance and power consumption of the target chip and adapting to the chip demand scenario.

[0067] K-(I / J)-1<R≤K-(I / J) can be used to constrain the number of remaining target modules to be minimized under the premise of supporting the requirements of the first performance indicator, so as to reduce power consumption.

[0068] See also Figure 5, is a flow chart of a general chip acquisition system provided by an embodiment of the present invention during execution, wherein determining the performance requirement may refer to the chip management module determining the configuration value of the acquisition register corresponding to each target module according to the first performance indicator I of the target chip and the second performance indicator J of the target module, the acquisition monitoring module monitoring the state of the target module, if the target module is abnormal, reporting the abnormal information and the number of abnormal times to the chip management module, the chip management module determining the configuration value and configuring it by the acquisition management module, when the configuration value is a first preset value, the target module is in a first acquisition state, in which the data and clock of the target module are no longer flipped, when the configuration value is a second preset value, the target module is in a second acquisition state, and the step of determining the configuration value by the chip management module is returned, when the configuration value is the first preset value and the clock and data have been processed, the acquisition access module processes the access request to the target module, and normally returns the access result corresponding to the access request, after the acquisition of the target module is completed, that is, after the target module does not need to maintain the first acquisition state, the acquisition completion state is returned to the chip management module.

[0069] It can be seen that this embodiment dynamically determines the acquisition status of the target module by monitoring the abnormal information of the target module, and the entire target chip will not be unavailable due to the abnormality of a certain target module. The acquisition access module is used to ensure that the target module can respond to access requests normally in any state, thereby greatly improving the reliability of the chip, and the target module can be managed according to needs, greatly improving the flexibility of the chip in various scenarios.

[0070] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A universal chip acquisition system, characterized in that: The system comprises: a chip management module included in the target chip, M target modules and their corresponding acquisition module sets, wherein the acquisition module set comprises an acquisition management module, an acquisition access module and an acquisition monitoring module, and M is a positive integer; The acquisition monitoring module is used to monitor the abnormal information of the corresponding target module, count the abnormal times of the abnormal information, and send the abnormal information and its corresponding abnormal times to the chip management module; The chip management module is used to determine the configuration value of the corresponding acquisition register according to the abnormal information and the corresponding abnormal number after receiving the abnormal information, wherein the configuration value of the corresponding acquisition register according to the abnormal information and the corresponding abnormal number includes: If the abnormal information is consistent with the preset reference information, determining that the configuration value of the corresponding acquisition register is a first preset value; If the abnormal information is inconsistent with the preset reference information and the number of abnormalities corresponding to the abnormal information is greater than or equal to the preset reference threshold corresponding to the abnormal information, determining that the configuration value of the corresponding acquisition register is the first preset value; Otherwise, determining that the configuration value of the corresponding acquisition register is a second preset value; The chip management module is further used to determine the configuration value of the acquisition register corresponding to each target module according to the first performance indicator I of the target chip and the second performance indicator J of the target module, wherein the configuration value of the acquisition register corresponding to each target module according to the first performance indicator I of the target chip and the second performance indicator J of the target module includes: Determine the number K of target modules in the second acquisition state; If (J-1)×K≥I, then the configuration values ​​of the acquisition registers corresponding to R target modules in the target modules in the second acquisition state are set to the first preset value, and R satisfies the condition: K-(I / J)-1<R≤K-(I / J) and R is a positive integer; The acquisition management module corresponds to the acquisition register, and the acquisition management module is used to configure the corresponding acquisition register. When the configuration value of the acquisition register is a first preset value, the target module corresponding to the acquisition management module is in a first acquisition state, and the data and clock in the target module are no longer flipped. When the configuration value of the acquisition register is a second preset value, the target module corresponding to the acquisition management module is in a second acquisition state, and the data and clock in the target module are flipped normally. The acquisition access module is used to parse the access request, execute a preset access process, and return an access result corresponding to the access request when the corresponding target module receives the access request.

2. The universal chip acquisition system according to claim 1, characterized in that: The abnormal information includes read data abnormality, read data return status abnormality, write data return status abnormality and no return abnormality.

3. The universal chip acquisition system according to claim 1, characterized in that: When the corresponding target module receives the access request, parsing the access request, executing a preset access process, and returning an access result corresponding to the access request includes: When the corresponding target module is in the first acquisition state and the access request is parsed as a read request, a read completion state and a third preset value are returned as the access result, and the access request is discarded; When the corresponding target module is in the first acquisition state, and the access request is parsed as a write request, a write completion state is returned as the access result, and the access request is discarded.

4. The universal chip acquisition system according to claim 3, characterized in that: When the corresponding target module receives the access request, the access request is parsed, a preset access process is executed, and an access result corresponding to the access request is returned, further comprising: When the corresponding target module is in the second acquisition state and the access request is parsed as a read request, a read operation is performed on the target module, and a read operation result and a read completion status are returned as the access result; When the corresponding target module is in the second acquisition state, and the access request is parsed as a write request, a write operation is performed on the target module, and a write completion state is returned as the access result.

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