Circuit board packaging method and circuit board

Abstract

The present invention discloses a circuit board packaging method and a circuit board, the method comprising: welding a step carrier plate on a chip window of the circuit board, the step carrier plate comprising a first carrier plate and a second carrier plate, the first carrier plate and the second carrier plate being in an inverted step-shaped structure; setting a welding window in the first area of ​​the second carrier plate; setting a test node in the second area of ​​the second carrier plate; setting a convex wiring between the first carrier plate and the second carrier plate, so that the convex wiring is connected in series with the test node and then electrically connects the chip window and the welding window; welding the chip to be tested on the welding window. By adding a step carrier plate, the chip to be tested is suspended, and the suspended second carrier plate is convenient for setting the test node, the test node does not affect the dense components on the circuit board, and is connected in series with the convex wiring at the same time, so that the signal measured by the test node is less subject to reflection interference, and can be widely used in the field of circuit board packaging technology.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board packaging, and in particular to a circuit board packaging method and a circuit board. Background Art

[0002] In the board-level application system of the circuit board, an oscilloscope is usually used to measure and analyze the signal of the circuit board. However, the density of components on the circuit board is often high, and it is difficult to find a suitable measurement point to put the probe of the oscilloscope, making it difficult to carry out signal measurement. Summary of the invention

[0003] In view of this, an object of an embodiment of the present invention is to provide a circuit board packaging method and a circuit board, which can set measurement points on a circuit board with a high component density to facilitate signal measurement of the circuit board.

[0004] In a first aspect, an embodiment of the present invention provides a circuit board packaging method, comprising:

[0005] Welding a stepped carrier plate on the chip window of the circuit board, the stepped carrier plate comprising a first carrier plate and a second carrier plate, the first carrier plate being welded to the chip window, the second carrier plate being arranged on the first carrier plate, and the first carrier plate and the second carrier plate being in an inverted stepped structure;

[0006] Disposing a welding window in the first area of ​​the second carrier plate;

[0007] Setting a test node in a second area of ​​the second carrier, wherein the first area and the second area are both located on the same surface of the second carrier and do not interfere with each other, wherein the second area and the first area of ​​the second carrier are obtained according to the size of the chip to be tested and the components on the circuit board;

[0008] A convex wiring is arranged between the first carrier board and the second carrier board, so that the convex wiring is connected in series with the test node and then electrically connects the chip opening and the welding opening;

[0009] The chip to be tested is welded on the welding window.

[0010] In some optional embodiments, the first surface of the first carrier board is welded to the chip window through a first welding point, the second surface of the first carrier board and the first surface of the second carrier board are an integrated structure, the second surface of the second carrier board is provided with the first area and the second area, and the chip to be tested is welded to the welding window through a second welding point.

[0011] In some optional embodiments, the first solder joint, the test node and the second solder joint are connected in series through the convex trace, and the first solder joint and the second solder joint correspond to each other one by one.

[0012] In some optional embodiments, the processing method of the first carrier plate includes:

[0013] Obtaining size information of the chip to be tested;

[0014] The first carrier is obtained by CNC processing the stepped carrier according to the size information, so that the welding surface area of ​​the first carrier and the chip to be tested is specifically the same size, and the welding surface area represents the surface area of ​​the welding between the chip to be tested or the first carrier and the welding window or the chip window.

[0015] In some optional embodiments, the method further includes:

[0016] Acquire component information within a first preset range of the chip window;

[0017] Determine height information of the first carrier board according to the component information;

[0018] The first carrier plate having a first height is obtained by CNC processing the stepped carrier plate according to the height information, so that the second carrier plate on the first carrier plate does not interfere with components within the first preset range.

[0019] In some optional embodiments, the method further includes:

[0020] Hollowing out a second surface of the second carrier board according to the size information to obtain a plurality of corner structures;

[0021] The welding window is arranged in the corner structure.

[0022] In some optional embodiments, the method further includes:

[0023] Determining a side angle of the first carrier board according to the component information;

[0024] The first carrier plate having the side angle is obtained by CNC processing the stepped carrier plate, so that the first carrier plate and the components within the first preset range do not interfere with each other.

[0025] In some optional embodiments, the processing method of the second carrier plate includes:

[0026] Acquiring interference information at various positions on the second surface of the second carrier board;

[0027] Determining an optimal point with minimal interference according to the interference information;

[0028] determining a second height of the second carrier plate according to the first height;

[0029] Determine an optimal surface area of ​​the second surface of the second carrier board according to the component information and the size information;

[0030] The step carrier is CNC-processed to obtain the second carrier having the second height and the optimal surface area, so that the second carrier does not interfere with components within the first preset range, and the test node is located at the optimal point.

[0031] In some optional embodiments, obtaining interference information at various positions on the second surface of the second carrier board includes:

[0032] After determining, according to the component information and the first height, the signal quality measured by the test node after the test node is set at each position on the second surface of the second carrier board;

[0033] The interference information is determined according to the signal quality.

[0034] In a second aspect, an embodiment of the present invention provides a circuit board manufactured by the above-mentioned circuit board packaging method.

[0035] The implementation of the embodiment of the present invention includes the following beneficial effects: The embodiment of the present invention provides a circuit board packaging method, including: welding a step carrier on a chip window of a circuit board, the step carrier including a first carrier and a second carrier, the first carrier being welded to the chip window, the second carrier being arranged on the first carrier, the first carrier and the second carrier being in an inverted step-shaped structure; a welding window being arranged in a first area of ​​the second carrier; a test node being arranged in a second area of ​​the second carrier, the first area and the second area being both located on the same surface of the second carrier and not interfering with each other; a convex trace being arranged between the first carrier and the second carrier, so that the convex trace is connected in series with the test node and then electrically connects the chip window and the welding window; and the chip to be tested is welded on the welding window. By adding a step carrier at the position where the chip to be tested is welded on the circuit board, the chip to be tested is suspended on the circuit board, and the suspended second carrier facilitates the setting of the test node, the test node does not affect the dense components on the circuit board, and is connected in series with the convex trace, so that the signal measured through the test node is less subject to reflection interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flowchart of the steps of a circuit board packaging method provided by an embodiment of the present invention;

[0037] Figure 2 is a structural diagram of a circuit board after packaging provided by an embodiment of the present invention;

[0038] Figure 3is a top view of a second carrier board provided by an embodiment of the present invention;

[0039] Figure 4 is another circuit board structure diagram after packaging provided by an embodiment of the present invention;

[0040] Reference numerals: chip under test 100 , second solder joint 110 , convex trace 120 , second carrier 200 , test node 210 , corner structure 220 , first carrier 300 , first solder joint 310 , circuit board 400 . DETAILED DESCRIPTION

[0041] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0042] In the description of the present invention, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0043] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0044] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0045] The embodiment of the present invention provides a circuit board packaging method and a circuit board, wherein the circuit board packaging method includes: welding a stepped carrier on a chip window of a circuit board 400, the stepped carrier including a first carrier 300 and a second carrier 200, the first carrier 300 being welded to the chip window, the second carrier 200 being arranged on the first carrier 300, the first carrier 300 and the second carrier 200 being in an inverted stepped structure; a welding window being arranged in a first area of ​​the second carrier 200; a test node 210 being arranged in a second area of ​​the second carrier 200, the first area and the second area being both located on the same surface of the second carrier 200 and not interfering with each other; a convex trace 120 being arranged between the first carrier 300 and the second carrier 200, so that the convex trace 120 is connected in series with the test node 210 and then electrically connects the chip window and the welding window; and welding the chip 100 to be tested on the welding window. By adding a stepped carrier board at the position where the chip to be tested 100 is welded on the circuit board 400, the chip to be tested 100 is suspended on the circuit board 400, and the suspended second carrier board 200 is convenient for setting the test node 210. The test node 210 does not affect the densely packed components on the circuit board 400, and is connected in series with the convex trace 120, so that the signal measured through the test node 210 is less subject to reflection interference.

[0046] The circuit board packaging method according to the embodiment of the present invention is further described below.

[0047] Reference Figure 1-4 , Figure 1 A flowchart of a circuit board packaging method provided by an embodiment of the present invention, the circuit board packaging method includes but is not limited to the following steps:

[0048] S100, welding a stepped carrier on the chip window of the circuit board 400, the stepped carrier comprising a first carrier 300 and a second carrier 200, the first carrier 300 being welded to the chip window, the second carrier 200 being arranged on the first carrier 300, and the first carrier 300 and the second carrier 200 being in an inverted stepped structure;

[0049] Specifically, a variety of components are densely arranged on the circuit board 400 (PCB), including resistors, capacitors, inductors, transistors, etc. When it is necessary to measure the chip 100 to be tested on the circuit board 400, such as using an oscilloscope to measure and analyze the signal of the chip 100 to be tested, due to the high density of components on the circuit board 400, it is difficult to find a suitable test node 210 to put the probe of the oscilloscope, which makes the test troublesome, and the high-density components also interfere with the measured signal, thereby affecting the accuracy of the test. A padding structure is welded at the chip window where the chip 100 to be tested is welded on the circuit board 400, that is, a stepped carrier, so that the chip 100 to be tested is suspended, and the suspended chip 100 is far away from other components on the circuit board 400, and the second carrier 200 of the stepped carrier is larger than the original chip window, and the size of the second carrier 200 can be set according to the needs, so as to facilitate the setting of the corresponding test node 210 on the second carrier 200. The welding window on the second carrier board 200 is used to weld the chip to be tested 100. The chip to be tested 100 is connected in series with the test node 210 and the chip window in sequence through the convex wiring 120. The series test node 210 reduces the signal reflection interference caused by the general pile line design, and compared with the general design of increasing buried resistance, the process is simpler and the production cost is lower.

[0050] S200, setting a welding window in a first area of ​​the second carrier plate 200;

[0051] Specifically, the size of the first area of ​​the second carrier board 200 matches the size of the chip to be tested 100 , and after the welding window is set in the first area, it is convenient to weld the chip to be tested 100 on the welding window.

[0052] In some optional embodiments, the method further includes: hollowing out a plurality of corner structures 220 on the second surface of the second carrier plate 200 according to the size information; and providing the welding windows in the corner structures 220 .

[0053] Specifically, refer to Figure 3 Four corner structures 220 are arranged in the first area of ​​the second carrier 200, and the welding openings are conveniently arranged after positioning by the corner structures 220. The corner structures 220 can also be used for positioning when welding the chip 100 to be tested, thereby ensuring that the welding position of the chip 100 to be tested is accurate.

[0054] In some optional embodiments, the first surface of the first carrier board 300 is welded to the chip window through a first welding point 310, the second surface of the first carrier board 300 and the first surface of the second carrier board 200 are an integrated structure, the second surface of the second carrier board 200 is provided with the first area and the second area, and the chip to be tested 100 is welded to the welding window through a second welding point 110.

[0055] Specifically, the pins of the chip under test 100 are welded to the welding windows to form a plurality of second welding points 110, and the first surface of the first carrier 300 is welded to the chip windows to obtain a plurality of first welding points 310, and the first welding points 310 correspond to the second welding points 110 one by one, thereby ensuring that the pins of the chip under test 100 can be correctly electrically connected to the chip windows on the circuit board 400. The first carrier 300 and the second carrier 200 are an integrated structure, thereby eliminating the welding process of the first carrier 300 and the second carrier 200, which not only reduces the number of welding times and manufacturing costs, but also improves the connection stability between the first carrier 300 and the second carrier 200.

[0056] S300, setting a test node 210 in a second area of ​​the second carrier 200, wherein the first area and the second area are both located on the same surface of the second carrier 200 and do not interfere with each other, wherein the second area and the first area of ​​the second carrier are obtained according to the size of the chip to be tested and the components on the circuit board;

[0057] Specifically, the second area and the first area of ​​the second carrier 200 are determined according to the specific size of the chip 100 to be tested and the components on the circuit board 400, so that the first area can just set the welding window, and the second area can just set the test node 210, and the interference at the test node 210 is small, and the measured signal quality is high.

[0058] S400, disposing a convex wiring 120 between the first carrier board 300 and the second carrier board 200, so that the convex wiring 120 is connected in series with the test node 210 and then electrically connects the chip opening and the welding opening.

[0059] Specifically, the chip under test 100 on the second carrier 200 is electrically connected to the chip window on the circuit board 400 by setting the convex wiring 120, so as to ensure smooth connection after the chip under test 100 is suspended. The convex wiring 120 extends to the area outside the welding window, thereby passing through the test node 210 in the second area, so that the test node 210 is connected in series with the convex wiring 120, which greatly reduces the reflection problem caused by the signal measurement.

[0060] In some optional embodiments, the first solder joint 310 , the test node 210 , and the second solder joint 110 are connected in series via the convex trace 120 , and the first solder joint 310 and the second solder joint 110 correspond to each other one by one.

[0061] Specifically, the convex wiring 120 sequentially connects the first solder joint 310, the test node 210 and the second solder joint 110 in series, and the chip under test 100 can be measured through the test node 210. The pins of the chip under test 100 are soldered to the soldering window through the second solder joint 110, and the first carrier 300 is soldered to the chip window through the first solder joint 310. The first solder joint 310 and the second solder joint 110 are connected one by one through the convex wiring 120 to ensure that the chip under test 100 can be accurately electrically connected to the chip window on the circuit board 400.

[0062] S500, welding the chip to be tested 100 on the welding window.

[0063] Specifically, after the chip 100 to be tested is welded on the welding window, the chip 100 to be tested is raised and suspended in the air, and the suspended chip 100 to be tested can easily set a test node 210 on the second carrier board 200 to test the chip 100. The chip 100 to be tested floats on the upper layer of the circuit board 400, cleverly avoiding the interference of the high-density components on the original circuit board 400.

[0064] In some optional embodiments, the processing method of the first carrier board 300 includes: obtaining the size information of the chip to be tested 100; performing CNC processing on the step carrier board according to the size information to obtain the first carrier board 300, so that the first carrier board 300 and the chip to be tested 100 have a welding surface area of ​​the same size, and the welding surface area represents the surface area of ​​the chip to be tested 100 or the first carrier board 300 and the welding window or the chip window welding.

[0065] Specifically, the surface of the first carrier 300 where it is welded to the chip window needs to be the same size as the chip to be tested 100, so that the first carrier 300 can adapt to the chip window. By obtaining the size information of the chip to be tested 100, the CNC (computer numerical control) processing of the first carrier 300 is completed according to the size information, so that the first carrier 300 has the same size as the chip to be tested 100, that is, it has the same welding surface area as the chip to be tested 100. The specific welding surface area is the surface area of ​​the bottom surface of the chip to be tested 100, that is, the surface area of ​​the bottom surface of the first carrier 300.

[0066] In some optional embodiments, the method further includes: obtaining component information within a first preset range at the chip window; determining height information of the first carrier 300 based on the component information; and performing CNC processing on the step carrier based on the height information to obtain the first carrier 300 having a first height, so that the second carrier 200 on the first carrier 300 does not interfere with the components within the first preset range.

[0067] Specifically, within the first preset range of the chip window, the density of components and the shape of components need to be considered, that is, the component information includes the density, shape, material, power, etc. of the components; if the density of components is high, the interference degree of the components on the chip 100 to be tested is strong, and the first height of the first carrier 300 needs to be appropriately increased; similarly, the larger the shape of the components, such as the height of the components, the first height of the first carrier 300 needs to be increased, thereby raising the second carrier 200, so that the second carrier 200 does not interfere with the components within the first preset range. The specific increase ratio is set according to the operating process and requirements, and is not limited here. In some embodiments, the first height of the first carrier 300 is 1.7mm, the width of the first carrier 300 is 11.5mm, and the length is 13mm.

[0068] In some optional embodiments, the method further includes: determining the side angle of the first carrier 300 according to the component information; and performing CNC processing on the step carrier to obtain the first carrier 300 having the side angle, so that the first carrier 300 does not interfere with the components within the first preset range.

[0069] Specifically, refer to Figure 4 , the shapes of the components around the chip windows are determined according to the component information, and then the side angles of the first carrier 300 are determined according to the shapes of the specific components, so that the sides of the first carrier 300 avoid the components to prevent interference; at the same time, the first carrier 300 can adapt to different chip windows without being affected by the components around the chip windows.

[0070] In some optional embodiments, the processing method of the second carrier board 200 includes: obtaining interference information of each position on the second surface of the second carrier board 200; determining an optimal point with minimal interference based on the interference information; determining a second height of the second carrier board 200 based on the first height; determining an optimal surface area of ​​the second surface of the second carrier board 200 based on the component information and the size information; and performing CNC processing on the stepped carrier board to obtain the second carrier board 200 with the second height and the optimal surface area, so that the second carrier board 200 does not interfere with the components within the first preset range, and the test node 210 is located at the optimal point.

[0071] In some optional embodiments, obtaining the interference information of each position on the second surface of the second carrier 200 includes: determining, according to the component information and the first height, a signal quality measured by the test node 210 after setting the test node 210 at each position on the second surface of the second carrier 200; and determining the interference information according to the signal quality.

[0072] Specifically, by calculating the interference of components on each position on the second surface of the second carrier 200, the point with the least influence on the measurement signal is determined, that is, the optimal point. Specifically, the interference strength of the components is obtained according to the component density, component shape, and component power in the component information, and the signal quality after measurement at each position on the second surface of the second carrier 200 is determined according to the first height, so as to obtain the corresponding interference information, find the optimal point, and use the optimal point as the test node 210. The second height of the second carrier 200 is determined according to the first height, so that the second carrier 200 avoids other components. In some embodiments, the second height is 0.5mm. The position of the second area is obtained by determining the specific interference situation according to the component information, and the required first area is determined according to the size information, so as to determine the optimal surface area of ​​the second surface of the second carrier 200 according to the first area and the second area. After CNC processing of the stepped carrier, a second carrier 200 with a second height and an optimal surface area is obtained.

[0073] The implementation of the embodiment of the present invention includes the following beneficial effects: The embodiment of the present invention provides a circuit board packaging method, including: welding a stepped carrier on a chip window of a circuit board 400, the stepped carrier including a first carrier 300 and a second carrier 200, the first carrier 300 being welded to the chip window, the second carrier 200 being arranged on the first carrier 300, the first carrier 300 and the second carrier 200 being in an inverted stepped structure; a welding window is arranged in a first area of ​​the second carrier 200; a test node 210 is arranged in a second area of ​​the second carrier 200, the first area and the second area are both located on the same surface of the second carrier 200 and do not interfere with each other; a convex trace 120 is arranged between the first carrier 300 and the second carrier 200, so that the convex trace 120 is connected in series with the test node 210 and then electrically connects the chip window and the welding window; and the chip 100 to be tested is welded to the welding window. By adding a stepped carrier board at the position where the chip to be tested 100 is welded on the circuit board 400, the chip to be tested 100 is suspended on the circuit board 400, and the suspended second carrier board 200 is convenient for setting the test node 210. The test node 210 does not affect the densely packed components on the circuit board 400, and is connected in series with the convex trace 120, so that the signal measured through the test node 210 is less subject to reflection interference.

[0074] In a second aspect, an embodiment of the present invention further provides a circuit board manufactured by the above-mentioned circuit board packaging method.

[0075] It can be seen that the contents of the above method embodiments are all applicable to the present circuit board embodiment, the functions specifically implemented by the present circuit board embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0076] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are expected, wherein the order of various operations is changed and the sub-operation described as a part of a larger operation is performed independently.

[0077] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional techniques of the engineer. Therefore, those skilled in the art can implement the present application set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the attached claims and their equivalents.

[0078] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0079] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0080] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A circuit board packaging method, characterized in that: include: Welding a stepped carrier plate on the chip window of the circuit board, the stepped carrier plate comprising a first carrier plate and a second carrier plate, the first carrier plate being welded to the chip window, the second carrier plate being arranged on the first carrier plate, and the first carrier plate and the second carrier plate being in an inverted stepped structure; Disposing a welding window in the first area of ​​the second carrier plate; A test node is set in the second area of ​​the second carrier board, the first area and the second area are both located on the same surface of the second carrier board and do not interfere with each other, wherein the second area and the first area of ​​the second carrier board are obtained according to the size of the chip to be tested and the components on the circuit board; the first surface of the first carrier board is welded to the chip opening through a first welding point, the second surface of the first carrier board and the first surface of the second carrier board are an integrated structure, the second surface of the second carrier board is provided with the first area and the second area, and the chip to be tested is welded to the welding opening through a second welding point; A convex wiring is arranged between the first carrier board and the second carrier board, the first solder joint, the test node and the second solder joint are connected in series through the convex wiring, and the first solder joint and the second solder joint correspond to each other one by one; The chip to be tested is welded on the welding window.

2. The method according to claim 1, characterized in that The processing method of the first carrier plate comprises: Obtaining size information of the chip to be tested; The first carrier is obtained by CNC processing the stepped carrier according to the size information, so that the welding surface area of ​​the first carrier and the chip to be tested is specifically the same size, and the welding surface area represents the surface area of ​​the welding between the chip to be tested or the first carrier and the welding window or the chip window.

3. The method according to claim 2, characterized in that The method further comprises: Acquire component information within a first preset range of the chip window; Determine height information of the first carrier board according to the component information; The first carrier plate having a first height is obtained by CNC processing the stepped carrier plate according to the height information, so that the second carrier plate on the first carrier plate does not interfere with components within the first preset range.

4. The method according to claim 2, characterized in that: The method further comprises: Hollowing out a second surface of the second carrier board according to the size information to obtain a plurality of corner structures; The welding window is arranged in the corner structure.

5. The method according to claim 3, characterized in that: The method further comprises: Determining a side angle of the first carrier board according to the component information; The first carrier plate having the side angle is obtained by CNC processing the stepped carrier plate, so that the first carrier plate and the components within the first preset range do not interfere with each other.

6. The method according to claim 5, characterized in that The processing method of the second carrier plate comprises: Acquiring interference information at various positions on the second surface of the second carrier board; Determining an optimal point with minimal interference according to the interference information; determining a second height of the second carrier plate according to the first height; Determine an optimal surface area of ​​the second surface of the second carrier board according to the component information and the size information; The step carrier is CNC-processed to obtain the second carrier having the second height and the optimal surface area, so that the second carrier does not interfere with components within the first preset range, and the test node is located at the optimal point.

7. The method according to claim 6, characterized in that The obtaining interference information of each position on the second surface of the second carrier board includes: After determining, according to the component information and the first height, the signal quality measured by the test node after the test node is set at each position on the second surface of the second carrier board; The interference information is determined according to the signal quality.

8. A circuit board, characterized in that: It is manufactured by the circuit board packaging method described in any one of claims 1 to 7.

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