Method, device, microprocessor and storage medium for adjusting power-off maintenance time

Abstract

An embodiment of the present application provides a method, device, microprocessor, storage medium electronic device and computer program product for adjusting the power-off maintenance time, wherein the method includes: when it is determined that the power-off maintenance time of a server power supply needs to be adjusted, obtaining the voltage difference between the input power consumption of the server power supply detected by a first detection circuit and the output voltage of a power factor correction electrode circuit of the power supply detected by a second detection circuit; determining the correspondence between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction electrode circuit of the power supply based on the input power consumption and the voltage difference; and adjusting the output capacitance according to the correspondence to adjust the power-off maintenance time of the server power supply to the first power-off maintenance time.

Description

Technical Field

[0001] Embodiments of the present application relate to the computer field, and in particular, to a method, device, microprocessor, storage medium electronic device, and computer program product for adjusting a power-off maintenance time. Background Art

[0002] In the field of server power supply, ensuring power continuity to cope with voltage interruption or sudden drop is a core design challenge. The solution strategies in related technologies mostly rely on hardware enhancement, such as introducing additional boost circuits to maintain output voltage stability. However, this method generally leads to larger power supply size, higher costs, and may reduce overall power density.

[0003] Currently, effective control means are determined in the relevant technology to optimize the power outage maintenance time of the server without adding additional hardware such as a boost circuit. Summary of the invention

[0004] The embodiments of the present application provide a method, device, microprocessor, storage medium electronic device and computer program product for adjusting the power-off maintenance time, so as to at least solve the problems existing in the related art that additional hardware such as a boost circuit is needed to optimize the power-off maintenance time of a server power supply, thereby resulting in an increase in the size of the power supply, an increase in cost and a lower reliability of the server power supply.

[0005] According to an embodiment of the present application, a method for adjusting a power-off maintenance time is provided, which is applied to a microprocessor, wherein the microprocessor is provided with a plurality of pairs of pins, wherein different pairs of pins are connected to detection circuits for performing different detection functions; the method comprises: in the case of determining that the power-off maintenance time of a server power supply needs to be adjusted, obtaining the voltage difference between the input power consumption of the server power supply detected by a first detection circuit and the output voltage of a power factor correction electrode circuit of the power supply detected by a second detection circuit; determining the correspondence between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction electrode circuit of the power supply based on the input power consumption and the voltage difference; and adjusting the output capacitance according to the correspondence to adjust the power-off maintenance time of the server power supply to the first power-off maintenance time.

[0006] In an exemplary embodiment, obtaining the input power consumption of a server power supply detected by a first detection circuit includes: obtaining the output power consumption, the output percentage and the power consumption conversion efficiency of the server power supply detected by the first detection circuit; and determining the input power consumption based on the output power consumption, the output percentage and the conversion efficiency.

[0007] In an exemplary embodiment, determining the input power consumption based on the output power consumption, the output percentage and the conversion efficiency includes: determining the input power consumption Pin by the following formula (1): Pin=Pout×Load / ηFormula (1); wherein Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency.

[0008] In an exemplary embodiment, the method of obtaining the voltage difference of the output voltage of the power factor correction pole circuit of the power supply detected by the second detection circuit includes: obtaining the maximum value of the output voltage of the power factor correction pole circuit of the power supply detected by the second detection circuit, and the minimum value of the voltage used to maintain the power supply output of the server; and determining the difference between the maximum voltage value and the minimum voltage value as the voltage difference.

[0009] In an exemplary embodiment, determining the correspondence between the power-off holding time of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and the voltage difference includes: determining the correspondence between the power-off holding time T_holdup of the server power supply and the output capacitance C_bulk by the following formula (2): T_holdup = C_bulk×ΔV^2 / (2× Pin) Formula (2), wherein ΔV is the voltage difference, and Pin is the input power consumption.

[0010] In an exemplary embodiment, when it is determined that the power-off maintenance time of the server power supply needs to be adjusted, the method further includes: determining the corresponding relationship between the power-off maintenance time of the server power supply and the output voltage of the power factor correction pole circuit of the power supply; adjusting the output voltage of the power factor correction pole circuit of the power supply according to the corresponding relationship to adjust the power-off maintenance time of the server power supply to a second power-off maintenance time.

[0011] In an exemplary embodiment, determining the correspondence between the power-off holding time of the server power supply and the output voltage of the power factor correction pole circuit of the power supply includes: determining the following formula (3) based on the formula (2), wherein the formula (3) is used to indicate the correspondence between the power-off holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction pole circuit of the power supply: T_holdup = C_bulk×(1- C_error) × (Vbulk_high ^2 - Vbulk_low ^2 ) × η / (2× Pout × Load) Formula (3); wherein C_error is the error value of the output capacitor, Vbulk_high is the maximum value of the output voltage of the power factor correction pole circuit of the power supply, and Vbulk_low is the minimum value of the voltage used to maintain the output of the server power supply.

[0012] In an exemplary embodiment, adjusting the output voltage of the power factor correction pole circuit of the power supply according to the corresponding relationship to adjust the power-off maintenance time of the server power supply to a second power-off maintenance time includes: determining a target output voltage, wherein when the output voltage of the power factor correction pole circuit of the power supply is the target output voltage, the power-off maintenance time of the server power supply is maintained at the second power-off maintenance time; based on the current input voltage of the power factor correction pole circuit of the power supply and the corresponding relationship between the input voltage and the output voltage of the power factor correction pole circuit of the power supply, adjusting the duty cycle to adjust the output voltage of the power factor correction pole circuit of the power supply to the target output voltage.

[0013] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: determining the corresponding relationship between the input voltage Vin and the output voltage Vout of the power factor correction circuit of the power supply by the following formula (4): Vout=Vin / (1-D) Formula (4); wherein D is the duty cycle.

[0014] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: acquiring a current input voltage of the power factor correction circuit of the power supply detected by a third detection circuit.

[0015] In an exemplary embodiment, the third detection circuit includes a first resistor and a second resistor, wherein the first end of the first resistor is connected to the input voltage detection end of the power factor correction circuit of the power supply, the second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor, and the second end of the second resistor is grounded.

[0016] In an exemplary embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of the first sub-resistor and the second sub-resistor are both 499 KΩ, and the resistance value of the second resistor is 5.57 KΩ.

[0017] According to another embodiment of the present application, a device for adjusting a power-off maintenance time is provided, which is applied to a microprocessor, wherein the microprocessor is provided with a plurality of pairs of pins, wherein different pairs of pins are connected to detection circuits for performing different detection functions; the device comprises: a first acquisition module, which is used to obtain the input power consumption of the server power supply detected by the first detection circuit and the voltage difference between the output voltage of the power factor correction electrode circuit of the power supply detected by the second detection circuit when it is determined that the power-off maintenance time of the server power supply needs to be adjusted; a first determination module, which is used to determine the corresponding relationship between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction electrode circuit of the power supply based on the input power consumption and the voltage difference; and a first adjustment module, which is used to adjust the output capacitance according to the corresponding relationship, so as to adjust the power-off maintenance time of the server power supply to the first power-off maintenance time.

[0018] According to another embodiment of the present application, a microprocessor is provided, comprising: the above-mentioned device for adjusting the power-off maintenance time.

[0019] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0020] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0021] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0022] Through this application, an effective control method is provided for optimizing the power-off maintenance time of the server power supply when the input voltage is interrupted or suddenly dropped, without introducing an additional boost circuit, and adjusting the output capacitor according to the specific correspondence between the power-off maintenance time and the output capacitor, thereby achieving the adjustment of the power-off maintenance time. Compared with the traditional method that relies on adding additional hardware such as a boost circuit, the present invention significantly reduces costs, saves space, improves the power density of the server power supply, simplifies the maintenance process, and effectively solves the problems existing in the related art that the additional hardware such as a boost circuit is needed to optimize the power-off maintenance time of the server power supply, thereby resulting in an increase in the size of the power supply, an increase in cost, and a low reliability of the server power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of an input voltage interruption waveform in the related art;

[0024] Figure 2 It is a schematic diagram of an input voltage sag waveform in the related art;

[0025] Figure 3 is a hardware structure block diagram of a server device according to a method for adjusting a power failure maintenance time according to an embodiment of the present application;

[0026] Figure 4 is a flow chart of a method for adjusting the power-off maintenance time according to an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of the structure of a server power supply according to an embodiment of the present application;

[0028] Figure 6 is a structural block diagram of a boost circuit of an active power factor correction pole circuit according to an embodiment of the present application;

[0029] Figure 7 is a schematic diagram of the waveform of the inductance effect of the boost circuit according to an embodiment of the present application;

[0030] Figure 8 is a diagram of a power supply PFC circuit and control architecture according to an embodiment of the present application;

[0031] Fig. 9 is a schematic diagram of a PFC output voltage increase process when the input voltage is interrupted or drops suddenly according to an embodiment of the present application;

[0032] Fig.10 is a schematic diagram of an input voltage detection circuit according to an embodiment of the present application;

[0033] Fig.11 It is a structural block diagram of a device for adjusting the power-off maintenance time according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0036] Based on the definition of power quality disturbance defined by IEEE and the waveform, power quality problems can be divided into the following 7 types:

[0037] (1) Transient phenomenon; (2) Interruption; (3) Voltage sag / undervoltage; (4) Voltage swell / overvoltage; (5) Waveform distortion; (6) Voltage fluctuation; (7) Frequency jitter.

[0038] An input interruption is defined as the complete disappearance of the supply voltage or load current. Depending on its duration, interruptions can be classified as transient, temporary, short-term or continuous. Figure 1 The following is a schematic diagram of the input voltage interruption waveform. The duration ranges of various interruption types are as follows:

[0039] Transient interruption 0.5 to 30 cycles;

[0040] Temporary interruption of 30 cycles to 2 seconds;

[0041] Short interruption 2 seconds to 2 minutes;

[0042] The interruption lasts for more than 2 minutes.

[0043] Voltage sag refers to the AC voltage drop at a given frequency (50-60Hz), which returns to normal after a short period of half a cycle to 1 minute. According to the European standard EN50160, the voltage drops below 90% of the standard value and then recovers to above 90%, with a duration of 10ms to 60s. Therefore, a power outage is considered when the voltage drops for more than 1 minute. The voltage is calculated based on the standard value. When the voltage drops from 92% of the standard value to 3%, it is an 11% voltage sag. Figure 2 The waveform of an input voltage sag is shown. The process of the power infrastructure trying to clear a remote fault may cause problems for the end user. If the problem is obvious, it will be seen as an outage. However, for problems that are cleared quickly or recover quickly, it may also appear as a voltage sag.

[0044] Input interruptions or voltage sags are often caused by power system failures, including starting heavy loads (such as starting a large air conditioning unit for the first time) and troubleshooting remote power equipment. Similarly, starting large motors in industrial plants can cause significant voltage drops. Power equipment short circuits, tree growth that touches overhead cables, cable damage, such as power equipment failures during excavation projects. Or due to weather factors, such as overhead cables tripping due to lightning strikes. Whether it is a transient interruption, temporary interruption, short-term interruption or continuous interruption, it can cause damage, damage and downtime to users as small as home users or as large as industrial users. Home or small business computer users may lose important data due to power outages and information corruption.

[0045] Generally, data centers use uninterruptible power supply (UPS) to prevent input interruption or voltage drop. UPS is a device that provides backup AC power to electrical load devices in an uninterrupted manner to maintain normal operation of electrical appliances when the power grid is abnormal (such as power outage, undervoltage, interference or surge (inrush current)). Usually, uninterruptible power supply is used to maintain the uninterrupted execution of critical commercial devices or precision instruments such as computers (especially servers) or switches to prevent computer data loss, telephone communication network interruption or instrument loss of control. If the mains power fails, the UPS will switch to battery power to ensure that the system will not shut down. The conversion time refers to the time required for the UPS to complete the switch to ensure uninterrupted power supply. It also refers to the time required for the UPS to switch the power back to the mains after the problem is solved, which will be completed in 1 AC cycle - half an AC cycle. For example, if the AC power supply rate is 50Hz, 1 / 50Hz ~ 1 / (2 x 50Hz) = 20ms ~ 10ms is required, and if the AC power supply rate is 60Hz, 1 / 60Hz ~ 1 / (2 x 60Hz) = 16ms ~ 8ms is required. Therefore, it is recommended that the UPS switch to battery power supply within 20ms when the system is fully loaded. Therefore, the most stringent standard for the hold-up time of the server power supply during power outage is required to meet 100% load output and maintain 20ms continuously (it should be noted that this duration is used as an example in the present invention. In subsequent applications, the duration can be flexibly set based on actual conditions. For example, the duration can also be set to 30ms, 50ms, etc. based on actual conditions). The present invention provides a server power supply that can maintain the optimal 20ms for the hold-up time during power outage when the input is interrupted or the voltage drops suddenly, when the power supply is working at 75% ~ 100% load. The present invention is described below in conjunction with an embodiment:

[0046] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 3 1 is a hardware structure block diagram of a server device of a method for adjusting the power failure maintenance time in an embodiment of the present application. Figure 3 As shown, the server device may include one or more ( Figure 3 Only one is shown in the figure) a processor 302 (the processor 302 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 304 for storing data, wherein the server device may also include a transmission device 306 and an input / output device 308 for communication functions. It can be understood by those skilled in the art that Figure 3 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 3 More or fewer components as shown, or with Figure 3 Different configurations are shown.

[0047] The memory 304 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for adjusting the power-off maintenance time in the embodiment of the present application. The processor 302 executes various functional applications and data processing by running the computer program stored in the memory 304, that is, to implement the above method. The memory 304 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 304 may further include a memory remotely arranged relative to the processor 302, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0048] The transmission device 306 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 306 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 306 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0049] In this embodiment, a method for adjusting the power-off maintenance time is provided, which can be applied to a microcontroller unit (MCU) configured with multiple pairs of pins, wherein different pairs of pins are connected to detection circuits for performing different detection functions. Figure 4 is a flow chart of a method for adjusting the power-off maintenance time according to an embodiment of the present application. Figure 4 As shown, the process includes the following steps:

[0050] Step S402, when it is determined that the power-off maintenance time of the server power supply needs to be adjusted, obtaining a voltage difference between the input power consumption of the server power supply detected by the first detection circuit and the output voltage of the power factor correction electrode circuit of the power supply detected by the second detection circuit;

[0051] Step S404, determining a corresponding relationship between a power-off maintenance time of the server power supply and an output capacitance of a power factor correction circuit of the power supply based on the input power consumption and the voltage difference;

[0052] Step S406: adjusting the output capacitor according to the corresponding relationship to adjust the power-off maintenance time of the server power supply to a first power-off maintenance time.

[0053] In the above embodiment, the server power supply may also be referred to as a Server PSU (Server Power Supply Unit, server voltage supply). The structure of the power supply may be referred to in the attached Figure 5 (Should Figure 5The circuit diagram may also be referred to as the block diagram of the AC / DC digital power supply unit), wherein multiple pairs of pins are configured in the MCU, and each pair of pins is connected to a specific detection circuit for real-time monitoring of different key parameters of the server power supply. For example, the first detection circuit is responsible for detecting the input power consumption of the server power supply, while the second detection circuit detects the voltage of the power factor correction stage (PFC stage) circuit of the power supply. For example, the second detection circuit can detect the output voltage difference of the PFC stage circuit (also referred to as the PFC circuit) (wherein, the second detection circuit can detect the maximum value of the output voltage of the PFC circuit and the minimum value of the voltage that can maintain the server voltage output, and then determine the voltage difference based on the two). In addition, the MCU can also be connected to other circuits for detecting different parameters, such as connecting a circuit for detecting the input current of the PFC circuit (by detecting the input circuit, a specific current protection operation can be performed, or some specific operations can be performed based on the current detection result, etc.), a circuit for detecting the input voltage of the PFC circuit, etc. The specific circuit type connected can be flexibly set based on actual conditions. By working with these pins and detection circuits, the MCU can quickly identify parameter changes in specific scenarios, such as identifying any changes in input voltage, including interruptions or voltage drops, and accurately measure the impact of these changes on the server power supply.

[0054] In the above embodiments, there are many ways to adjust the output capacitor. For example, multiple capacitor connection branches can be pre-configured, and the specific capacitor branch to be connected can be selected based on the actual situation to achieve the purpose of adjusting the output capacitor. For another example, the energy that the capacitor can provide during the power outage can be indirectly affected by controlling the charge and discharge state of the capacitor, that is, the voltage across the capacitor, thereby extending the power-off maintenance time. The energy storage capacity of the capacitor is proportional to the product of its voltage and capacitance. Therefore, without replacing the capacitor, the capacitor can be charged to a higher voltage before the power outage through software control, which can increase the energy it can provide, thereby extending the maintenance time. For example, when a sudden drop or interruption in the input voltage is detected, the output voltage of the PFC circuit can be adjusted so that the capacitor can store more energy at the moment of power outage, that is, the effect of increasing the capacitor can be simulated by increasing the voltage across the capacitor. The key to this technology is how to accurately judge the occurrence of voltage interruption or sudden drop, and timely adjust the control signal of the PFC circuit to quickly increase the capacitor voltage.

[0055] In the above embodiment, an effective control method is provided for optimizing the power-off maintenance time of the server power supply when the input voltage is interrupted or suddenly dropped, without introducing an additional boost circuit, and adjusting the output capacitor according to the specific correspondence between the power-off maintenance time and the output capacitor, thereby achieving the adjustment of the power-off maintenance time. Compared with the traditional method that relies on adding additional hardware such as a boost circuit, the present invention significantly reduces costs, saves space, improves the power density of the server power supply, simplifies the maintenance process, and effectively solves the problems existing in the related art that the additional hardware such as a boost circuit is required to optimize the power-off maintenance time of the server power supply, thereby resulting in an increase in the size of the power supply, an increase in cost, and a low reliability of the server power supply.

[0056] In an exemplary embodiment, the step of obtaining the input power consumption of the server power supply detected by the first detection circuit includes: obtaining the output power consumption, output percentage and power conversion efficiency of the server power supply detected by the first detection circuit; and determining the input power consumption based on the output power consumption, output percentage and conversion efficiency. In the above embodiment, the input power consumption of the server power supply can be determined based on its output power consumption, output percentage and power conversion efficiency, wherein the output power consumption of the server power supply can be measured by the sum of the products of all DC output voltages and currents provided by it. For example, if the server power supply provides multiple output voltages such as +12V, +5V and +3.3V, then the power consumption (power) of each output is the product of the output voltage and its corresponding current. The total output power consumption (Pout) is the sum of all output powers; the output percentage is used to reflect the ratio between the total output power of the server power supply and the full load power, that is, the ratio of the current actual load to the maximum possible load. This parameter is usually determined by monitoring key performance indicators such as the current CPU utilization, RAM usage, and hard disk activity of the server; the conversion efficiency of the server power supply is to evaluate its ability to convert AC input power consumption into available DC output power consumption.

[0057] In an exemplary embodiment, the input power consumption is determined based on the output power consumption, the output percentage and the conversion efficiency, including: determining the input power consumption Pin by the following formula (1): Pin=Pout×Load / ηFormula (1); wherein Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency. The above embodiment can accurately calculate and determine the output power consumption of the server power supply, thereby achieving the purpose of optimizing power management, improving energy efficiency, and predicting and preventing potential power problems.

[0058] In an exemplary embodiment, the method of obtaining the voltage difference of the output voltage of the power factor correction pole circuit of the power supply detected by the second detection circuit includes: obtaining the maximum value of the output voltage of the power factor correction pole circuit of the power supply detected by the second detection circuit, and the minimum value of the voltage used to maintain the power supply output of the server; and determining the difference between the maximum voltage value and the minimum voltage value as the voltage difference.

[0059] In the above embodiment, the second detection circuit is responsible for monitoring the output voltage of the PFC circuit in the server power supply. Under normal operating conditions, it will continuously monitor and record the voltage peak value across the output capacitor (Bulk Cap) of the PFC circuit, that is, the maximum value of the output voltage. This value reflects the maximum voltage support that the PFC circuit can provide under full load and light load conditions. In addition, in order to ensure that the server power supply can maintain a stable output during power outages, it is necessary to set a minimum voltage maintenance value (or referred to as a minimum voltage value), which is the minimum voltage required for the power supply to maintain the operation of the critical load of the server after the power supply is powered off. The minimum voltage value is usually set based on the minimum output voltage requirement of the server power supply and the power-off maintenance time standard to ensure that the power supply output will not be lower than the voltage threshold for maintaining stable operation of the server under any possible power grid disturbance. The above voltage difference is the difference between the maximum voltage value and the minimum voltage value, and the voltage difference can reflect the energy range that the output capacitor of the PFC circuit can release during power outages.

[0060] In an exemplary embodiment, determining the correspondence between the power-off holding time of the server power supply and the output capacitance of the power factor correction circuit of the power supply based on the input power consumption and the voltage difference includes: determining the correspondence between the power-off holding time T_holdup of the server power supply and the output capacitance C_bulk by the following formula (2): T_holdup = C_bulk×ΔV^2 / (2× Pin) Formula (2), wherein ΔV is the voltage difference, and Pin is the input power consumption. The above formula can accurately calculate the correspondence between the power-off holding time and the output capacitance, and realizes the accurate calculation and optimization adjustment of the power-off holding time of the server power supply, which not only improves the intelligence and reliability of power management, but also optimizes the power supply design, improves the energy efficiency ratio, and simplifies the maintenance process, which is of great significance for improving the stability and business continuity of high-performance servers in complex power environments.

[0061] In an exemplary embodiment, when it is determined that the power-off maintenance time of the server power supply needs to be adjusted, the method further includes: determining the corresponding relationship between the power-off maintenance time of the server power supply and the output voltage of the power factor correction electrode circuit of the power supply; adjusting the output voltage of the power factor correction electrode circuit of the power supply according to the corresponding relationship to adjust the power-off maintenance time of the server power supply to the second power-off maintenance time. In this embodiment, the purpose of the output capacitor of the PFC circuit can be achieved by adjusting the output voltage of the PFC circuit. In addition, on the basis of the aforementioned embodiment of adjusting the power-off maintenance time by adjusting the output capacitor, the power-off maintenance time can be further adjusted by adjusting the output voltage of the PFC circuit. For example, the adjustment of part of the power-off maintenance time can be achieved based on the corresponding relationship between the output capacitor and the power-off maintenance time, and then the adjustment of the remaining maintenance time can be achieved based on the corresponding relationship between the power-off maintenance time and the output voltage. The power-off maintenance time is adjusted to the required value through the above two adjustment operations, for example, adjusted to 20ms, 25ms, 30ms, etc. The above multi-stage adjustment method can more finely control the power-off maintenance time, ensuring that under different load and voltage conditions, the server power supply can achieve the optimal power-off maintenance time to meet the needs of different scenarios.

[0062] In an exemplary embodiment, determining the correspondence between the power-off holding time of the server power supply and the output voltage of the power factor correction pole circuit of the power supply includes: determining the following formula (3) based on the formula (2), wherein the formula (3) is used to indicate the correspondence between the power-off holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction pole circuit of the power supply: T_holdup = C_bulk×(1- C_error) × (Vbulk_high ^2 - Vbulk_low ^2 ) × η / (2× Pout × Load) Formula (3); wherein C_error is the error value of the output capacitor, Vbulk_high is the maximum value of the output voltage of the power factor correction pole circuit of the power supply, and Vbulk_low is the minimum value of the voltage used to maintain the output of the server power supply. In the above embodiment, the aforementioned formula (2) is further optimized to obtain formula (3), in which the error value of the output capacitor of the PFC circuit is comprehensively considered, and the calculation deviation caused by measurement error or other uncertain factors is corrected, so that the energy that the capacitor can store and release during power failure can be more accurately calculated. This is more consistent with the actual capacitor performance and provides a more reliable energy estimation. In addition, the calculation method of the square of the voltage difference (i.e., ΔV^2) is also optimized. In the optimized formula, the relationship between the maximum voltage value and the minimum voltage value of the PFC circuit and the power failure maintenance time is highlighted, making the calculation simpler and more accurate.

[0063] In an exemplary embodiment, the output voltage of the power factor correction pole circuit of the power supply is adjusted according to the corresponding relationship to adjust the power-off maintenance time of the server power supply to the second power-off maintenance time, including: determining a target output voltage, wherein when the output voltage of the power factor correction pole circuit of the power supply is the target output voltage, the power-off maintenance time of the server power supply is maintained at the second power-off maintenance time; based on the current input voltage of the power factor correction pole circuit of the power supply, and the corresponding relationship between the input voltage and the output voltage of the power factor correction pole circuit of the power supply, adjusting the duty cycle to adjust the output voltage of the power factor correction pole circuit of the power supply to the target output voltage. In this embodiment, the input voltage and the output voltage of the PFC circuit also satisfy a certain correlation relationship. Based on the current input voltage, the output voltage can be adjusted to an ideal value by adjusting the duty cycle, wherein the detection of the input voltage can be implemented by the MCU through a specific detection circuit, and the detection of the output voltage can also be implemented by the MCU through a specific detection circuit. The circuit for detecting the output voltage can further verify whether the output voltage has been adjusted to the ideal value.

[0064] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: determining the corresponding relationship between the input voltage Vin and the output voltage Vout of the power factor correction circuit of the power supply by the following formula (4): Vout=Vin / (1-D) Formula (4); wherein D is the duty cycle.

[0065] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: obtaining a current input voltage of the power factor correction circuit of the power supply detected by the third detection circuit. In this embodiment, the structure of the third detection circuit can be flexibly set based on the actual application scenario and the requirements for detection accuracy. The structure of the third detection circuit is exemplarily described below:

[0066] In an exemplary embodiment, the third detection circuit includes a first resistor and a second resistor, wherein the first end of the first resistor is connected to the input voltage detection end of the power factor correction circuit of the power supply, the second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor, and the second end of the second resistor is grounded. In this embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of the first sub-resistor and the second sub-resistor are both 499KΩ, and the resistance value of the second resistor is 5.57 KΩ. It should also be noted that the number of the first resistor and the second resistor can also be other values, for example, the number of the first resistor and the second resistor is both 1, or the number of the first resistor is 1, the number of the second resistor is 2, and so on. In the case where the number of resistors in each part is different, the resistance value of each resistor can also be different, and the specific resistance value can be adjusted based on the actual structure of the detection circuit.

[0067] The present invention is described as a whole below in conjunction with specific embodiments:

[0068] The implementation of the embodiment of the present invention is divided into three parts:

[0069] 1. Determination of the input voltage of the server PSU (Server Power Supply Unit, corresponding to the aforementioned server power supply) power factor correction (PFC) circuit (PFC circuit can also be referred to as PFC for short);

[0070] 2. The increase of the PFC control signal of the Server PSU power factor correction pole;

[0071] 3. Design of the PFC output voltage of the Server PSU power factor correction.

[0072] The following describes each part separately:

[0073] 1. Determination of Server PSU Power Factor Correction Pole Voltage:

[0074] The server PSU power factor correction pole overvoltage determination is implemented in two parts:

[0075] (1) Determine when input voltage interruption and sag occur;

[0076] (2) PFC voltage boost condition when input voltage interruption and sudden drop occur.

[0077] in,

[0078] (1) Determine input voltage interruption and sudden drop:

[0079] In the related technology, the server power supply (Server PSU) will use MCU to complete the converter switch control, fan control, LED (Light Emitting Diode, semiconductor light-emitting device) control, monitoring, protection, communication and other functions in the power supply. In terms of division of labor, MUC is divided into primary side MCU and secondary side MCU.

[0080] Among them, the main functions of the primary side MCU are: 1) Power Factor Correction Circuit (PFC) switch control; 2) AC input voltage and current monitoring and protection; 3) Inrush Current protection switch control; 4) Communication functions such as UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), etc.; 5) FRU (Field Replace Unit) data storage.

[0081] The main functions of the secondary side MCU are: 1) high-efficiency converter (DCDC, Direct Current to Direct Current Converter) switch control; 2) DC output voltage and current monitoring and protection; 3) PSU fan control and over-temperature, 4) communication functions such as UART, SPI, I2C, etc.

[0082] The power factor correction stage (PFC stage) circuit controls the hold time (Hold up time) when the power is cut off for the power input and circuit. There are many electrical products whose power factor is very low due to the characteristics of their internal impedance. In order to improve the power factor of electrical products, a power factor correction circuit must be installed at the power input. However, installing a circuit will inevitably increase the manufacturing cost, and these costs will eventually be passed on to consumers. Therefore, in order to save costs, manufacturers usually focus on low prices and are unwilling to let customers spend more on environmental protection. Most consumers, because they do not understand the importance of power factor correction circuits, only think that building power plants is the only solution to the problem of power shortages. This is a major problem in the power supply of most developing countries.

[0083] The main function of the power factor correction stage (PFC stage) circuit is to make the voltage and current phase the same and make the load close to resistance, so there are many ways to design the circuit. According to the components used, it can be divided into two types: passive and active power factor correctors. Passive power factor correctors can only reach 70% PF value under the best conditions, which is not applicable under strict power factor requirements. If you want to achieve a PF value of more than 85% in the full voltage range (90V~265Vac) and under light and heavy load conditions, an active power factor corrector is a necessary choice. Active power factor correction stage circuits are mostly boost circuit structures (Boost Topology).

[0084] like Figure 6 FIG. 1 is a block diagram of a boost circuit structure of an active power factor correction circuit in an embodiment of the present invention. Figure 7 The figure shows the waveform of the inductor effect of the boost circuit in the embodiment of the present invention, wherein the input voltage requirement is 180V~265Vac, and the DC voltage at point Vd is 255V~375V. The boost circuit increases the output voltage Vo to 415V DC, and the working process is as follows:

[0085] 1. When Q is turned on, the voltage on the inductor VL=Vd. At this time, Vd, L, and Q form a loop, and Vd charges the inductor L. The loop is as follows: Figure 6 As shown by the dotted line in the middle, at this time the inductor current ζL rises along the same slope until Q is cut off, and the working cycle (DT) ends.

[0086] 2. When Q is turned off, the inductor voltage reverses and adds Vd to start discharging to the output terminal through diode D. At this time, capacitor C is in a charged state, and RL maintains the output Vo, where the value of Vo is the value of the input voltage Vd plus the inductor voltage (-VL) (because the inductor voltage is reversed, -VL is positive). The circuit is as follows: Figure 6 As shown by the middle gray line, until Q is turned on again (that is, the (1-D)T time period ends).

[0087] If you want Figure 7 If the boost circuit of the active power factor correction stage circuit has the power factor correction function, the control signal of Q must come from an integrated circuit (PFC IC) with a power factor correction function, and the voltage loop and current loop must be used for feedback control. These signals are fed back to the PFC IC to control the conduction and cutoff of Q, thereby achieving the purpose of current waveform shaping. There are two types of PFC ICs. One is a discontinuous current mode power factor corrector (DCM PFC), which is suitable for power factor correction with lower power requirements. European energy regulations stipulate that power supplies above 70W must be equipped with a PFC circuit, and DCM PFC is generally used below 200W. The other is a continuous current mode power factor corrector (CCM PFC), which is generally used above 200W to several thousand W. The input voltage and output voltage of the power factor correction stage (PFCstage) and feedback control, as well as the control signal of the switch are controlled by the primary side MCU. Such as Figure 8 The power supply PFC circuit and control architecture diagram of the embodiment of the present invention shown in FIG. 1 and the input voltage sag and interruption judgment process can refer to FIG. Fig. 9 ,Should Fig. 9 It is used to demonstrate the PFC output voltage increase process when the input voltage is interrupted or drops suddenly. It is necessary to add judgment logic to the primary side MCU firmware to import and judge when the input voltage is interrupted or drops suddenly, which includes the following steps:

[0088] S902: PFC input voltage detection;

[0089] S904, determine whether the interruption and sudden drop conditions are met (the conditions can be Fig. 9 The conditions shown can also be set to other similar conditions);

[0090] S906, when it is determined that the interruption and sudden drop conditions are met, performing PFC load adjustment;

[0091] S908, executing a PFC output voltage adjustment operation.

[0092] Among them, the interruption conditions include the following: transient interruption of 0.5 to 30 AC cycles; voltage sag refers to the AC voltage drop at a given frequency (50-60Hz), and then returns to normal after a short duration of half a cycle to 1 minute. According to the European standard EN50160, the voltage drops to below 90% of the standard value and then recovers to above 90%, with a duration of 10ms to 60s.

[0093] The design of the hold up time of the PFC circuit when it is powered off is as follows:

[0094] The maintenance time of the PFC circuit when it is powered off is mainly supported by the PFC output capacitor Bulk Cap. Therefore, the power-off maintenance time can be obtained by using the energy conservation theorem capacitor model:

[0095] Pin × ΔT_holdup = 1 / 2 × C_bulk × ΔV^2;

[0096] Therefore, the maintenance time during power failure can be shifted to:

[0097] ΔT_holdup = C_bulk × ΔV^2 / (2×Pin);

[0098] Among them, ΔV^2 is the square of ΔV. In addition, the meanings of each parameter are as follows:

[0099] 1) Pin: Server PSU input power consumption, also equal to Pin = Pout (Server PSU output power consumption) × Load (output fraction %) / η (Server PSU conversion efficiency);

[0100] 2) ΔT_holdup: Hold up time during power outage (i.e., the power outage hold time mentioned above);

[0101] 3) C_bulk: PFC output capacitor Bulk Cap capacitance, C_error is the error value of Bulk Cap capacitance, the maximum is 20%;

[0102] 4) ΔV: The voltage difference from the maximum value to the voltage that can maintain the output can be expressed as:

[0103] Vbulk_high - Vbulk_low;

[0104] Therefore, after substituting the above formula and making appropriate changes, the formula for the hold uptime of the PFC circuit when it is powered off can be obtained:

[0105] ΔT_holdup = C_bulk × (1- C_error) × (Vbulk_high ^2 - Vbulk_low ^2 )× η / (2× Pout × Load).

[0106] For example, for a server with a maximum output of 1600W, according to the PFC output capacitor Bulk Cap capacitance and the operating load range, the maintenance time of the PFC circuit when the power is off is shown in Table 1:

[0107] Table 1

[0108]

[0109] For example, if the full load 100% output needs to last for more than 20ms, the output capacitor must be 1000uF or more to achieve this. The number of manufacturers that can support this design value is limited, which makes design and material selection difficult.

[0110] If the output voltage of the PFC circuit is adjusted from 450V to 290V (these two values ​​are for illustration purposes only. In actual applications, the ideal voltage of PFC and the voltage after the reduction can be set based on actual conditions, for example, the ideal voltage can be set to 480V or 500V, etc.), the power-off maintenance time can also be effectively extended. At this time, the output capacitor should be 810uF with a withstand voltage of 600V, which means that the full load 100% output can reach more than 20ms. There are many manufacturers who can support it without special capacitor values, as shown in Table 2.

[0111] Table 2

[0112]

[0113] (2) Judgment of PFC voltage boost when input voltage is interrupted or drops suddenly:

[0114] When the input voltage drops suddenly, the feedback voltage judgment formula is as follows:

[0115] 1) Input voltage is 0, Vin = 0 for 0.5 to 30 AC cycles.

[0116] 2) Input voltage drops by 90% for 0 to 0.5 AC cycles.

[0117] 3) Input voltage is decreased by 30% for 1 to 3000 AC cycles.

[0118] It should be noted that the above-mentioned judgment methods are only examples. In actual applications, other judgment methods can also be used. For example, the voltage drops by 50% and lasts for 1 to 500 cycles, the voltage drops by 70% and lasts for 1 to 2000 AC cycles, etc. The specific judgment conditions can be set based on actual conditions.

[0119] 2. Server PSU power factor correction (PFC) control signal increase:

[0120] The power factor correction stage (PFC stage) and control signal architecture in the power supply circuit are as follows: Figure 8 As shown, the primary side MCU provides a PWM (pulse width modulation) signal to the main switch Q as a driving signal via the Gate Driver to complete the power factor correction work and output the PFC voltage.

[0121] Therefore, the purpose of controlling the PFC voltage range can be achieved by limiting the duty cycle (D, Duty) of the PFC control signal. The relationship between the PFC voltage (PFC Voltage), the input voltage (Vin) and the duty cycle D is PFC Vout=Vin / (1-D), D < 1 (the duty cycle will be less than 1). That is, for the PFC circuit, when Vin is much smaller than PFC Vout, the circuit needs to provide a larger D to meet the boost requirement. Therefore, the wider the input voltage range, the greater the chip's duty cycle adjustment capability. At this time, if a voltage sag or interruption scenario occurs and the PFC Vout needs to rise to 450V, the duty cycle D limit is set as follows:

[0122] (a) Input voltage is 0, Vin = 0 for 0.5 to 30 AC cycles:

[0123] At this time, Vin is 0, and the PFC output needs to rise to 450V. At this time, the input voltage is 220Vac, that is, the PFC output voltage is 220x1.414 =311, which drops to 290V;

[0124] The duty cycle D increases by 450 = 311 / (1-D) ~ 450 = 290 / (1-D) => At this time, the duty cycle D is 0.3~ 0.35.

[0125] (ii) Input voltage drops by 90% for 0 to 0.5 AC cycles:

[0126] At this time, Vin is 220Vac, which drops by 90% to 22V. The PFC Voltage needs to be increased to 450V:

[0127] The duty cycle D increases by 450 = 22x1.414 / (1-D) => the duty cycle needs to be increased to 0.93.

[0128] (iii) Input voltage drops by 30% for 1 to 3000 AC cycles:

[0129] At this time, Vin is 220Vac, which drops by 30% to 154V. When the PFC Voltage needs to be increased to 450V:

[0130] The duty cycle D is limited to 440 = 154x1.414 / (1-D) => now the duty cycle needs to be increased to 0.52.

[0131] 3. Design of Server PSU Power Factor Correction PFC Output Voltage:

[0132] The core is that the primary side MCU controls the output voltage (V_Bulk) of the power factor correction stage (PFC stage) to be adjusted to 450V. The input voltage detection circuit is as follows Fig.10 As shown, when the Server PSU power factor correction pole PFC output voltage, its feedback voltage judgment formula is as follows:

[0133] Vo = Vref × (R1+R2+R3) / R3;

[0134] Among them, M1 is the primary side MCU;

[0135] Fixed feedback reference voltage Vref = 2.5V;

[0136] The feedback resistor has an accuracy of 1% and is a high withstand voltage resistor;

[0137] The design values ​​of R1, R2, and R3 are as follows:

[0138] According to the formula, the output voltage needs to be stabilized at 450V, Vref is set to 2.5V, R1 and R2 are both 499Kohm, and R3 is 5.57K ohm. For details of the parameters, see Table 3:

[0139] Table 3

[0140]

[0141] Therefore, when the input voltage drops or is interrupted, by placing this firmware function into the primary-side MCU, the server power outage maintenance time can be effectively extended. There is no need for special capacitor values, and there are many manufacturers to choose from. The best 20ms is maintained when the power supply is working at 75% ~ 100% load.

[0142] It should be noted that the application scenarios of the above embodiments are relatively broad. For example, input voltage may drop suddenly due to starting heavy loads (such as starting large air-conditioning equipment) and troubleshooting remote power equipment or starting large motors in industrial plants. In this scenario, the solution described in the embodiments of the present invention can be adopted.

[0143] Through the embodiments of the present application, the following effects can be achieved:

[0144] By placing this firmware function in the primary-side MCU in advance when the input voltage drops or is interrupted, the server power outage maintenance time can be effectively extended without adding any hardware functions with special capacitor values, and the optimal 20ms is maintained when the power supply is working at 75% ~ 100% load.

[0145] It can save maintenance personnel from the trouble of having to go to the computer room on site to troubleshoot problems caused by "sudden input voltage drop or interruption".

[0146] No additional hardware setup or special capacitor values ​​are required; this function can be added to the existing architecture and firmware.

[0147] There is no need to use special technology or new materials, and the threshold for implementation is relatively low.

[0148] A firmware design step is proposed to effectively extend the power outage maintenance time of the power server without adding hardware.

[0149] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0150] In this embodiment, a device for adjusting the power-off maintenance time is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0151] Fig.11is a structural block diagram of a device for adjusting the power-off maintenance time according to an embodiment of the present application, such as Fig.11 As shown, the device is applied to a microprocessor, and the microprocessor is configured with multiple pairs of pins, wherein different pairs of pins are connected to detection circuits for performing different detection functions; including: a first acquisition module 112, which is used to obtain the input power consumption of the server power supply detected by the first detection circuit and the voltage difference of the output voltage of the power factor correction electrode circuit detected by the second detection circuit when it is determined that the power-off maintenance time of the server power supply needs to be adjusted; a first determination module 114, which is used to determine the corresponding relationship between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction electrode circuit based on the input power consumption and the voltage difference; a first adjustment module 116, which is used to adjust the output capacitance according to the corresponding relationship, so as to adjust the power-off maintenance time of the server power supply to the first power-off maintenance time.

[0152] In an exemplary embodiment, the first acquisition module 112 includes: a first acquisition unit, used to obtain the output power consumption, output percentage and power consumption conversion efficiency of the server power supply detected by the first detection circuit; a first determination unit, used to determine the input power consumption based on the output power consumption, the output percentage and the conversion efficiency.

[0153] In an exemplary embodiment, the first determining unit includes: a determining subunit, configured to determine the input power consumption Pin by the following formula (1): Pin=Pout×Load / η Formula (1); wherein Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency.

[0154] In an exemplary embodiment, the first acquisition module 112 includes: a second acquisition unit, used to obtain the maximum output voltage value of the power factor correction pole circuit of the power supply detected by the second detection circuit, and to maintain the minimum voltage value of the server power supply output; a second determination unit, used to determine the difference between the maximum voltage value and the minimum voltage value as the voltage difference.

[0155] In an exemplary embodiment, the first determination module 114 includes: a third determination unit, configured to determine the corresponding relationship between the power-off hold time T_holdup of the server power supply and the output capacitance C_bulk by using the following formula (2): T_holdup = C_bulk×ΔV^2 / (2× Pin) Formula (2); wherein ΔV is the voltage difference, and Pin is the input power consumption.

[0156] In an exemplary embodiment, the device also includes: a second determination module, which is used to determine the correspondence between the power-off maintenance time of the server power supply and the output voltage of the power factor correction pole circuit of the power supply when it is determined that the power-off maintenance time of the server power supply needs to be adjusted; and a second adjustment module, which is used to adjust the output voltage of the power factor correction pole circuit of the power supply according to the correspondence so as to adjust the power-off maintenance time of the server power supply to the second power-off maintenance time.

[0157] In an exemplary embodiment, the second determination module includes: a fourth determination unit, used to determine the following formula (3) based on the formula (2), wherein the formula (3) is used to indicate the corresponding relationship between the power-off maintenance time T_holdup of the server power supply and the output voltage Pout of the power factor correction pole circuit of the power supply: T_holdup = C_bulk×(1- C_error) × (Vbulk_high ^2 - Vbulk_low ^2 ) × η / (2× Pout × Load) Formula (3); wherein C_error is the error value of the output capacitor, Vbulk_high is the maximum value of the output voltage of the power factor correction pole circuit of the power supply, and Vbulk_low is the minimum value of the voltage used to maintain the output of the server power supply.

[0158] In an exemplary embodiment, the second adjustment module includes: a fifth determination unit, used to determine a target output voltage, wherein when the output voltage of the power factor correction pole circuit of the power supply is the target output voltage, the power-off maintenance time of the server power supply is maintained at the second power-off maintenance time; an adjustment unit, used to adjust the duty cycle based on the current input voltage of the power factor correction pole circuit of the power supply and the corresponding relationship between the input voltage and the output voltage of the power factor correction pole circuit of the power supply, so as to adjust the output voltage of the power factor correction pole circuit of the power supply to the target output voltage.

[0159] In an exemplary embodiment, the device further includes: a third determination module, which is used to determine the corresponding relationship between the input voltage Vin and the output voltage Vout of the power factor correction circuit of the power supply by the following formula (4) before adjusting the duty cycle: Vout=Vin / (1-D) Formula (4); wherein D is the duty cycle.

[0160] In an exemplary embodiment, the device further includes: a second acquisition module, configured to acquire a current input voltage of the power factor correction circuit of the power supply detected by a third detection circuit before adjusting the duty cycle.

[0161] In an exemplary embodiment, the third detection circuit includes a first resistor and a second resistor, wherein the first end of the first resistor is connected to the input voltage detection end of the power factor correction circuit of the power supply, the second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor, and the second end of the second resistor is grounded.

[0162] In an exemplary embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of the first sub-resistor and the second sub-resistor are both 499 KΩ, and the resistance value of the second resistor is 5.57 KΩ.

[0163] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0164] An embodiment of the present application further provides a microprocessor MCU, comprising the device for adjusting the power-off maintenance time as described in any one of the above items.

[0165] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0166] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0167] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0168] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0169] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0170] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0171] The embodiments of the present application also provide a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

[0172] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0173] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0174] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for adjusting the power-off maintenance time, characterized in that: Applied in a microprocessor, the microprocessor is configured with multiple pairs of pins, wherein different pairs of pins are connected to detection circuits for performing different detection functions; include: In the case where it is determined that the power-off maintenance time of the server power supply needs to be adjusted, obtaining a voltage difference between the input power consumption of the server power supply detected by the first detection circuit and the output voltage of the power factor correction electrode circuit of the power supply detected by the second detection circuit; Determine the corresponding relationship between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction electrode circuit of the power supply based on the input power consumption and the voltage difference; adjusting the output capacitor according to the corresponding relationship to adjust the power-off maintenance time of the server power supply to a first power-off maintenance time; The method also includes: in case it is determined that the power-off maintenance time of the server power supply needs to be adjusted, determining the corresponding relationship between the power-off maintenance time of the server power supply and the output voltage of the power factor correction pole circuit of the power supply; adjusting the power-off maintenance time of the server power supply to a second power-off maintenance time in the following manner: determining a target output voltage, wherein when the output voltage of the power factor correction pole circuit of the power supply is the target output voltage, the power-off maintenance time of the server power supply is maintained at the second power-off maintenance time; based on the current input voltage of the power factor correction pole circuit of the power supply and the corresponding relationship between the input voltage and the output voltage of the power factor correction pole circuit of the power supply, adjusting the duty cycle to adjust the output voltage of the power factor correction pole circuit of the power supply to the target output voltage.

2. The method according to claim 1, characterized in that The obtaining of the input power consumption of the server power supply detected by the first detection circuit includes: Acquire the output power consumption, output percentage and power consumption conversion efficiency of the server power supply detected by the first detection circuit; The input power consumption is determined based on the output power consumption, the output percentage, and the conversion efficiency.

3. The method according to claim 2, characterized in that The determining the input power consumption based on the output power consumption, the output percentage and the conversion efficiency comprises: The input power consumption Pin is determined by the following formula (1): Pin = Pout × Load / η Formula (1); Wherein, Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency.

4. The method according to claim 1, characterized in that: The step of obtaining the voltage difference of the output voltage of the power factor correction electrode circuit of the power supply detected by the second detection circuit comprises: Obtaining the maximum value of the output voltage of the power factor correction circuit of the power supply detected by the second detection circuit, and the minimum value of the voltage used to maintain the output of the server power supply; The difference between the highest voltage value and the lowest voltage value is determined as the voltage difference.

5. The method according to claim 1 or 4, characterized in that: Determining the correspondence between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction circuit of the power supply based on the input power consumption and the voltage difference includes: The corresponding relationship between the power-off holding time T_holdup of the server power supply and the output capacitor C_bulk is determined by the following formula (2): T_holdup = C_bulk × ΔV^2 / (2 × Pin) Formula (2); Wherein, ΔV is the voltage difference, and Pin is the input power consumption.

6. The method according to claim 5, characterized in that The determining of the correspondence between the power-off maintenance time of the server power supply and the output voltage of the power factor correction electrode circuit of the power supply includes: Based on the formula (2), the following formula (3) is determined, wherein the formula (3) is used to indicate the corresponding relationship between the power-off holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction electrode circuit of the power supply: T_holdup =C_bulk×(1- C_error) × (Vbulk_high ^2 - Vbulk_low ^2 ) × η / (2× Pout × Load) formula (3); Among them, C_error is the error value of the output capacitor, Vbulk_high is the maximum output voltage value of the power factor correction electrode circuit of the power supply, and Vbulk_low is the minimum voltage value used to maintain the output of the server power supply.

7. The method according to claim 1, characterized in that Before adjusting the duty cycle, the method further includes: The corresponding relationship between the input voltage Vin and the output voltage Vout of the power factor correction circuit of the power supply is determined by the following formula (4): Vout = Vin / (1-D) Formula (4); Wherein, D is the duty cycle.

8. The method according to claim 1, characterized in that Before adjusting the duty cycle, the method further includes: The current input voltage of the power factor correction circuit of the power supply detected by the third detection circuit is obtained.

9. The method according to claim 8, characterized in that The third detection circuit includes a first resistor and a second resistor, wherein the first end of the first resistor is connected to the input voltage detection end of the power factor correction circuit of the power supply, the second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor, and the second end of the second resistor is grounded.

10. The method according to claim 9, characterized in that The first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of the first sub-resistor and the second sub-resistor are both 499 KΩ, and the resistance value of the second resistor is 5.57 KΩ.

11. A device for adjusting the power-off maintenance time, characterized in that: Applied in a microprocessor, the microprocessor is configured with multiple pairs of pins, wherein different pairs of pins are connected to detection circuits for performing different detection functions; include: A first acquisition module is used to acquire the voltage difference between the input power consumption of the server power supply detected by the first detection circuit and the output voltage of the power factor correction electrode circuit of the power supply detected by the second detection circuit when it is determined that the power-off maintenance time of the server power supply needs to be adjusted; A first determination module is used to determine the corresponding relationship between the power-off maintenance time of the server power supply and the output capacitance of the power factor correction electrode circuit of the power supply based on the input power consumption and the voltage difference; A first adjustment module, configured to adjust the output capacitor according to the corresponding relationship, so as to adjust the power-off maintenance time of the server power supply to a first power-off maintenance time; The device is also used to perform the following operations: when it is determined that the power-off maintenance time of the server power supply needs to be adjusted, determine the corresponding relationship between the power-off maintenance time of the server power supply and the output voltage of the power factor correction pole circuit of the power supply; adjust the power-off maintenance time of the server power supply to a second power-off maintenance time in the following manner: determine a target output voltage, wherein when the output voltage of the power factor correction pole circuit of the power supply is the target output voltage, the power-off maintenance time of the server power supply is maintained at the second power-off maintenance time; based on the current input voltage of the power factor correction pole circuit of the power supply and the corresponding relationship between the input voltage and the output voltage of the power factor correction pole circuit of the power supply, adjust the duty cycle to adjust the output voltage of the power factor correction pole circuit of the power supply to the target output voltage.

12. A microprocessor, characterized in that: include: The device for adjusting the power-off maintenance time as claimed in claim 11.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 10 when executed by a processor.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 10 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 10 are implemented.

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