A path search method for LSI wiring based on design rules

Abstract

The present invention discloses a path search method for large-scale integrated circuit wiring based on design rules, comprising the steps of: S10, data preprocessing stage: constructing a three-dimensional fast lookup table according to a circuit description file; the three-dimensional fast lookup table is established according to the through holes in the circuit description file to quickly screen whether there is a cutting spacing violation at the current position; S20, wiring stage: in the path search process, establishing an adaptive cutting spacing consideration method, using the adaptive cutting spacing consideration method to consider the cutting spacing in advance, avoiding the cutting spacing violation existing in the path in advance, reducing the final design rule violation, and obtaining the path. The present invention effectively reduces the design rule violation problem and ensures the manufacturability of the chip.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a path search method for large-scale integrated circuit wiring based on design rules. Background Art

[0002] VLSI routing is usually performed in two stages: global and detailed. In the global routing stage, the routing space is divided into a set of regular cells, where a coarse-grained routing solution is generated. It optimizes wire length, number of vias, routability, timing, and other metrics from a global perspective. Detailed routing achieves a global routing solution by considering precise metal shapes and positions. It considers many complex detailed design rules such as parallel run spacing, end-of-line (EOL) spacing, cut spacing, minimum area, etc. The quality of its solution directly affects various final design metrics such as timing, signal integrity, and chip yield. At the same time, its solution space, i.e., a three-dimensional grid graph, is significantly larger than that of global routing. In advanced technology nodes, detailed routing becomes the most complex and time-consuming stage.

[0003] Therefore, design rule violation is one of the important evaluation indicators in detailed wiring. In detailed wiring, whether the wiring network has design rule violations can only be checked after the wiring is completed. In the prior art, most of the work deals with design rules in two aspects: on the one hand, the wiring network is sorted, and the order of wiring has a significant help in reducing design rule violations after the wiring network is completed; on the other hand, after the wiring is completed, the wiring network with design rule violations is torn and rewired, and the design rule violations are reduced after several rounds of tearing and rewiring. After these steps, there are still design rule violations in the wiring network, and design rule violations will affect the manufacturability of the chip. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a path search method for large-scale integrated circuit wiring based on design rules, which effectively reduces the design rule violation problem and ensures the manufacturability of the chip.

[0005] To achieve the above object, the technical solution adopted by the present invention is: a path search method for large-scale integrated circuit wiring based on design rules, comprising the steps of:

[0006] S10, data preprocessing stage: constructing a three-dimensional fast lookup table according to the circuit description file; the three-dimensional fast lookup table is established according to the through holes in the circuit description file to quickly screen whether there is a cutting spacing violation at the current position;

[0007] S20, routing phase: During the path search process, an adaptive cutting spacing consideration method is established. The adaptive cutting spacing consideration method is used to consider the cutting spacing in advance, and the cutting spacing violations in the path are avoided in advance to reduce the final design rule violations and obtain the path.

[0008] Furthermore, in the data preprocessing stage, the circuit description file is read to obtain the through-hole information;

[0009] A three-dimensional quick query table is established according to the through-hole information. The three-dimensional quick query table includes the through-hole rectangular shape and spacing rules, and the maximum value of the two is taken to generate a query table for each through-hole.

[0010] Furthermore, with the current through hole as the origin and the through hole shape plus half of the maximum value of the cutting spacing as the radius, two tables, the top layer and the bottom layer, are generated. When querying, the two tables are used at the same time.

[0011] Furthermore, in the routing stage, the pre-processed data is obtained and a path search algorithm is started to be executed on the grid graph constructed by the circuit description file.

[0012] Furthermore, a path search algorithm is started on the grid graph constructed by the circuit description file, including the steps of:

[0013] S201, all vertices in the grid graph are initialized and enter the priority queue;

[0014] S202, obtain a node, determine whether the node is cross-layer extended and whether the current iteration number iter is greater than K, K=V*30, where V is the number of nodes in the current wiring network; if not, proceed to step S203, if yes, proceed to step S204;

[0015] S203, retain the current node, and then update the current node cost;

[0016] S204: if the current node is a cross-layer extension and the current iteration number iter is greater than K, the established three-dimensional fast query table is called to determine whether the cutting spacing between the current node and the M through holes before the query is in violation of the rules. If there is a violation, the current node is skipped; if there is no violation, the current node is retained;

[0017] The above steps are repeated to iterate all nodes in the queue, starting from the source point with the lowest cost. As the number of iterations increases, the resulting path gets closer to the final path.

[0018] Furthermore, the formula for obtaining M is: M=iter / K.

[0019] The beneficial effects of adopting this technical solution are:

[0020] The method proposed by the present invention can reduce design rule violations, thereby improving the quality of the solution. By generating a three-dimensional fast lookup table, design rule violations can be considered and avoided in advance in the path algorithm, thereby reducing some possible design rule violations. Design rule violation is one of the important indicators of circuit design. It directly affects timing, signal integrity, chip yield, etc. Therefore, design rule violation can improve the efficiency and performance of circuit design.

[0021] The present invention proposes a three-dimensional fast lookup table constructed according to a circuit description file for checking design rule violations, taking into account the rectangular shape of the through hole and the spacing rule, so as to quickly screen out whether there is a cutting spacing violation at the current position.

[0022] The present invention proposes a path search algorithm that takes into account adaptive cutting spacing to avoid potential violations and considers different through-hole shapes on different cutting layers, so as to reduce design rule violations in chip design and improve chip manufacturability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic flow chart of a path search method for large-scale integrated circuit wiring based on design rules of the present invention;

[0024] Figure 2 A schematic diagram of a through hole in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a three-dimensional quick query in an embodiment of the present invention;

[0026] Figure 4 The figure is a flow chart of a method for adaptive cutting spacing consideration according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0028] In this embodiment, see Figure 1 As shown, the present invention proposes a path search method for large-scale integrated circuit wiring based on design rules, comprising the steps of:

[0029] S10, data preprocessing stage: constructing a three-dimensional fast lookup table according to a circuit description file (such as a LEFDEF file); the three-dimensional fast lookup table is established according to the through holes in the circuit description file to quickly screen whether there is a cutting spacing violation at the current position;

[0030] S20, routing phase: During the path search process, an adaptive cutting spacing consideration method is established. The adaptive cutting spacing consideration method is used to consider the cutting spacing in advance, and the cutting spacing violations in the path are avoided in advance to reduce the final design rule violations and obtain the path.

[0031] As an optimization solution of the above embodiment:

[0032] In modern chip design, a multi-layer wiring layer and cutting layer design is usually adopted. The combination of these layers provides higher integration, more optimized signal transmission and lower power consumption. The wiring layer is used to route signals and power lines on the chip. These layers are usually composed of multiple metal layers, each of which can be used to lead out different signal lines or power lines. The cutting layer is usually located between the wiring layers. When it is necessary to go from the current wiring layer to another wiring layer, it is necessary to pass through the cutting layer and use a through hole. In order to meet the design requirements and the limitations of the manufacturing process, a variety of types of through holes are usually provided for selection. The through hole is usually a rectangle and has a shape in both the current wiring layer and the other wiring layer. Figure 2 It is a through hole schematic.

[0033] In the Dijkstra algorithm, each vertex in the wiring grid graph is accessed redundantly. In the algorithm of the present invention, when accessing the vertices across layers, through holes are used and the cutting spacing is judged, which requires considering the rectangular shape of the through holes and the cutting spacing, and making a judgment for each access will generate unacceptable time overhead. Therefore, the present invention proposes a three-dimensional fast lookup table.

[0034] In the data preprocessing stage, the circuit description file (such as LEFDEF file) is read to obtain the through-hole information;

[0035] A three-dimensional quick query table is established based on the through-hole information. The three-dimensional quick query table includes the through-hole rectangular shape and spacing rules. The maximum value of the two is taken to generate a query table for each through-hole to minimize violations.

[0036] With the current through hole as the origin and the through hole shape plus half of the maximum value of the cutting spacing as the radius, the top and bottom tables are generated. When querying, the two tables are used at the same time.

[0037] For example: Figure 3 This is a diagram of a lookup table. When a through hole is used for cross-layer access, the lookup table will quickly determine the violation of the adjacent through hole and quickly feedback. In this case, we use 0 and 1 to indicate whether there is a violation, 0 represents no potential violation, and 1 represents a potential violation. The establishment of a three-dimensional fast lookup table can greatly improve the query speed.

[0038] As an optimization solution of the above embodiment:

[0039] In the routing phase, the preprocessed data is obtained and the path search algorithm is started on the grid graph constructed by the circuit description file.

[0040] The cutting pitch is the distance between two through holes. When a node is extended across layers, it needs to pass through the cutting layer, so it is called the cutting pitch.

[0041] The basic process of the adaptive cutting spacing algorithm is as follows Figure 4 As shown, after the wiring starts, all the data of the current wiring network are initialized first, and the costs of all nodes are updated and entered into the priority queue. Then, all the nodes in the queue are iterated, starting from the source point with the lowest cost.

[0042] The path search algorithm is started on the grid graph constructed by the circuit description file, including the following steps:

[0043] S201, all vertices in the grid graph are initialized and enter the priority queue;

[0044] S202, obtain a node, determine whether the node is cross-layer extended and whether the current iteration number iter is greater than K, K=V*30, where V is the number of nodes in the current wiring network; if not, proceed to step S203, if yes, proceed to step S204;

[0045] S203, retain the current node, and then update the current node cost;

[0046] S204 If the current node is extended across layers and the current iteration number iter is greater than K, the established three-dimensional quick query table is called to determine whether there is a violation in the cutting spacing between the current node and the M through holes before the query. If there is a violation, the current node is skipped; if there is no violation, the current node is retained.

[0047] The above steps are repeated to iterate all nodes in the queue, starting from the source point with the lowest cost. As the number of iterations increases, the resulting path gets closer to the final path.

[0048] By querying the first M through holes, the adaptability of the present invention is reflected in the definition of M, which is defined as M=iter / K; M increases with the number of iterations, because as the number of iterations increases, the obtained path is closer to the final path.

[0049] The present invention proposes to add consideration of cutting spacing rules (the cutting spacing is defined by a LEFDEF file (circuit description file) which specifies the minimum spacing allowed between through-holes on the same wiring network or different wiring networks) to the classic Dijkstra algorithm in the path search algorithm under the guidance of reducing design rule violations, and to improve the final quality of wiring by considering and avoiding the cutting spacing rules in advance in the process of finding the shortest path; at the same time, considering that considering other issues when finding the shortest path may cause a lot of time overhead, a three-dimensional fast lookup table is designed to quickly query cutting spacing violations, so as to quickly improve the quality of detailed wiring solutions, and ultimately obtain a better circuit design.

[0050] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A path search method for large-scale integrated circuit wiring based on design rules, characterized in that: Includes steps: S10, data preprocessing stage: constructing a three-dimensional fast lookup table according to the circuit description file; the three-dimensional fast lookup table is established according to the through holes in the circuit description file to quickly screen whether there is a cutting spacing violation at the current position; In the data preprocessing stage, the circuit description file is read to obtain the through-hole information; a three-dimensional quick query table is established according to the through-hole information, wherein the three-dimensional quick query table includes the through-hole rectangular shape and the spacing rule, and the maximum value of the two is taken to generate a query table for each through-hole; S20, routing stage: in the path search process, an adaptive cutting spacing consideration method is established, and the cutting spacing is considered in advance by using the adaptive cutting spacing consideration method, and the cutting spacing violation existing in the path is avoided in advance, so as to reduce the final design rule violation and obtain the path; In the routing phase, the preprocessed data is obtained and the path search algorithm is started on the grid graph constructed by the circuit description file; The path search algorithm is started on the grid graph constructed by the circuit description file, including the following steps: S201, all vertices in the grid graph are initialized and enter the priority queue; S202, obtain a node, determine whether the node is cross-layer extended and whether the current iteration number iter is greater than K, K=V*30, where V is the number of nodes in the current wiring network; if not, proceed to step S203, if yes, proceed to step S204; S203, retain the current node, and then update the current node cost; S204: If the current node is a cross-layer extension and the current iteration number iter is greater than K, the established three-dimensional fast query table is called to determine whether the cutting spacing between the current node and the M through holes before the query is in violation of the rules. If there is a violation, the current node is skipped. If there is no violation, keep the current node; The above steps are repeated to iterate all nodes in the queue, starting from the source point with the lowest cost. As the number of iterations increases, the resulting path gets closer to the final path.

2. A path search method for LSI wiring based on design rules according to claim 1, characterized in that: With the current through hole as the origin and the through hole shape plus half of the maximum value of the cutting spacing as the radius, the top and bottom tables are generated. When querying, the two tables are used at the same time.

3. The path search method for LSI wiring based on design rules according to claim 1, characterized in that: The formula for obtaining M is: M=iter / K.

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