Advanced package TSV identification alignment packaging method, packaging structure and packaging alignment system

Abstract

The application belongs to the technical field of semiconductor processing, and particularly relates to an advanced packaging TSV identification alignment packaging method, a packaging structure and a packaging alignment system. A TSV window groove structure is processed from the side of a bonding surface to align the position of an identification, the position of the TSV window groove structure of the bonding surface of a wafer is used to identify the alignment identification on the back surface of the wafer, an oxide medium is deposited from the side of the bonding surface, the oxide medium has transparency, the alignment identification can be identified from the bonding surface of the wafer, photoresist is deposited on the surface of the oxide medium, the photoresist after etching is etched and removed, and the wafer and a carrier substrate are aligned according to the alignment identification to complete chip packaging. The method is realized based on a packaging alignment system. The packaging structure and the packaging alignment system can be used for the packaging method. In the photoetching process, the photoresist is coated on the surface of the oxide medium layer, the problem that the photoresist is directly filled into the TSV window groove and the filling depth of the photoresist is too deep and the photoresist cannot be completely cleaned can be solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, specifically to an advanced packaging TSV mark alignment packaging method, packaging structure, and packaging alignment system. Background Technology

[0002] Advanced packaging technology lies between traditional wafer fabrication and packaging manufacturing, shortening interconnect lengths while enabling system reconfiguration between different chips. Advanced packaging technology needs to address the issue of packaging alignment. Packaging alignment systems are a key technology in the semiconductor packaging process, ensuring the precise positioning and alignment of packaged components. Chip alignment technologies typically include optical alignment, electron beam alignment, X-ray alignment, and laser alignment. The development trend of these technologies is to achieve higher alignment accuracy, faster alignment speed, and more layers of alignment.

[0003] 2.5D and 3D packaging technologies are representative of advanced packaging technologies. 3D packaging, also known as stacked chip packaging, involves stacking two or more chips vertically and using through-silicon vias (TSVs) to directly connect the electronic signals of the different chips, achieving shorter connection distances, higher connection strength, smaller and thinner packaging, and higher density. However, during the packaging process, alignment must be considered.

[0004] In advanced packaging technologies, alignment marks enable more efficient package alignment. Alignment marks are key elements in advanced packaging technologies that ensure precise overlay of micro-circuit patterns. Their role is to guarantee the alignment between individual chip components during the packaging process. Their presence has a decisive impact on improving package density, ensuring the accuracy of electrical connections, and the performance of the final product.

[0005] Alignment marks are typically special patterns pre-fabricated on silicon wafers to achieve precise overlay in subsequent photolithography steps. These alignment marks not only need to remain stable during photolithography and be resistant to process damage, but also need to be easy to place on a photomask without affecting the device, and be effectively detected by the alignment optics system to provide maximum signal strength.

[0006] Methods for achieving wafer-level alignment include top-to-bottom alignment (TSA / BSA), infrared transmission alignment (IR), wafer-to-mid alignment (ISA) / face-to-face alignment, and back-to-back alignment. For example... Figures 1 to 3The diagram illustrates the wafer bottom alignment marking process in advanced packaging technology. Advanced packaging technology employs a bonding process followed by back-side thinning. During the subsequent TSV (Thin-Side Vessel) formation process, alignment marks need to be made on the back of the wafer, and a TSV window slot is created on the bonding side facing the back of the wafer. The width of the TSV window slot should be as small as possible; however, to ensure the alignment marks on the back of the wafer can be identified, the size of the TSV window slot can be slightly larger than the alignment marks. The depth of the window slot is typically 5-10 mm. A certain depth is required to identify the markings on the back of the wafer. After trenching, photoresist is deposited on the wafer bonding surface, followed by exposure, drying, and photoresist cleaning to complete the wafer product processing. However, due to the excessive depth and small opening of the TSV window trench, the photoresist deposited at the bottom of the TSV window trench is difficult to clean, easily leading to photoresist (PR) accumulation at the bottom of the window. If the photoresist is not thoroughly cleaned, the residual photoresist may affect the adhesion between the photoresist and the wafer surface, causing photoresist peeling, affecting the stability of subsequent processes and product quality; photoresist and other chemicals may form defects in subsequent processes, and may migrate or diffuse during device operation, affecting the electrical performance of the device, increasing the chip defect rate, and reducing the yield. Summary of the Invention

[0007] The purpose of this invention is to solve one of the above-mentioned technical problems by providing an advanced packaging TSV mark alignment packaging method, packaging structure and packaging system, which solves the technical problem of TSV window slot and alignment mark alignment in advanced packaging technology.

[0008] To achieve the above objectives, some embodiments of the present invention provide the following technical solutions:

[0009] Some embodiments of the present invention provide an advanced packaging TSV identifier alignment packaging method for chip packaging alignment, wherein the chip is integrated on a wafer, the wafer includes a bonding surface and a back surface opposite to the bonding surface, and the packaging method includes the following steps:

[0010] S1: Alignment markings are processed on the back of the wafer;

[0011] S2: Perform a windowing process on the wafer, the windowing process comprising: processing a TSV window slot on the bonding surface of the wafer, the TSV window slot being aligned with the location of the alignment mark on the back of the wafer; the depth of the TSV window slot structure is configured such that the alignment mark on the back of the wafer can be identified from one side of the bonding surface of the wafer.

[0012] S3: Deposit an oxide dielectric layer on one side of the bonding surface of the wafer. The oxide dielectric layer has transparency so that alignment marks on the back side of the wafer can be identified from the bonding surface side of the wafer.

[0013] S4: Deposit a photoresist layer on the surface of the wafer oxide dielectric layer, and perform exposure, development and etching processes. During the development process, the exposed photoresist is removed.

[0014] S5: Provide the substrate to be packaged, adjust the position of the wafer to alignment according to the position of the alignment mark, and complete the chip packaging.

[0015] In some embodiments of the present invention, step S3 includes:

[0016] S31: An oxide dielectric layer is deposited on one side of the bonding surface, the oxide dielectric layer covering the bonding surface and the TSV window groove.

[0017] In some embodiments of the present invention, step S3 includes:

[0018] S32: Perform chemical mechanical polishing on the oxide dielectric layer on the bonding surface and the oxide dielectric layer in the TSV window groove to thin the oxide dielectric layer.

[0019] In some embodiments of the present invention, step S32 includes: performing chemical mechanical polishing on the oxide dielectric layer on the bonding surface and the oxide dielectric layer in the TSV window groove to thin the oxide dielectric layer and reduce the height difference between the oxide dielectric layer on the bonding surface and the oxide dielectric layer in the TSV window groove.

[0020] In some embodiments of the present invention, step S32 includes: performing chemical mechanical polishing on the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove, wherein, under the same polishing time, the polishing rate of the oxide medium layer on the bonding surface is greater than the polishing rate of the oxide medium layer in the TSV window groove.

[0021] In some embodiments of the present invention, the substrate to be packaged is a carrier substrate, a wafer, or a chip.

[0022] In some embodiments of the present invention, in step S32, the oxide dielectric layer on the bonding surface and the oxide dielectric layer in the TSV window groove are subjected to chemical mechanical polishing to thin the oxide dielectric layer. After the thinning process is completed, the surface of the oxide dielectric layer in the TSV window groove is processed into a concave arc shape.

[0023] In some embodiments of the present invention, in step S32, the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove are subjected to chemical mechanical polishing to thin the oxide medium layer. After the thinning process is completed, the oxide medium layer remains on the bonding surface.

[0024] Some embodiments of the present invention further provide a packaging structure for the advanced packaging TSV mark alignment packaging method described above. The packaging structure includes a wafer, the wafer including a bonding surface and a back surface opposite to the bonding surface.

[0025] The back side of the wafer is provided with an alignment mark, and the bonding surface of the wafer is provided with a TSV window slot, the position of which is opposite to the position of the alignment mark;

[0026] An oxide dielectric layer is deposited on the bonding surface of the wafer, the oxide dielectric layer fills the window trench, and the oxide dielectric layer has transparency so that alignment marks on the back side of the wafer can be identified from the bonding surface side of the wafer.

[0027] Some embodiments of the present invention further provide a packaging alignment system for performing the advanced packaging TSV identifier alignment packaging method described above, including:

[0028] Optical system: used to identify alignment marks and acquire their position;

[0029] Actuator: Used to adjust the position between the wafer and the carrier substrate;

[0030] Processor: Used to communicate with the optical system, obtain the position of the alignment mark, and generate control signals for the actuator based on the alignment mark to control and adjust the alignment of the wafer and carrier substrate.

[0031] Compared with the prior art, the beneficial effects of the technical solution of the present invention are as follows:

[0032] 1. By creating TSV window slots on the wafer surface and filling the TSV window slots with an oxide dielectric layer, the oxide dielectric layer does not affect the identification of package alignment marks. During photolithography, applying photoresist to the surface of the oxide dielectric layer can solve the problem of excessive photoresist filling depth and incomplete cleaning caused by directly filling the TSV window slots with photoresist.

[0033] 2. The oxide dielectric layer is subjected to chemical mechanical polishing to form a concave arc-shaped layer surface at the TSV window groove, which facilitates the cleaning of the photoresist after the photoresist layer is deposited.

[0034] 3. Performing chemical mechanical polishing on the oxide dielectric layer leaves residual oxide dielectric layer on the bonding surface, which can save the steps of oxide dielectric layer deposition after photoresist cleaning and before packaging, simplifying the wafer processing steps. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 Schematic diagram of a TSV window slot structure for a wafer;

[0037] Figure 2 This is a schematic diagram of photoresist deposition on the wafer bonding surface in the prior art;

[0038] Figure 3 This is a schematic diagram of photoresist cleaning in the prior art;

[0039] Figure 4 A flowchart of the packaging method according to the first embodiment of the present invention is provided;

[0040] Figure 5 A flowchart of the packaging method according to a second embodiment of the present invention is provided;

[0041] Figure 6 A schematic diagram of the deposition of an oxide dielectric layer in the encapsulation method provided by the present invention;

[0042] Figure 7 A schematic diagram of grinding the oxide dielectric layer in the encapsulation method provided by the present invention;

[0043] Figure 8 This is a schematic diagram of a wafer backside alignment marking structure in one embodiment of the present invention.

[0044] In the above image:

[0045] 1-Wafer substrate;

[0046] 2-TSV window slots;

[0047] 3-Photoresist layer;

[0048] 4-Oxide dielectric layer;

[0049] 501 - Back side of wafer; 502 - Bonding surface;

[0050] 6- Alignment mark. Detailed Implementation

[0051] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0053] Packaging technology is divided into chip-level packaging and wafer-level packaging. Chip-level packaging is a packaging method where the package area is close to or equal to the die area, aiming to maximize the miniaturization of chip size. Wafer-level packaging is an advanced packaging technology that encapsulates the chip while it is still on the wafer. A protective layer can be attached to the top or bottom of the wafer, then the circuitry is connected, and the wafer is diced into individual chips. Wafer-level packaging has advantages such as low cost, short production cycle, and high density.

[0054] The first embodiment of the present invention provides an advanced packaging TSV mark alignment packaging method, which is mainly used for wafer-level packaging.

[0055] Flowchart of encapsulation method Figure 4 and Figure 5 The diagram illustrates two implementation processes of the packaging method provided by this invention. The packaging method addresses the problem of packaging between two wafers, particularly the issue of package alignment.

[0056] refer to Figure 1 , Figures 4 to 7 The packaging method provided by the present invention is described in detail below.

[0057] S1: Alignment mark 6 is processed on the back side of the wafer substrate at 501.

[0058] Wafer bonding alignment marks 6 are a key technology for achieving chip packaging alignment. Alignment marks 6 are special patterns pre-designed on the silicon wafer that can be effectively detected by alignment optical systems. Common forms of alignment marks 6 include cross-shaped and bar-shaped images. (Reference) Figure 8 This is a schematic diagram of one embodiment of the alignment mark 6 on the back of a wafer. In actual applications, the number, size, and arrangement of the alignment marks 6 are all designed according to the packaging alignment requirements.

[0059] S2: A TSV window groove 2 is processed on the wafer bonding surface. The TSV window groove 2 is aligned with the position of the alignment mark 6. The depth of the TSV window groove 2 structure is configured such that the alignment mark 6 can be identified from the position of the TSV window groove 2 on the bonding surface 502 side of the wafer.

[0060] refer to Figure 1 Step S2 is the same as in the prior art. Because the wafer has thickness, a TSV window slot 2 is created at the location of the alignment mark 6 on the back side 501 of the wafer to ensure that the alignment mark 6 can be identified. The width of the TSV window slot 2 should be as small as possible, just enough to clearly identify the alignment mark 6. In the prior art, it is usually made slightly larger than the alignment mark 6 to ensure that the alignment mark 6 can be identified, while not affecting the performance of the wafer product due to an excessively large TSV window slot 2. For example, the depth of the TSV window slot 2 can be 5... Up to 10 .

[0061] It should be noted that the TSV window slot 2 described in this invention is different from the TSV interlayer vias used for interconnection between wafers during the bonding process, and is only used for marking alignment during the packaging process.

[0062] It should be understood that interconnection between chips is achieved through vertical penetrations in the silicon wafer to integrate functions between different chips or layers. Through-Silicon Vias (TSV) technology primarily uses conductive materials such as copper to fill the silicon vias to achieve vertical electrical connections within the silicon wafer. This technology reduces signal transmission delays, lowers capacitance and inductance, thereby enabling low power consumption and high-speed communication within the chip. This differs from the TSV window slot 2 in this invention.

[0063] S3: An oxide dielectric layer 4 is deposited on one side of the wafer bonding surface 502. The oxide dielectric layer 4 has transparency so that the alignment mark 6 on the back side 501 of the wafer can be identified from the direction of the bonding surface 502 of the wafer and from the position of the TSV window slot 2.

[0064] In some embodiments of the present invention, the oxide dielectric layer 4 may be PEOX, TEOS, or NDC. These materials have sufficient transparency and do not affect the performance of the wafer product.

[0065] In some embodiments of the present invention, step S3 specifically includes: S31: depositing an oxide dielectric layer 4 on one side of the wafer bonding surface 502, the oxide dielectric layer 4 covering the wafer bonding surface 502 and the TSV window trench 2.

[0066] For details, please refer to the following: Figure 5As shown, in some embodiments of the present invention, an oxide dielectric layer 4 is deposited on one side of the wafer bonding surface 502 using chemical vapor deposition. While chemical vapor deposition has high deposition efficiency, due to the small diameter of the TSV window trench 2, it is difficult to deposit the oxide dielectric layer 4 only inside the TSV window trench 2. Therefore, the oxide dielectric layer 4 accumulates on the surface of the wafer bonding surface 502 and inside the TSV window trench 2.

[0067] It should be understood that in step S31, the oxide dielectric layer 4 is deposited until the surface of the oxide dielectric layer 4 in the TSV window trench 2 is above the bonding surface 502. This structure, which fills the TSV window trench 2, ensures the cleanliness of the photoresist during subsequent photoresist cleaning after photoresist is deposited on the surface of the oxide dielectric layer 4, and avoids photoresist residue in the TSV window trench 2.

[0068] Because the TSV window trench 2 is relatively deep, during the synchronous deposition of the bonding surface 502 and the TSV window trench 2, a height difference will be generated between the surface of the bonding surface 502 and the surface of the oxide medium layer 4 in the TSV window trench 2. That is, the height of the oxide medium layer 4 on the surface of the bonding surface 502 is greater than the height of the oxide medium layer 4 on the surface of the TSV window trench 2.

[0069] If the oxide dielectric layer 4 in the TSV window trench 2 and the wafer bonding surface 502 is too high, it will affect the performance of the wafer product. Therefore, in this method, the deposited oxide dielectric layer 4 is further processed so that the oxide dielectric layer 4 in the wafer bonding surface 502 and the oxide dielectric layer 4 in the TSV window trench 2 both reach a suitable height.

[0070] The oxide dielectric layer 4 is treated using a chemical mechanical polishing method. In some embodiments of the present invention, step S3 includes:

[0071] S32: Perform chemical mechanical polishing (CMP) on the oxide dielectric layer 4 on the wafer bonding surface 502 and in the TSV window groove 2 to thin the oxide dielectric layer 4. The CMP height can be selected as needed.

[0072] In a preferred embodiment, the oxide dielectric layer on the bonding surface and the oxide dielectric layer in the TSV window groove are subjected to chemical mechanical polishing to thin the oxide dielectric layer and reduce the height difference between the oxide dielectric layer on the bonding surface and the oxide dielectric layer in the TSV window groove.

[0073] It should be understood that the thinning effect of grinding on oxide dielectric layer 4 may vary.

[0074] Ideally, the oxide dielectric layer 4 in the TSV window groove 2 and the oxide dielectric layer 4 on the bonding surface 502 should be ground until they are flush. However, this requires high precision in the chemical mechanical polishing process. Therefore, in practice, a small height difference between the surfaces of the two oxide dielectric layers 4 is desired.

[0075] Because the oxide dielectric layer 4 on the bonding surface 502 is relatively high, more of the oxide dielectric layer 4 on the bonding surface 502 needs to be removed during the grinding process.

[0076] In some embodiments of the present invention, in step S32, the grinding thickness can be controlled by controlling the grinding speed: the oxide medium layer 4 on the bonding surface 502 and the oxide medium layer 4 in the TSV window groove 2 are subjected to chemical mechanical polishing treatment. Under the same grinding time, the grinding rate of the oxide medium layer 4 on the bonding surface is greater than the grinding rate of the oxide medium layer 4 in the TSV window groove.

[0077] In some embodiments of the present invention, in step S32, the grinding thickness can also be controlled by controlling the grinding time: chemical mechanical polishing is performed on the oxide medium layer on the surface of the bonding surface 502 and the oxide medium layer 4 in the TSV window groove. At the same grinding rate, the grinding time of the oxide medium layer 4 on the surface of the bonding surface 502 is greater than the grinding time of the oxide medium layer 4 in the TSV window groove 2.

[0078] Ideally, the oxide dielectric layer 4 in the TSV window trench 2 can be ground until it is flush with the surface of the bonding surface 502, thus ensuring the cleanliness of the photoresist layer during cleaning. However, in actual grinding, grinding the oxide dielectric layer 4 in the TSV window trench 2 until it is flush with the surface of the bonding surface 502 requires high control precision. Therefore, in some embodiments of the present invention, in step S32, the oxide dielectric layer 4 on the surface of the bonding surface 502 and the oxide dielectric layer 4 in the TSV window trench 2 are subjected to chemical mechanical polishing to thin the oxide dielectric layer 4. After the thinning treatment, the distance between the oxide dielectric layer 4 in the TSV window trench 2 and the surface of the bonding surface is 0-5. This height is relatively easy to achieve and is less likely to cause photoresist residue during cleaning.

[0079] In some embodiments of the present invention, in step S32, the oxide dielectric layer 4 on the bonding surface 502 and the oxide dielectric layer 4 in the TSV window groove 2 are subjected to chemical mechanical polishing to thin the oxide dielectric layer 4. After the thinning process, the surface of the oxide dielectric layer 4 in the TSV window groove 2 is processed into a concave arc shape. This arc-shaped structure facilitates the cleaning of the photoresist layer 3 in subsequent steps.

[0080] Ideally, the oxide dielectric layer 4 on the bonding surface 502 can be ground until it is flush with the surface of the bonding surface 502, a technique that is easy to achieve. However, considering that in chip packaging processes, a thin insulating protective layer, i.e., a passivation layer, is usually applied to the wafer surface before chip packaging to protect semiconductor devices from environmental factors and reduce the risk of corrosion, contamination, and electrical leakage. The deposited layer not only serves as an insulating layer to prevent electrical signal interference between metal layers, but also as a protective layer to prevent corrosion from environmental factors such as humidity and dust. Therefore, after exposure and after cleaning the photoresist layer 3, before packaging, oxide layer deposition is required. Based on the above technical requirements and considering process simplification, in some embodiments of the present invention, in step S32, the oxide dielectric layer 4 on the bonding surface 502 and the oxide dielectric layer 4 in the TSV window trench 2 are subjected to chemical mechanical polishing to thin the oxide dielectric layer 4. After the thinning process, the oxide dielectric layer 4 remains on the surface of the bonding surface 502.

[0081] S4: Deposit photoresist layer 3 on the surface of oxide dielectric layer 4, perform exposure and development steps, and remove the etched photoresist.

[0082] A photoresist layer 3 is deposited on the surface of the oxide dielectric layer 4, covering both the oxide dielectric layer 4 on the bonding surface 502 and the oxide dielectric layer 4 in the TSV window trench 2. This step is a process of turning the wafer into photographic paper, preparing it for subsequent exposure. The photoresist layer must be thin and uniform to ensure that high-quality microcircuit patterns can be printed.

[0083] After photoresist is deposited, the wafer can be pre-baked to remove the solvent from the photoresist and improve its adhesion.

[0084] The wafer is placed in a lithography machine, and a mask alignment system is used to ensure that the markings on the wafer align with the pattern on the mask. During exposure, ultraviolet light shines through the mask onto the photoresist, creating areas of light and shadow based on the pattern on the mask. Exposure equipment (such as a stepper lithography machine) projects light through a mask containing the circuit pattern onto the photoresist layer on the wafer. In this process, the light selectively illuminates the photoresist, forming the desired circuit pattern.

[0085] After exposure, development is performed. The development process involves spraying developer onto the wafer, selectively removing hardened or unhardened photoresist portions after exposure. Depending on the type of photoresist used, the developer dissolves the hardened or unhardened areas, thus forming the circuit pattern. Development methods can be categorized as pit development, immersion development, and spray development. The amount of developer used, the uniformity of silicon wafer development, and temperature control are all important factors affecting the development quality.

[0086] After development, the developer and photoresist residue on the wafer surface need to be thoroughly cleaned to prepare for the next exposure or subsequent process steps. During the cleaning of photoresist layer 3, the oxide dielectric layer 4 on the bonding surface 502 can be directly cleaned. Because the depth of the TSV window trench 2 after filling the oxide dielectric layer 4 is small and the opening of the TSV window trench 2 is arc-shaped, the oxide dielectric layer 4 in the TSV window trench 2 is easily cleaned.

[0087] After cleaning, the TSV window slot 2 is restored to its polished state, and a vertical gap is formed between the slot opening of the TSV window slot 2 and the surface of the wafer bonding surface 502, which facilitates photolithography alignment.

[0088] S5: Provide the substrate to be packaged. Adjust the position of the wafer relative to the substrate to be packaged according to the alignment mark 6 until aligned, and complete the chip packaging. After packaging, complete the chip dicing.

[0089] In this embodiment of the invention, the substrate to be packaged can be a carrier substrate, a wafer, or a chip.

[0090] If the packaging substrate is a wafer, two opposite wafers can use the same alignment packaging structure. After packaging is completed, the chip is cut to divide the wafer into individual chips.

[0091] If the packaging substrate is a carrier substrate, the substrate can be made of semiconductor single-crystal materials, such as single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), silicon carbide (SiC), and diamond (C). These materials need to have a high degree of consistency in their crystal structure to ensure the stability and performance of the chip.

[0092] If the packaging substrate is a chip, this technology can be used to help stack multiple chips in the vertical direction.

[0093] Correspondingly, auxiliary alignment marks corresponding to the alignment mark 6 on the back side of the wafer 501 can be set on the packaging substrate. The position of the auxiliary alignment marks corresponds to the alignment mark 6 on the back side of the wafer 501. Multiple sets of corresponding marks can also be designed to facilitate packaging alignment in multiple dimensions.

[0094] The alignment mark 6 on the wafer and the auxiliary alignment mark on the packaging substrate can be the same or different, as long as they can achieve the purpose of matching and positioning each other.

[0095] The optical system identifies the alignment mark on the back of the wafer 501 and the auxiliary mark on the packaging substrate through the position identification of the TSV window slot 2. By adjusting the relative position difference between the alignment mark on the wafer and the auxiliary alignment mark on the packaging substrate, the system completes the chip packaging after the position is aligned.

[0096] The second embodiment of the present invention further provides a packaging structure.

[0097] Some embodiments of the present invention further provide a packaging structure. By using this packaging structure in conjunction with the advanced packaging TSV mark alignment packaging method described in the first embodiment, the problem of chip packaging alignment can be solved without affecting the cleaning residue of photoresist.

[0098] The package structure includes a wafer, which includes a bonding surface 502 and a back surface 501 opposite to the bonding surface 502.

[0099] Alignment marks are provided on the back side of the wafer, and TSV window slots 2 are provided on the bonding surface 502 of the wafer. The position of the TSV window slots 2 is opposite to the position of the alignment marks.

[0100] An oxide dielectric layer 4 is deposited on the bonding surface 502 of the wafer. The oxide dielectric layer 4 fills the TSV window trench 2, and the oxide dielectric layer has transparency so that the alignment mark on the back side 501 of the wafer can be identified from the bonding surface 502 side of the wafer.

[0101] A third embodiment of the present invention further provides a packaging system for performing the advanced packaging TSV identifier alignment packaging method described in the first embodiment above. The packaging system includes:

[0102] Optical system: used to identify alignment marks and acquire the position of alignment marks; the alignment marks mentioned here are alignment marks in a broad sense, including alignment marks 6 on the back of the wafer and auxiliary alignment marks on the packaging substrate.

[0103] Actuator: Used to adjust the position between the wafer and the packaging substrate.

[0104] Processor: Used to communicate with the optical system, obtain the position of the alignment marks, and generate control signals for the actuators based on the alignment marks to control the alignment of the wafer and the package substrate. The processor carries a readable program that can calculate the positional difference between the alignment marks on the back of the wafer and the auxiliary alignment marks, and generate control signals for the actuators based on the positional difference.

[0105] To achieve high-precision alignment, holographic interferometry alignment technology can be employed, utilizing metasurfaces to achieve 3D alignment of millimeter-level distance patterns with deep subwavelength accuracy. By analyzing the far-field light intensity map generated by the light transmitted from the two marks, the offset between the marks can be determined, thereby determining the offset between the workpieces.

[0106] The actuator adjusts the position of the packaging structure according to the control signal, and finally achieves packaging alignment.

[0107] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. It should be noted that any modifications, equivalent substitutions, and improvements made by those skilled in the art within the spirit and principles of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of this patent application should be determined by the scope of the appended claims.

Claims

1. An advanced package TSV mark-alignment packaging method, characterized in that, A packaging alignment method for a chip integrated on a wafer, the wafer comprising a bonding surface and a back surface opposite to the bonding surface, the packaging method comprising the following steps: S1: processing an alignment mark on the back surface of the wafer; S2: processing a window on the wafer, the window processing step comprising: processing a TSV window groove on the bonding surface of the wafer, the TSV window groove being aligned with the position of the alignment mark on the back surface of the wafer; the depth of the TSV window groove structure is configured to enable identification of the alignment mark on the back surface of the wafer from the bonding surface side of the wafer; S3: depositing an oxide medium layer on the bonding surface side of the wafer, the oxide medium layer having transparency to enable identification of the alignment mark on the back surface of the wafer from the bonding surface side of the wafer; S4: depositing a photoresist layer on the surface of the oxide medium layer of the wafer, and performing exposure, development and etching processes, wherein the photoresist layer after exposure is removed during the development process; S5: providing a packaging substrate, processing an auxiliary alignment mark on the packaging substrate, adjusting the position of the wafer relative to the packaging substrate to align the auxiliary alignment mark with the alignment mark according to the position of the alignment mark, and completing the packaging of the chip.

2. The advanced package TSV identification alignment packaging method of claim 1, wherein, The step S3 comprises: S31: depositing an oxide medium layer from the bonding surface side, the oxide medium layer covering the bonding surface and the TSV window groove.

3. The advanced package TSV identification alignment packaging method of claim 2, wherein, The step S3 comprises: S32: performing chemical mechanical polishing on the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove to thin the oxide medium layer.

4. The advanced package TSV identification alignment packaging method of claim 3, wherein, The step S32 comprises: performing chemical mechanical polishing on the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove to thin the oxide medium layer, and reducing the height difference between the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove.

5. The advanced package TSV identification alignment packaging method of claim 4, wherein, The step S32 comprises: performing chemical mechanical polishing on the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove, and the polishing rate of the oxide medium layer on the bonding surface is greater than the polishing rate of the oxide medium layer in the TSV window groove under the same polishing time.

6. The advanced package TSV mark alignment packaging method of claim 4, wherein, The packaging substrate is a carrier substrate, a wafer or a chip.

7. The advanced package TSV mark alignment packaging method of claim 3, wherein, In step S32, the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove are subjected to chemical mechanical polishing to thin the oxide medium layer, and after the thinning process is completed, the surface of the oxide medium layer in the TSV window groove is concave in an arc shape.

8. The advanced package TSV mark alignment packaging method of claim 4 or 5, wherein, In step S32, the oxide medium layer on the bonding surface and the oxide medium layer in the TSV window groove are subjected to chemical mechanical polishing to thin the oxide medium layer, and after the thinning process is completed, the oxide medium layer remains on the bonding surface.

9. A package structure, characterized by, An advanced packaging TSV mark alignment packaging method according to any one of claims 1 to 8, comprising a wafer, the wafer comprising a bonding surface and a back surface opposite to the bonding surface; The back surface of the wafer is provided with an alignment mark, and the bonding surface of the wafer is provided with a TSV window groove, the position of the TSV window groove being opposite to the position of the alignment mark; The bonding surface of the wafer is deposited with an oxide medium layer, the oxide medium layer fills the window slot, and the oxide medium layer has transparency to enable identification of the alignment mark on the back surface of the wafer from the bonding surface side of the wafer.

10. A package alignment system characterized by, The advanced packaging TSV identification alignment packaging method of any one of claims 1 to 8 is executed, comprising: An optical system for identifying the alignment mark and collecting the position of the alignment mark; An execution mechanism for adjusting the position between the wafer and the carrier substrate; A processor for communicating with the optical system, acquiring the position of the alignment mark, calculating the position difference between the alignment mark and the auxiliary alignment mark on the back surface of the wafer, and generating a control signal of the execution mechanism according to the position difference between the alignment mark and the auxiliary alignment mark to control the alignment of the wafer and the carrier substrate.

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