A low power consumption control method for SRAM array

Abstract

The present invention discloses a low-power control method for an SRAM array, and belongs to the field of SOC (System on Chip) on-chip storage technology. Which groups in the SRAM array are used are determined according to the scene requirements; at the same time, a Ret mode monitoring module is configured for each group of SRAM for monitoring and control; for each group of SRAM in use, if the Ret mode monitoring module detects that no new access is initiated after its counter reaches the maximum count value, the group of SRAM is powered off, the SRAM is placed in Ret mode, and the data in the group of SRAM is maintained; when a new access is initiated, the Ret mode monitoring module controls the corresponding SRAM to turn on the power, exit the Ret mode, and then receive read and write operations; each group of SRAM that is not in use is directly placed in the Shutdown mode without entering the Ret mode monitoring module for monitoring and control. The present invention solves the problem of high static (leakage) power consumption in large-scale SRAM storage arrays.

Description

Technical Field

[0001] The invention relates to a low power consumption control method for an SRAM array, in particular to a large-scale SRAM storage array power management solution, belonging to the technical field of SOC (System on Chip) on-chip storage. Background Art

[0002] Memory is a major component of modern digital systems, and its role and status in digital systems are becoming increasingly prominent. SRAM (Static Random Access Memory) is one of the most basic and most important volatile memories. Almost all computer systems use it to store programs and data. CACHE (cache memory) and register stack are key components implemented by SRAM, and their area, speed and power consumption greatly affect the performance of the entire SOC. Limited by the SRAM manufacturing process, the capacity of a single SRAM is usually very limited. SOC requires a large amount of SRAM space, and usually uses multiple groups of SRAM to achieve large space storage. During the operation of the system, usually not all SRAMs are accessed. SRAMs that are not accessed are also leaking electricity, which increases the power consumption of the system.

[0003] SRAM is usually powered by dual rails: VDDA is used to power the SRAM array; VDDP is used to power the logic of the SRAM interface. When SRAM is not being accessed, it can be in three low-power modes: Standby mode: SRAM chip select is invalid, that is, both VDDP and VDDA are not turned off; Retention (hereinafter referred to as Ret) mode: turn off VDDP power supply, and the data stored in the SRAM array can be retained; Shutdown mode: VDDP and VDDA are both turned off. Taking a certain 64KB SRAM as an example, the leakage in Standby mode is 126.8uW; the leakage in Ret mode is 64.46uW; and the leakage in Shutdown mode is 0. In the existing processing methods, SRAM is usually only placed in Standby mode or directly placed in Ret mode when not accessed. Placing SRAM only in Standby mode does not reduce power consumption; if SRAM is directly placed in Ret mode (it takes 10 to 20 clock cycles to exit Ret mode), it will affect the access efficiency of SRAM. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a low power consumption control method for an SRAM array, and to solve the problem of high static (leakage) power consumption in a large-scale SRAM storage array.

[0005] The technical solution of the present invention is: a Ret mode monitoring module, comprising:

[0006] Configure a Ret mode monitoring module for each group of SRAM;

[0007] Determine which SRAMs in the SRAM array are used based on the scenario needs; the SOC system directly puts each unused SRAM group into shutdown mode, and the Ret mode monitoring module does not monitor the SRAM in shutdown mode;

[0008] For each group of SRAM in use, that is, the SRAM that is not in the Shutdown mode, the Ret mode monitoring module monitors and judges it:

[0009] Determine whether the SRAM of this group is allowed to enter Ret mode;

[0010] For the SRAM that is allowed to enter the Ret mode, the counter inside the Ret mode monitoring module is used to count. If the counter does not reach the counting threshold, an external access to the group of SRAM is initiated, and the counter is cleared and counted again; if the counter inside the Ret mode monitoring module reaches the counting threshold and no new access is initiated, the VDDP power supply of the group of SRAM is turned off, that is, the group of SRAM enters the Ret mode, and the data in the group of SRAM is maintained;

[0011] For the SRAM in Ret mode, when a new access is initiated, the Ret mode monitoring module controls the SRAM group to turn on the VDDP power supply, that is, the SRAM group exits the Ret mode, and the SRAM access interface performs read and write operations on the SRAM group again.

[0012] Preferably, the Ret mode monitoring module includes: a Shutdown mode control interface, a Ret mode configuration interface, an SRAM access initiation interface, a Ret threshold setting interface, a Ret mode control output interface, an SRAM operable flag output interface, and a built-in judgment unit;

[0013] The built-in judgment unit judges the signal input from the SRAM access interface to the Ret mode monitoring module, and outputs the control signal to the SRAM and the SRAM access interface through the corresponding output interface according to the set conditions;

[0014] The specific interface functions of the Ret mode monitoring module are:

[0015] Shutdown mode control interface: receives the Shutdown mode control signal input from the SRAM access interface. When the Shutdown mode control signal is 1, the built-in judgment unit waits for a new Shutdown mode control signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 0; when the Shutdown mode control signal is 0, the built-in judgment unit waits for the input signal from the Ret mode configuration interface, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1;

[0016] Ret mode configuration interface: receives the Ret mode configuration signal input from the SRAM access interface. When the Ret mode configuration signal is 1, the built-in judgment unit waits for the new Ret mode configuration signal, and makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; if it is 0, the built-in judgment unit triggers the built-in counter to start counting, and makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1;

[0017] SRAM access initiation interface: receives the SRAM access initiation signal input by the SRAM access interface. When the SRAM access initiation signal is 1, the built-in judgment unit clears the built-in counter count to make the Ret mode control output interface output 0 and the SRAM operable flag output interface output 1; if it is 0, the built-in counter of the built-in judgment unit continues to count. Before the count reaches the threshold: the Ret mode control output interface outputs 0 and the SRAM operable flag output interface outputs 1; after the count reaches the threshold: the Ret mode control output interface outputs 1 and the SRAM operable flag output interface outputs 0;

[0018] Ret threshold setting interface: receives the Ret threshold input by the SRAM access interface;

[0019] Ret mode control output interface: outputs Ret mode control signal to SRAM. When the Ret mode control signal is 1, SRAM enters Ret mode, and when it is 0, SRAM exits Ret mode.

[0020] SRAM operable flag output interface: outputs the SRAM operable flag signal to the SRAM access interface. When the SRAM operable flag signal is 1, the SRAM can accept read and write access operations; when it is 0, the SRAM does not accept read and write access operations.

[0021] Preferably, the Ret mode monitoring module also includes the following interfaces:

[0022] Clock interface: receives the clock signal input from the SRAM access interface for timing alignment;

[0023] Reset interface: Receives the reset signal input from the SRAM access interface and is used to reset the Ret mode monitoring module.

[0024] Preferably, a group of counters is set in each Ret mode monitoring module, and the maximum count value is the Ret threshold.

[0025] Preferably, the SOC system directly sets each unused SRAM group to the Shutdown mode, at which time the SRAM access interface inputs 1 to the Shutdown mode control interface of the corresponding Ret mode monitoring module, and the built-in judgment unit waits for a new Shutdown mode control signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 0;

[0026] For each group of SRAM in use, that is, the SRAM that is not in the Shutdown mode, the SRAM access interface inputs 0 to the Shutdown mode control interface of the corresponding Ret mode monitoring module, and the built-in judgment unit waits for the input signal of the Ret mode configuration interface, and at the same time makes the Ret mode control output interface output 0 and the SRAM operable flag output interface output 1.

[0027] Preferably, when the SRAM access interface inputs 0 to the corresponding Shutdown mode control interface of the Ret mode monitoring module:

[0028] If the SRAM access interface of a group of SRAM inputs 1 to the Ret mode configuration interface of the corresponding Ret mode monitoring module, the SRAM of this group is not allowed to enter the Ret mode, and the built-in judgment unit waits for the new Ret mode configuration signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1;

[0029] If the SRAM access interface of a certain group of SRAM inputs 0 to the Ret mode configuration interface of the corresponding Ret mode monitoring module, the Ret mode monitoring module of the group enters the Ret mode dynamic monitoring state to determine whether the group of SRAM enters the Ret mode.

[0030] Preferably, in the dynamic monitoring state of Ret mode, when no external access is initiated to the group of SRAM, the counter of the Ret mode monitoring module starts counting, and the built-in judgment unit waits for a new Ret mode configuration signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; if an external read or write access to the SRAM is initiated when the count has not reached the set Ret threshold, that is, when the SRAM access interface inputs 1 to the SRAM access initiation interface of the Ret mode monitoring module, the counter is cleared, and after the access ends, when the SRAM access interface inputs 0 to the SRAM access initiation interface of the Ret mode monitoring module, the counter restarts counting, so that the group of SRAM does not temporarily enter the Ret mode; before the counter count reaches the threshold, the built-in judgment unit makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1.

[0031] Preferably, in the dynamic monitoring state of Ret mode, when no access is initiated to the group of SRAM, the counter of the Ret mode monitoring module starts counting, and when the counter count reaches the Ret threshold, there is still no new read and write access initiated to the group of SRAM, that is, after the counter count reaches the Ret threshold, the input of the group of SRAM access interface to the SRAM access initiation interface of the Ret mode monitoring module is always 0:

[0032] The built-in judgment unit of the Ret mode monitoring module sets the Ret mode control output interface to 1 and outputs it to the SRAM, turning off the VDDP power supply of the SRAM, that is, the group of SRAM enters the Ret mode; at the same time, the built-in judgment unit of the Ret mode monitoring module sets the SRAM operable flag output interface to 0, indicating that the group of SRAM does not accept read and write access operations.

[0033] Preferably, after the group of SRAM enters the Ret mode, when a new read / write access to the group of SRAM is initiated externally, that is, when the SRAM access interface inputs 1 to the SRAM access initiation interface:

[0034] If the output of the SRAM operable flag output interface of the Ret mode monitoring module to the SRAM access interface is 0, the SRAM access interface does not immediately perform read and write access operations on the SRAM, that is, the internal address calculation unit does not work, and at the same time, the built-in judgment unit of the Ret mode monitoring module sets the corresponding Ret mode control output interface to 0, turns on the VDDP power supply of the SRAM, that is, the SRAM exits the Ret mode, and at the same time, the built-in judgment unit of the Ret mode monitoring module sets the output of the SRAM operable flag output interface to the SRAM access interface to 1;

[0035] If the output of the corresponding SRAM operable flag output interface to the SRAM access interface is 1, indicating that the SRAM has exited the Ret mode, the external device can perform read and write access operations on the SRAM through the SRAM access interface.

[0036] Preferably, the Ret threshold is obtained by simulation, and the simulation process is specifically as follows:

[0037] Determine bandwidth requirements for work scenarios;

[0038] The Ret threshold is dynamically modified from high to low, and the minimum value corresponding to the performance requirement is selected as the optimal Ret threshold, and the power consumption is also the minimum at this time.

[0039] Compared with the prior art, the present invention has the following advantages:

[0040] (1) The present invention designs a Ret mode monitoring module to configure the unaccessed SRAM to the Shutdown mode, thereby further saving power consumption;

[0041] (2) The present invention uses a Ret mode monitoring module to put an SRAM that has not been accessed for a long time into Ret mode. At the same time, the Ret threshold in the design is configurable. The dynamic Ret threshold can be specified according to the characteristics of peripheral access, which can reduce the access efficiency loss caused by entering the Ret mode immediately after the access is completed, and solve the problem of high static (leakage) power consumption in large-scale SRAM storage arrays;

[0042] (3) The Ret mode monitoring module of the present invention is a parameterized design, and the number of groups of dynamic monitoring modules can be specified as needed, which is more flexible when used in an instantiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a schematic diagram of the interface design of the Ret mode monitoring module (ret_monitor) of the present invention;

[0044] Figure 2 Schematic diagram of an SRAM storage array with a Ret mode monitoring module (ret_monitor) according to the present invention. DETAILED DESCRIPTION

[0045] The technical solution of the present invention is:

[0046] Design a Ret mode monitoring module for each bank of SRAM, namely the ret_monitor module, to monitor and set the state of the SRAM when it is not being accessed:

[0047] (1) Among the three low power modes, the Standby mode has the most leakage compared to the Shutdown mode and Ret mode, so it is not considered to be set to the Standby mode.

[0048] (2) For unused SRAM, the shutdown mode is directly set, that is, the Ret mode will not be entered.

[0049] (3) Each Ret mode monitoring module sets a group of counters (cnt_i), and the maximum count value (Ret threshold, ret_per) can be configured by the user. If no new access is initiated after the maximum count value is reached, the corresponding Ret mode monitoring module will power off the SRAM (even if the SRAM is placed in Ret mode by the ret_monitor module, the data in the SRAM can be retained); when a new access is initiated, the Ret mode monitoring module first turns on the SRAM power supply, and the SRAM receives the read and write operations from the SRAM access interface.

[0050] The design of the ret_monitor (Ret mode monitoring) module is as follows Figure 1 As shown, Figure 2 Figure 2. SRAM memory array diagram with ret_monitor (Ret mode monitoring) module.

[0051] A Ret mode monitoring module, comprising: a clock interface, a reset interface, a Shutdown mode control interface, a Ret mode configuration interface, an SRAM access initiation interface, a Ret threshold setting interface, a Ret mode control output interface, an SRAM operable flag output interface, and a built-in judgment unit of the Ret mode monitoring module, wherein the built-in judgment unit of the Ret mode monitoring module judges information input to the Ret mode monitoring module by the SRAM access interface, outputs control information to the SRAM through the corresponding output interface according to set conditions so as to make the corresponding SRAM enter or exit the Ret mode, and is used for the SRAM access interface (SRAM_ACCESS_PORT) to judge whether the SRAM can accept read and write access operations;

[0052] The specific interface functions of the Ret mode monitoring module are:

[0053] Clock interface clk: controls the SRAM access interface to input clock signals to the Ret mode monitoring module for timing alignment;

[0054] Reset interface: controls the SRAM access interface to input a reset signal to the Ret mode monitoring module, so as to reset the Ret mode monitoring module.

[0055] Shutdown mode control interface: receives the Shutdown mode control signal input from the SRAM access interface to the Ret mode monitoring module. When the Shutdown mode control signal is 1, it indicates that the SRAM is in the Shutdown mode, and the Ret mode monitoring module does not monitor it. The built-in judgment unit waits for a new Shutdown mode control signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 0; when it is 0, the SRAM is in the normal working mode, and the Ret mode monitoring module monitors it. The built-in judgment unit waits for the input information of the Ret mode configuration interface, and the Ret mode control output interface outputs 0, and the SRAM operable flag output interface outputs 1;

[0056] Ret mode configuration interface: receives the Ret mode configuration signal input from the SRAM access interface to the Ret mode monitoring module, which is used to indicate whether the SRAM is allowed to be configured to enter the Ret mode. If it is 1, the group of SRAM is not allowed to enter the Ret mode, the built-in judgment unit waits for a new Ret mode configuration signal, the Ret mode control output interface outputs 0, and the SRAM operable flag output interface outputs 1; if it is 0, the group of SRAM can be allowed to enter the Ret mode, the built-in judgment unit triggers the built-in counter to start counting, the Ret mode control output interface outputs 0, and the SRAM operable flag output interface outputs 1;

[0057] SRAM access initiation interface: receives the SRAM access initiation signal input from the SRAM access interface to the Ret mode monitoring module, which is used to indicate whether to initiate read and write access to the SRAM. If it is 1, it indicates that read and write access to the SRAM is currently initiated, the built-in judgment unit clears the built-in counter count, the Ret mode control output interface outputs 0, and the SRAM operable flag output interface outputs 1; if it is 0, it indicates that read and write access to the SRAM is not currently initiated, and the built-in counter of the built-in judgment unit continues to count. Before the count reaches the threshold: the Ret mode control output interface outputs 0, and the SRAM operable flag output interface outputs 1; after the count reaches the threshold: the Ret mode control output interface outputs 1, and the SRAM operable flag output interface outputs 0;

[0058] Ret threshold setting interface: The receiving SRAM access interface inputs the Ret threshold to the Ret mode monitoring module, indicating that if there is no access initiation after the last access initiation operation interval Ret threshold count times, the group of SRAM enters the Ret mode;

[0059] Ret mode control output interface: The Ret mode monitoring module outputs the Ret mode control signal to the SRAM. When the Ret mode control signal is 1, the SRAM enters the Ret mode, and when it is 0, it exits the Ret mode.

[0060] SRAM operable flag output interface: The Ret mode monitoring module outputs an SRAM operable flag signal to the SRAM access interface, which is used by the SRAM access interface to determine whether the SRAM can accept read and write access operations. A value of 1 indicates that it can be accepted; a value of 0 indicates that it cannot be accepted.

[0061] Figure 1 The Ret mode monitoring (ret_monitor) module interface is shown in Table 1:

[0062] Table 1 ret_monitor (Ret mode monitoring) module interface table

[0063] Interface Name direction Bit width Signal Description Connection relationship Clock interface clk I 1 Clock, used for timing synchronization SRAM access port (SRAM_ACCESS_PORT) Reset interface rstn I 1 Reset the Ret mode monitoring module SRAM access port (SRAM_ACCESS_PORT) Shutdown mode control interface sd_ctrl I bank_num Shutdown mode control. When configured as 1, the SRAM of this group is in shutdown mode. When configured as 0, the SRAM of this group is in normal working mode. SRAM access port (SRAM_ACCESS_PORT) Ret mode configuration interface ret_mask I bank_num Used to configure whether to allow SRAM to enter Ret mode. If it is 1, the SRAM group is not allowed to enter Ret mode. If it is 0, the SRAM group enters Ret mode according to the configured time. SRAM access port (SRAM_ACCESS_PORT) SRAM access initiation interface sram_bank_sel I bank_num Used to indicate whether to initiate read and write access to SRAM. 1 indicates that read and write access to SRAM is currently initiated, and 0 indicates that read and write access to SRAM is not currently initiated. SRAM access port (SRAM_ACCESS_PORT) Ret threshold setting interface ret_per I p Ret threshold (ret_per_num). If there is no access after ret_per_num cycles since the last access operation, the SRAM of this group can enter Ret mode; it can be configured by the user SRAM access port (SRAM_ACCESS_PORT) Ret mode control output interface ret_ctrl O bank_num Ret mode control. When it is 1 (high level), SRAM enters Ret mode, and when it is 0 (low level), it exits Ret mode. SRAM SRAM operable flag output interface op_ready O bank_num SRAM operable flag, determines whether SRAM can accept access, 1 means it can be accepted; 0 means it cannot be accepted SRAM access port (SRAM_ACCESS_PORT)

[0064] The working process of the ret_monitor (Ret mode monitoring) module:

[0065] (1) According to the scenario requirements, decide which banks of SRAM in the SRAM array to use. The SOC system directly configures the unused SRAM to shutdown mode (that is, sd_ctrl is configured to 1). SRAM in the SOC system is usually designed for maximum access performance. For example, some monitoring SOCs have a maximum access capacity of 8M 60 frames (the SRAM space required in the chip is 16MB). When the chip is used in a scenario of 4M 30 frames (the maximum SRAM requirement is 8MB), the extra 8MB SRAM can be configured to shutdown mode;

[0066] (2) For the SRAM in use (i.e., sd_ctrl is configured to 0), if the ret_mask bit of the Ret mode configuration interface of the Ret mode monitoring module corresponding to a bank is 1, the SRAM of the bank is not allowed to enter the Ret mode;

[0067] (3) For the SRAM in use (i.e., sd_ctrl is configured to 0), if the ret_mask bit of the Ret mode configuration interface of the Ret mode monitoring module corresponding to a bank is 0, the Ret mode monitoring module of the group enters the Ret mode dynamic monitoring state, and the SRAM of the group determines whether to enter the Ret mode based on the result of the Ret mode dynamic monitoring state. In the Ret mode dynamic monitoring state, the specific process is as follows:

[0068] a) When there is no read or write access initiated to the SRAM of the bank (the SRAM access initiation interface sram_bank_sel of the Ret mode monitoring module is 0), the counter cnt_i of the Ret mode monitoring module starts counting. If a new read or write access is initiated to the bank (i.e. sram_bank_sel is 1) before the software-set Ret threshold ret_per_num is reached, the counter cnt_i is cleared to 0. After the access ends (when sram_bank_sel is 0), the counter cnt_i starts counting again.

[0069] b) When no read or write access is initiated to the SRAM of the bank (sram_bank_sel is 0), the counter cnt_i of the Ret mode monitoring module starts counting. When cnt_i reaches the Ret threshold ret_per_num, and there is still no new read or write access initiated to the SRAM group, that is, sram_bank_sel is always 0, the Ret mode monitoring module sets the corresponding Ret mode control output interface ret_ctrl to 1, that is, turns off the VDDP power supply of the SRAM, indicating that the SRAM enters the Ret mode, and the Ret mode monitoring module sets the SRAM operational flag output interface op_ready to 0;

[0070] c) After the SRAM enters the Ret mode, when a new access to the bank is initiated from the outside, if the Ret mode monitoring module sets the SRAM operable flag output interface op_ready to 0, the internal address calculation unit of the SRAM access interface (SRAM_ACCESS_PORT) will not work, and the Ret mode control output interface ret_ctrl will be set to 0, the SRAM VDDP power supply will be turned on, and the SRAM will exit the Ret mode. At the same time, the Ret mode monitoring module sets the SRAM operable flag output interface op_ready to 1. If the corresponding op_ready is 1, indicating that the SRAM has exited the Ret mode, the SRAM access interface can perform read and write access operations on the SRAM. (There will be no situation where the SRAM is in Ret mode and the corresponding SRAM operable flag output interface op_ready is 1)

[0071] The Ret threshold ret_per_num can be obtained through simulation, the specific steps are:

[0072] a) Determine the bandwidth requirements for the work scenario;

[0073] b) Dynamically modify the Ret threshold (from high to low). When the performance requirements are met, the corresponding minimum value is the optimal threshold, and the power consumption is also the lowest. Example

[0074] A 16 SRAM array system design example:

[0075] The SRAM substrate is 4096x128b (64KB), and every 16 groups of SRAM form a storage bank (4096x128x16) with a total capacity of 1MB, for a total of 16 groups. Among them, 8MB of SRAM is not accessed SRAM, and at most 2 groups of SRAM are accessed at the same time. The power consumption of a single block of SRAM (64KB) in 3 modes is: Standby mode (126.8uW), Ret mode (64.46uW), Shutdown mode (0). In a certain scenario, the maximum performance requirement is 100MB / s (the optimal Ret threshold is 1024), and the SRAM power consumption (relative to Standby mode) is calculated as follows:

[0076] (1) 8MB SRAM can be in shutdown mode, saving 8x16x126.8uW=16.23mW;

[0077] (2) For the 8MB SRAM used, the dynamic Ret mode is turned on. Since at most 2 groups of SRAM are accessed at the same time, at most 6 groups of SRAM power can be turned off, which can save 6x16 (126.8-64.46) = 5.98mW;

[0078] Total savings: 16.23mW+5.98mW=22.21mW;

[0079] (3) For continuous access operations, the Ret threshold ret_per can be set to avoid frequent entry into Ret mode and shorten access delay.

[0080] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. A low power consumption control method for an SRAM array, characterized in that include: Configure a Ret mode monitoring module for each group of SRAM; Determine which SRAM in the SRAM array is used based on scenario needs; The SOC system directly puts each unused SRAM group into shutdown mode, and the Ret mode monitoring module does not monitor the SRAM in shutdown mode; For each group of SRAM in use, that is, the SRAM that is not in the Shutdown mode, the Ret mode monitoring module monitors and judges it: Determine whether the SRAM of this group is allowed to enter Ret mode; For the SRAM that is allowed to enter the Ret mode, the counter inside the Ret mode monitoring module is used to count. If the counter does not reach the counting threshold, an external access to the group of SRAM is initiated, and the counter is cleared and counted again; if the counter inside the Ret mode monitoring module reaches the counting threshold and no new access is initiated, the VDDP power supply of the group of SRAM is turned off, that is, the group of SRAM enters the Ret mode, and the data in the group of SRAM is maintained; For the SRAM in Ret mode, when a new access is initiated, the Ret mode monitoring module controls the SRAM to turn on the VDDP power supply, that is, the SRAM exits the Ret mode, and the SRAM access interface performs read and write operations on the SRAM again; The Ret mode monitoring module includes: a Shutdown mode control interface, a Ret mode configuration interface, an SRAM access initiation interface, a Ret threshold setting interface, a Ret mode control output interface, an SRAM operable flag output interface, and a built-in judgment unit; The built-in judgment unit judges the signal input from the SRAM access interface to the Ret mode monitoring module, and outputs the control signal to the SRAM and the SRAM access interface through the corresponding output interface according to the set conditions; The specific interface functions of the Ret mode monitoring module are: Shutdown mode control interface: receives the Shutdown mode control signal input from the SRAM access interface. When the Shutdown mode control signal is 1, the built-in judgment unit waits for a new Shutdown mode control signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 0; when the Shutdown mode control signal is 0, the built-in judgment unit waits for the input signal from the Ret mode configuration interface, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; Ret mode configuration interface: receives the Ret mode configuration signal input from the SRAM access interface. When the Ret mode configuration signal is 1, the built-in judgment unit waits for the new Ret mode configuration signal, and makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; if it is 0, the built-in judgment unit triggers the built-in counter to start counting, and makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; SRAM access initiation interface: receives the SRAM access initiation signal input by the SRAM access interface. When the SRAM access initiation signal is 1, the built-in judgment unit clears the built-in counter count to make the Ret mode control output interface output 0 and the SRAM operable flag output interface output 1; if it is 0, the built-in counter of the built-in judgment unit continues to count. Before the count reaches the threshold: the Ret mode control output interface outputs 0 and the SRAM operable flag output interface outputs 1; after the count reaches the threshold: the Ret mode control output interface outputs 1 and the SRAM operable flag output interface outputs 0; Ret threshold setting interface: receives the Ret threshold input by the SRAM access interface; Ret mode control output interface: outputs Ret mode control signal to SRAM. When the Ret mode control signal is 1, SRAM enters Ret mode, and when it is 0, SRAM exits Ret mode. SRAM operable flag output interface: outputs the SRAM operable flag signal to the SRAM access interface. When the SRAM operable flag signal is 1, the SRAM can accept read and write access operations; when it is 0, the SRAM does not accept read and write access operations.

2. The SRAM array low power consumption control method according to claim 1, characterized in that: The Ret mode monitoring module also includes the following interfaces: Clock interface: receives the clock signal input from the SRAM access interface for timing alignment; Reset interface: Receives the reset signal input from the SRAM access interface and is used to reset the Ret mode monitoring module.

3. The SRAM array low power consumption control method according to claim 1, characterized in that: A group of counters is set in each Ret mode monitoring module, and the maximum count value is the Ret threshold.

4. The SRAM array low power consumption control method according to claim 1, characterized in that: The SOC system directly sets each unused SRAM group to the Shutdown mode. At this time, the SRAM access interface inputs 1 to the Shutdown mode control interface of the corresponding Ret mode monitoring module, and the built-in judgment unit waits for the new Shutdown mode control signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 0; For each group of SRAM in use, that is, the SRAM that is not in the Shutdown mode, the SRAM access interface inputs 0 to the Shutdown mode control interface of the corresponding Ret mode monitoring module, and the built-in judgment unit waits for the input signal of the Ret mode configuration interface, and at the same time makes the Ret mode control output interface output 0 and the SRAM operable flag output interface output 1.

5. The SRAM array low power consumption control method according to claim 4, characterized in that: When the SRAM access interface inputs 0 to the corresponding Shutdown mode control interface of the Ret mode monitoring module: If the SRAM access interface of a group of SRAM inputs 1 to the Ret mode configuration interface of the corresponding Ret mode monitoring module, the SRAM of this group is not allowed to enter the Ret mode, and the built-in judgment unit waits for the new Ret mode configuration signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; If the SRAM access interface of a certain group of SRAM inputs 0 to the Ret mode configuration interface of the corresponding Ret mode monitoring module, the Ret mode monitoring module of the group enters the Ret mode dynamic monitoring state to determine whether the group of SRAM enters the Ret mode.

6. The SRAM array low power consumption control method according to claim 5, characterized in that: In the dynamic monitoring state of Ret mode, when no external access is initiated to the group of SRAM, the counter of the Ret mode monitoring module starts counting, and the built-in judgment unit waits for a new Ret mode configuration signal, and at the same time makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1; if an external read or write access to the SRAM is initiated before the count reaches the set Ret threshold, that is, when the SRAM access interface inputs 1 to the SRAM access initiation interface of the Ret mode monitoring module, the counter is cleared, and after the access ends, when the SRAM access interface inputs 0 to the SRAM access initiation interface of the Ret mode monitoring module, the counter restarts counting, so that the group of SRAM does not enter the Ret mode temporarily; before the counter count reaches the threshold, the built-in judgment unit makes the Ret mode control output interface output 0, and the SRAM operable flag output interface output 1.

7. The SRAM array low power consumption control method according to claim 5, characterized in that: In the dynamic monitoring state of Ret mode, when there is no access initiation to this group of SRAM, the counter of the Ret mode monitoring module starts counting. When the counter count reaches the Ret threshold, there is still no new read or write access initiation to this group of SRAM, that is, after the counter count reaches the Ret threshold, the input of this group of SRAM access interface to the SRAM access initiation interface of the Ret mode monitoring module is always 0: The built-in judgment unit of the Ret mode monitoring module sets the Ret mode control output interface to 1 and outputs it to the SRAM, turning off the VDDP power supply of the SRAM, that is, the group of SRAM enters the Ret mode; at the same time, the built-in judgment unit of the Ret mode monitoring module sets the SRAM operable flag output interface to 0, indicating that the group of SRAM does not accept read and write access operations.

8. The SRAM array low power consumption control method according to claim 7, characterized in that: After the SRAM group enters the Ret mode, when a new read or write access to the SRAM group is initiated externally, that is, when the SRAM access interface inputs 1 to the SRAM access initiation interface: If the output of the SRAM operable flag output interface of the Ret mode monitoring module to the SRAM access interface is 0, the SRAM access interface does not immediately perform read and write access operations on the SRAM, that is, the internal address calculation unit does not work, and at the same time, the built-in judgment unit of the Ret mode monitoring module sets the corresponding Ret mode control output interface to 0, turns on the VDDP power supply of the SRAM, that is, the SRAM exits the Ret mode, and at the same time, the built-in judgment unit of the Ret mode monitoring module sets the output of the SRAM operable flag output interface to the SRAM access interface to 1; If the output of the corresponding SRAM operable flag output interface to the SRAM access interface is 1, indicating that the SRAM has exited the Ret mode, the external device can perform read and write access operations on the SRAM through the SRAM access interface.

9. The SRAM array low power consumption control method according to claim 3, characterized in that: The Ret threshold is obtained through simulation, and the simulation process is as follows: Determine bandwidth requirements for work scenarios; The Ret threshold is dynamically modified from high to low, and the minimum value corresponding to the performance requirement is selected as the optimal Ret threshold, and the power consumption is also the minimum at this time.

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