A memory testing system and a memory testing method

Abstract

The present invention provides a test system and a test method for a memory, the test system comprising: a test board, on which a memory is connected, a plurality of detection pins are set on the test board, and the detection pins correspond to the test pins of the memory; a logic analyzer, which generates a custom configuration file based on the detection pins; and a processing module, which is arranged on the test board and is connected to the memory for communication to build a test environment; wherein the processing module is used to send different instructions to the memory so that the memory performs different operations; the logic analyzer is used to obtain the timing waveform of the test pin of the memory when performing different operations; the logic analyzer is also used to compare the timing waveform of the test pin with the timing specification protocol, determine the type of the test pin, and update the configuration file. Through the test system and the test method for a memory provided by the present invention, the definition and arrangement order of the test pins of the memory can be quickly analyzed.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a storage testing system and a storage testing method. Background Art

[0002] Memories are widely used in terminal devices such as mobile phones, tablet computers, televisions, set-top boxes, etc. There are many memory manufacturers in the market. Different manufacturers define some test pins for testing and debugging when designing memories, so that R&D personnel can debug, test and diagnose memories during the R&D and production process to ensure product performance and quality.

[0003] Since each manufacturer has different definitions and usage methods for its test pins and there is no unified standard, different tools and methods are required to debug and test the memories of different manufacturers. How to quickly analyze the definition and arrangement order of the memory test pins has become an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a memory test system and a test method, so as to quickly analyze the definition and arrangement sequence of the test pins of the memory.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory testing system, comprising:

[0007] A test board, to which a memory is connected, wherein a plurality of detection pins are set on the test board, and the detection pins correspond to the test pins of the memory;

[0008] a logic analyzer, which is in communication with the detection pins of the test board and generates a custom configuration file based on the detection pins; and

[0009] A processing module, disposed on the test board and communicatively connected with the memory to build a test environment;

[0010] Wherein, the processing module is used to send different instructions to the memory so that the memory performs different operations;

[0011] The logic analyzer is used to obtain the timing waveform of the test pin of the memory when performing different operations;

[0012] The logic analyzer is also used to compare the timing waveform of the test pin with the timing specification protocol, determine the type of the test pin, and update the configuration file.

[0013] In one embodiment of the present invention, the processing module is used to send a read / write command and corresponding test data to the memory, the logic analyzer obtains the test pins of the memory that have not jumped, represents them as non-signal pins, and updates the configuration file.

[0014] In one embodiment of the present invention, the processing module is used to initiate an initialization operation to the memory, and the logic analyzer determines the test pins of the memory corresponding to command latch enable, write enable, and address latch enable according to the timing specification protocol, and updates the configuration file.

[0015] In one embodiment of the present invention, the processing module is further used to initiate a reset operation to the memory, and the logic analyzer determines the test pins of the memory corresponding to ready / busy and chip select enable according to the timing specification protocol, and updates the configuration file.

[0016] In one embodiment of the present invention, the processing module is also used to initiate a read identification code operation and a read status operation to the memory in sequence, and the logic analyzer determines the test pins of the memory corresponding to the data selection signal-true / complement and the read enable signal-true / complement according to the timing specification protocol, and updates the configuration file.

[0017] In one embodiment of the present invention, the processing module is further used to initiate multiple random read and write operations to the memory, and the logic analyzer determines the test pins of the memory corresponding to the data signal lines according to the timing specification protocol, and updates the configuration file.

[0018] In one embodiment of the present invention, the processing module is further used to initiate a write protection operation to the memory, and the logic analyzer determines the test pin of the memory corresponding to the write protection signal line according to the timing specification protocol, and updates the configuration file.

[0019] In one embodiment of the present invention, the processing module is also used to initiate random read and write operations to the memory. When the processing module determines that the instructions / host data obtained from the memory are consistent with the instructions / host data sent by the processing module to the memory, it indicates that the configuration file has been configured.

[0020] In one embodiment of the present invention, when the processing module determines that the instructions / host data obtained from the memory are inconsistent with the instructions / host data sent by the processing module to the memory, the processing module re-analyzes the test pin of the memory where the problem occurs until the instructions / host data obtained from the memory by the processing module are consistent with the instructions / host data sent by the processing module to the memory.

[0021] The present invention also provides a memory testing method, comprising:

[0022] Build a storage test environment and generate a custom configuration file;

[0023] Sending different instructions to the memory to make the memory perform different operations;

[0024] Acquire the timing waveform of the test pin of the memory when performing different operations;

[0025] The timing waveform of the test pin is compared with the timing specification protocol to determine the type of the test pin, and the configuration file is updated.

[0026] As described above, the present invention provides a test system and test method for a memory, which realizes the automatic configuration and definition of the test pins through the upper-level configuration file, without the need for manual plugging and unplugging to replace different signal lines, thereby significantly improving the efficiency of testing and debugging. At the same time, the definition of the automated configuration file reduces the burden of manual operation and reduces human errors such as wrong connection and missed connection that may be caused by manual plugging and unplugging of signal lines, thereby improving the accuracy and reliability of the test. The present application utilizes a logic analyzer and an automated configuration file to timely and accurately obtain information such as the test pin sequence of the memory and the behavioral status of the back-end interface, ensuring the real-time and accuracy of the data during debugging and problem analysis.

[0027] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0029] Figure 1 A schematic diagram of a memory testing system according to an embodiment of the present invention;

[0030] Figure 2 The figure is a flow chart of a memory testing method according to an embodiment of the present invention.

[0031] In the figure: 100, test board; 200, processing module; 300, detection pin; 400, logic analyzer; 500, host; 600, power module; 700, transmission module; 800, interface module; 900, memory module; 1000, storage. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] See also Figure 1 The present invention provides a memory test system, which can test the type of memory test pins to quickly analyze the definition and arrangement order of the memory test pins. The test system may include a test board 100, a processing module 200 (CPU), a detection pin 300 (TPx), a logic analyzer 400, a host 500, a power module 600 (POWER), a transmission module 700 (USB), an interface module 800 (UART) and a memory module 900 (DRAM).

[0034] In one embodiment, the test board 100 may be a printed circuit board (PCB), on which the processing module 200 , the detection pin 300 , the power module 600 , the transmission module 700 , the interface module 800 and the memory module 900 may be integrated.

[0035] In one embodiment, the processing module 200 may be responsible for executing instructions in a computer program and controlling other hardware devices to work in coordination. The processing module 200 may acquire instructions, decode instructions, and execute instructions to complete its main functions.

[0036] In one embodiment, the detection pins 300 may be test points on the test board 100. The number of the detection pins 300 may be the same as the number of the test pins of the memory 1000. For example, the number of the test pins of the memory 1000 is 26. In this case, the number of the detection pins 300 is also 26, which are divided into TP1 to TP26 according to the sequence number. Each detection pin 300 may be connected to a corresponding test pin of the memory 1000.

[0037] In one embodiment, a logic analyzer 400 (LA) is a tool for capturing and analyzing digital signals. The logic analyzer 400 can be electrically connected to a plurality of detection pins 300 on the test board 100, and can monitor and record the timing waveforms of the test pins of the memory 1000. The logic analyzer 400 can not only capture the signals of the test pins of the memory 1000, but also analyze the relationship between the signals, thereby analyzing the protocol behavior of the memory 1000. For example, the read and write operations of the data bus, the address selection of the address bus, and the enable and disable of the control signal can be analyzed.

[0038] In one embodiment, the host 500 may be electrically connected to the logic analyzer 400 to display information related to the test pins of the memory 1000 .

[0039] In one embodiment, the power module 600 can provide power to the processing module 200 .

[0040] In one embodiment, the transmission module 700 may be connected between the host 500 and the processing module 200. The processing module 200 may display the test information of the memory 1000 on the host 500 through the transmission module 700.

[0041] In one embodiment, the interface module 800 may be electrically connected to the processing module 200. The interface module 800 may be an interface for serial communication. The processing module 200 may perform serial communication with an external device through the interface module 800.

[0042] In one embodiment, the memory module 900 may be electrically connected to the processing module 200. The memory module 900 may be used to temporarily store currently running programs and data. The processing module 200 may quickly access these data to improve computing performance.

[0043] In one embodiment, when testing the test pins of the memory 1000 , the processing module 200 , the detection pins 300 , and the logic analyzer 400 may cooperate with each other to build a test environment for the memory 1000 .

[0044] Specifically, the memory 1000 can be firstly connected to the test board 100 for communication, so that the test pin of the memory 1000 is connected to the detection pin 300 for correspondence. Afterwards, the power module 600 can supply power to the test board 100, so that the processing module 200 and other modules thereon start working. Subsequently, the processing module 200 can also be connected to the host for communication through the transmission module 700, and the host can select a specific firmware or operating system image (SOC Image) and burn it to the storage module (not shown in the figure) of the test board 100 through the transmission module 700. After the burning is completed, the test board 100 is powered on again to start the newly burned image.

[0045] Further, after the memory 1000 is mounted on the test board 100, the multiple signal lines of the logic analyzer 400 can be sequentially connected to the detection pins 300 of the test board 100. For example, the logic analyzer 400 can also be provided with 26 signal lines, the first signal line can be connected to the detection pin 300 with a serial number of TP1, the second signal line can be connected to the detection pin 300 with a serial number of TP2, and so on, the twenty-sixth signal line can be connected to the detection pin 300 with a serial number of TP26. At this time, the multiple signal lines of the logic analyzer 400 can be sequentially connected to the corresponding test pins 300 and connected to the corresponding test pins of the memory 1000.

[0046] Furthermore, after the multiple signal lines of the logic analyzer 400 are sequentially connected to the detection pins 300 of the test board 100 for communication, the logic analyzer 400 can configure the test pins of the memory 1000 through the detection pins 300, generate a custom configuration file, and complete the construction of the test environment.

[0047] Among them, the configuration file can be used to define the mapping relationship between the signal line of the logic analyzer 400 and the test pin of the actual memory 1000. The mapping relationship can follow the JEDEC specification standard to ensure the accuracy and consistency of the test. At this time, the signal line of the logic analyzer 400 in the configuration file corresponds to the test pin of the actual memory 1000, but the type of the test pin of the actual memory 1000 is unclear.

[0048] In one embodiment, after the test environment of the memory 1000 is set up, the processing module 200 can send different instructions to the memory 1000 to make the memory 1000 perform different operations. When the memory 1000 performs different operations, its test pin will send a signal to the outside. At this time, the logic analyzer 400 can obtain the timing waveform of the test pin of the memory 1000 when performing different operations through the detection pin 300, and compare the timing waveform of the test pin with the timing specification protocol to determine the type of the test pin, and update the configuration file.

[0049] In one embodiment, the processing module 200 may send a read / write command and corresponding test data to the memory 1000 to determine a non-signal pin of the memory 1000 .

[0050] Specifically, during the test of the memory 1000, it is necessary to confirm which test pins are signal pins and which test pins are non-signal pins (such as power pins and ground pins). The processing module 200 can send specific read and write commands and data patterns, and the logic analyzer 400 is used to capture and analyze the transitions of these signals.

[0051] First, the processing module 200 can send a large number of read and write commands to the memory 1000 to stimulate all possible signal pins. At the same time, the corresponding test data sent by the memory can be a specific data pattern, such as 0x5A5A5A5A. The specific data pattern has obvious binary jump characteristics, which can trigger obvious changes in the signal and facilitate analysis.

[0052] Subsequently, the logic analyzer 400 can capture the level change of the test pin of the memory 1000 when receiving the read and write commands and data, that is, whether a jump occurs. If a test pin generates an obvious jump (high and low level change) when receiving commands and data, it can be determined that the test pin is a signal pin, because the test pin is transmitting a valid data signal. If a test pin does not generate a jump, it is possible that the test pin is a non-signal pin, such as a power pin (Power) or a ground pin (GND), and a non-signal pin usually does not change state with changes in data commands.

[0053] Further, after it is obtained that some test pins are non-signal pins, the configuration file can be updated according to the serial numbers of the test pins, thereby completing the test of the non-signal pins of the memory 1000 .

[0054] In one embodiment, the processing module 200 may also sequentially initiate an initialization operation, a reset operation, and a read operation to the memory 1000. The logic analyzer 400 may determine the test pins of the memory 1000 corresponding to the command latch enable, write enable, address latch enable, ready / busy, chip select enable, data strobe signal-true / complement, and read enable signal-true / complement according to the timing specification protocol, and update the configuration file.

[0055] In one embodiment, the processing module 200 may first send an initialization instruction to the memory 1000, and the memory 1000 may perform an initialization operation after receiving the initialization instruction. During the initialization process of the memory 1000, each test pin of the memory 1000 will experience a specific timing change. The logic analyzer 400 can determine the specific type and function of each test pin by capturing the timing waveforms of these test pins and comparing them with the timing specification protocol of the memory 1000.

[0056] Specifically, when the processing module 200 initiates the initialization operation of the memory 1000, such as power-on, reset signal triggering, etc., at this time, the logic analyzer 400 can capture and record the timing waveforms of all test pins in this process. Subsequently, the logic analyzer 400 can compare the captured timing waveforms with the description in the timing specification protocol, and identify the functions of each test pin by analyzing the characteristics of the specific timing waveform (such as level change mode, trigger conditions and time parameters). Among them, the timing specification protocol records in detail the expected behavior of each test pin of the memory 1000 when performing different operations, including the rise and fall time, duration, interval, etc. of the signal.

[0057] Furthermore, during the initialization process of the memory 1000, the command latch enable (CLE) signal, the write enable (WE_n) signal, and the address latch enable (ALE) signal can be activated. Among them, the command latch enable signal can maintain a high level or a low level after a specific edge (rising / falling) of the clock signal, indicating the input time window of the command data. The write enable signal is closely related to the data writing operation in terms of timing, and often remains valid (low level) throughout the period of writing data. The duration of the high level or low level of the address latch enable signal is usually consistent with the time window for accurate transmission of address information.

[0058] For example, during the initialization process of the memory 1000, the timing specification stipulates the following characteristics: the command latch enable signal changes from a low level to a high level during a specific initialization command and remains for a period of time; the write enable signal has a low level pulse when data writing is started; the address latch enable signal changes from a low level to a high level during the address specification period and lasts for the entire address specification period. At this time, the logic analyzer 400 captures the timing waveforms of the three test pins.

[0059] The timing waveform of the first test pin rises to a high level at a certain time of initialization and remains high for a period of time. At this time, the timing waveform of the first test pin can correspond to the command latch enable signal. The first test pin can be represented as the test pin corresponding to the command latch enable signal.

[0060] The timing waveform of the second test pin has a short low-level pulse during a specific data transmission period. At this time, the timing waveform of the second test pin can correspond to the write enable signal. The second test pin can be represented as a test pin corresponding to the write enable signal.

[0061] The timing waveform of the third test pin changes from a low level to a high level during a specific initialization period and lasts throughout the entire stage. At this time, the timing waveform of the third test pin can correspond to the address latch enable signal. The third test pin can be represented as the test pin corresponding to the address latch enable signal.

[0062] After determining the test pin corresponding to the command latch enable signal, the test pin corresponding to the write enable signal, and the test pin corresponding to the address latch enable signal, the configuration file can be updated according to the serial numbers of these test pins to complete the test of the command latch enable signal pin, write enable signal pin, and address latch enable signal pin of the memory 1000.

[0063] In one embodiment, the processing module 200 may also send a reset instruction to the memory 1000. After receiving the reset instruction, the memory 1000 may perform a reset operation (Reset). During the reset process of the memory 1000, each test pin of the memory 1000 will experience a specific timing change. The logic analyzer 400 can determine the specific type and function of each test pin by capturing the timing waveforms of these test pins and comparing them with the timing specification protocol of the memory 1000.

[0064] Specifically, in the reset operation of the memory 1000, the Ready / Busy (R / B_n) signal and the Chip Enable (CE_n) signal can be activated. Among them, the Ready / Busy signal can be used to indicate the state of the memory 1000, a high level indicates "Ready" and a low level indicates "Busy". During the reset operation, the Ready / Busy signal will change from a busy state (low level) to a ready state (high level), indicating that the memory 1000 has completed the reset and is ready to receive commands. The chip enable signal can be used to select a specific memory: a low level indicates that the memory is selected, and a high level indicates that the memory is not selected. During the reset operation, the chip enable signal can remain at a low level, indicating that the memory is in a selected state and is ready to receive a reset command at any time.

[0065] For example, during the reset process of the memory 1000, the timing specification stipulates the following characteristics: the ready / busy signal remains at a low level during the reset period and turns to a high level after the reset is completed. The chip select enable signal remains at a low level during the entire reset operation, indicating that the memory is selected. At this time, the logic analyzer 400 captures the timing waveforms of the two test pins.

[0066] The timing waveform of the first test pin maintains a low level during the reset period and turns to a high level after the reset is completed. At this time, the timing waveform of the first test pin can correspond to the ready / busy signal. The first test pin can be represented as the test pin corresponding to the ready / busy signal.

[0067] The timing waveform of the second test pin maintains a low level during the reset operation. At this time, the timing waveform of the second test pin can correspond to the chip select enable signal. The second test pin can be represented as a test pin corresponding to the chip select enable signal.

[0068] After determining the test pins corresponding to the ready / busy signals and the test pins corresponding to the chip select enable signals, the configuration file can be updated according to the serial numbers of these test pins to complete the testing of the ready / busy signal pins and the chip select enable signal pins of the memory 1000.

[0069] In one embodiment, the processing module 200 may also send a read instruction to the memory 1000, and the memory 1000 may perform a read operation after receiving the read instruction. The read instruction may include a read identification code instruction and a read status instruction, and the corresponding read operation may include a read identification code operation (Read ID 90h) and a read status operation (ReadStatus 70h). During the reading process of the memory 1000, each test pin of the memory 1000 will experience specific timing changes. The logic analyzer 400 can determine the specific type and function of each test pin by capturing the timing waveforms of these test pins and comparing them with the timing specification protocol of the memory 1000.

[0070] Further, in the read identification code operation of the memory 1000, the read identification code operation can be used to read the device identification code (ID) of the memory 1000. At this time, the data strobe signal-true / complement (Data Strobe-True / Complement) can be activated. Among them, the data strobe signal is used to synchronize data transmission, and usually has two signal lines: a true signal (DS_T) and a complement signal (DS_C). In the read identification code operation, DS_T and DS_C will have a specific timing relationship, such as being inverted to each other, for accurate synchronization of data transmission.

[0071] Furthermore, in the read state operation of the memory 1000, the read state operation can be used to read the current state information of the memory 1000. At this time, the read enable signal-true / complement (Data Strobe-True / Complement) can be activated. Among them, the read enable signal is used to control the data read operation, and there will also be two signal lines: true signal (RE_T) and complement signal (RE_C). In the read state operation, RE_T and RE_C will have a specific timing relationship, which is used to indicate and control the time window of data reading.

[0072] By analyzing the waveform characteristics of the data selection signal-true / complement and the read enable signal-true / complement, the specific type of the corresponding test pin can be determined. At this time, the configuration file can be updated according to the serial numbers of these test pins to complete the test of the data selection signal-true / complement pin and the read enable signal-true / complement pin of the memory 1000.

[0073] In one embodiment, the processing module 200 may also sequentially initiate multiple data read and write operations and write protection operations to the memory 1000. The logic analyzer 400 may determine the test pins of the memory 1000 corresponding to the data signal line and the write protection signal line according to the timing specification protocol, and update the configuration file.

[0074] In one embodiment, the processing module 200 may sequentially initiate multiple data read and write operations (Command) to the memory 1000. The logic analyzer 400 may determine the test pins of the memory 1000 corresponding to the data signal lines (DQ0-DQ7) according to the timing specification protocol, and update the configuration file. The data sent by the processing module 200 to the memory 1000 may include at least one of 0x1 / 0x2 / 0x3 / 0x4 / 0x5 / 0x6 / 0x7 / 0x8.

[0075] Specifically, when the memory 1000 performs multiple data read and write operations, the signal of the data signal line (DQ0~DQ7) can be activated. The memory 1000 uses multiple parallel data signal lines to transmit data, and each data signal line is responsible for transmitting one data bit. Among them, in the read operation, the memory 1000 transmits the data from the specified address to the data signal line (DQ0~DQ7), and finally reaches the processing module 200. In the write operation, the processing module 200 transmits the data to the specified address of the memory 1000 through the data signal line (DQ0~DQ7). Each data signal line has a specific timing behavior, such as the change of data level in each data cycle, and the synchronization relationship with other signals.

[0076] Furthermore, the timing waveforms of each test pin of the memory 1000 during the read and write operations can be captured and recorded by the logic analyzer 400. Subsequently, the captured waveform is compared in detail with the memory timing specification protocol, with particular attention paid to the characteristics of each data signal line. By analyzing the waveform characteristics, the specific test pins of each data signal line (DQ0~DQ7) can be determined. Finally, the configuration file can be updated according to the serial numbers of these test pins, thereby completing the test of the data signal line pins of the memory 1000.

[0077] In one embodiment, the processing module 200 may initiate a write protection operation to the memory 1000. The logic analyzer 400 may determine the test pin of the memory 1000 corresponding to the write protection signal line according to the timing specification protocol, and update the configuration file.

[0078] Specifically, when the memory 1000 performs a write protection operation, the write protection operation can be used to prevent the contents of the memory 1000 from being accidentally or unauthorizedly changed. At this time, the write protection signal line (Write Protect, WP_n) can be activated. The WP_n signal is usually low-level valid, that is, when the WP_n signal is pulled low, the write operation of the memory 1000 is prohibited to prevent the data from being accidentally or unauthorizedly modified. When the WP_n signal is high, the write operation is allowed. The write protection signal will change level under certain conditions, such as when the write protection is enabled, the WP_n signal will be pulled down to a low level.

[0079] Furthermore, the timing waveforms of each test pin of the memory 1000 during the write protection operation can be captured and recorded by the logic analyzer 400. Subsequently, the captured timing waveform is compared with the timing specification protocol of the memory 1000, with special attention paid to the timing characteristics of the write protection signal line. For example, during the write protection operation, specific timing behaviors are displayed, such as changing from a high level to a low level, and returning to a high level when the write protection is disabled. By comparing with the description in the timing specification, it can be identified that the test pin is a write protection signal line. Finally, the configuration file can be updated according to the serial number of the test pin, thereby completing the test of the write protection signal line pin of the memory 1000.

[0080] Please refer to Table 1, Table 2 and Table 3. In one embodiment, in the above process, the test pins corresponding to the power supply, ground, command latch enable, write enable, address latch enable, ready / busy, chip select enable, data selection signal-true / complement, read enable signal-true / complement, data signal line, and write protection signal line of the memory 1000 have been tested, and the type of the test pin corresponding to the detection pin (TP1~TP26) has been determined, and the mapping relationship between the detection pin and the test pin of the actual memory 1000 has been updated in the configuration file, so as to identify the type of each test pin of the memory 1000. In the above test process, the test order of different test pins can be set according to actual needs. Among them, NC refers to a non-signal line.

[0081] Table 1: Undefined test pins.

[0082]

[0083] Table 2: Test pins during parsing.

[0084]

[0085] Table 3: Parsed test pins.

[0086]

[0087] In one embodiment, the processing module 200 may also initiate a random read and write operation (Random) to the memory 1000. The processing module 200 verifies whether the type of the test pin of the memory 1000 is correct by determining whether the instruction / host data obtained from the memory 1000 is consistent with the instruction / host data sent by the processing module 200 to the memory 1000.

[0088] Specifically, when the instruction / host data obtained by the processing module 200 from the memory 1000 is inconsistent with the instruction / host data sent by the processing module 200 to the memory 1000, it can be indicated that there is a problem with the type of some test pins of the memory 1000, and it is necessary to re-analyze the test pins with problems in the memory 1000 until the instruction / host data obtained from the memory 1000 is consistent with the instruction / host data sent to the memory 1000. When the instruction / host data obtained by the processing module 200 from the memory 1000 is consistent with the instruction / host data sent by the processing module 200 to the memory 1000, it means that the configuration file has been configured. At this time, the configuration file can be saved, for example, in the storage module of the test board 100.

[0089] It can be seen that in the above scheme, the automatic configuration and definition of the test pins are realized through the upper-level configuration file, and there is no need to manually plug and unplug different signal lines, thereby significantly improving the efficiency of testing and debugging. At the same time, the automatic configuration file definition reduces the burden of manual operation and reduces human errors such as wrong connection and missed connection that may be caused by manual plugging and unplugging of signal lines, thereby improving the accuracy and reliability of the test. The present application uses a logic analyzer and an automatic configuration file to timely and accurately obtain information such as the test pin sequence of the memory and the behavioral status of the back-end interface, ensuring the real-time and accuracy of the data during debugging and problem analysis.

[0090] See also Figure 2 The present invention also provides a memory test method, which can be applied to the above test system to test the test pins of the memory 1000. The steps of the test method correspond to the above test system. The test method may include the following steps:

[0091] Step S10: Building a test environment for the storage device and generating a custom configuration file;

[0092] Step S20, sending different instructions to the memory to make the memory perform different operations, obtaining the timing waveform of the test pin when the memory performs different operations, comparing the timing waveform of the test pin with the timing specification protocol, determining the type of the test pin, and updating the configuration file;

[0093] Step S30, initiating a random read / write operation to the memory, and determining whether the instruction / host data obtained from the memory is consistent with the instruction / host data sent to the memory;

[0094] Step S40: when the instruction / host data obtained from the memory is inconsistent with the instruction / host data sent to the memory, re-analyze the test pin of the memory with the problem until the instruction / host data obtained from the memory is consistent with the instruction / host data sent to the memory;

[0095] Step S50: When the instruction / host data obtained from the memory is consistent with the instruction / host data sent to the memory, it indicates that the configuration file has been configured.

[0096] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory testing system, characterized in that: include: A test board, to which a memory is connected, wherein a plurality of detection pins are set on the test board, and the detection pins correspond to the test pins of the memory; A logic analyzer is communicatively connected to the detection pins of the test board and generates a custom configuration file based on the detection pins; as well as A processing module, disposed on the test board and communicatively connected with the memory to build a test environment; Wherein, the processing module is used to send different instructions to the memory so that the memory performs different operations; The logic analyzer is used to obtain the timing waveform of the test pin of the memory when performing different operations; The logic analyzer is also used to compare the timing waveform of the test pin with the timing specification protocol, determine the type of the test pin, and update the configuration file; The processing module is used to send a read / write command and corresponding test data to the memory, the logic analyzer obtains the test pins of the memory that have not jumped, represents them as non-signal pins, and updates the configuration file.

2. The memory test system according to claim 1, characterized in that: The processing module is used to initiate an initialization operation to the memory, and the logic analyzer determines the test pins of the memory corresponding to command latch enable, write enable, and address latch enable according to the timing specification protocol, and updates the configuration file.

3. The memory test system according to claim 1, characterized in that: The processing module is also used to initiate a reset operation to the memory, and the logic analyzer determines the test pins of the memory corresponding to ready / busy and chip select enable according to the timing specification protocol, and updates the configuration file.

4. The memory test system according to claim 1, characterized in that: The processing module is also used to initiate a read identification code operation and a read status operation to the memory in sequence. The logic analyzer determines the test pins of the memory corresponding to the data selection signal-true / complement and the read enable signal-true / complement according to the timing specification protocol, and updates the configuration file.

5. The memory test system according to claim 1, characterized in that: The processing module is also used to initiate multiple random read and write operations to the memory. The logic analyzer determines the test pins of the memory corresponding to the data signal lines according to the timing specification protocol, and updates the configuration file.

6. The memory test system according to claim 1, characterized in that: The processing module is also used to initiate a write protection operation to the memory, and the logic analyzer determines the test pin of the memory corresponding to the write protection signal line according to the timing specification protocol, and updates the configuration file.

7. The memory test system according to claim 1, characterized in that: The processing module is also used to initiate random read and write operations to the memory. When the processing module determines that the instructions / host data obtained from the memory are consistent with the instructions / host data sent by the processing module to the memory, it indicates that the configuration file has been configured.

8. The memory test system according to claim 7, characterized in that: When the processing module determines that the instructions / host data obtained from the memory are inconsistent with the instructions / host data sent by the processing module to the memory, the processing module re-analyzes the test pin of the memory with the problem until the instructions / host data obtained from the memory by the processing module are consistent with the instructions / host data sent by the processing module to the memory.

9. A memory testing method, characterized in that: include: Build a storage test environment and generate a custom configuration file; Sending different instructions to the memory to make the memory perform different operations; Acquire the timing waveform of the test pin of the memory when performing different operations; Comparing the timing waveform of the test pin with the timing specification protocol, determining the type of the test pin, and updating the configuration file; The step of sending different instructions to the memory so that the memory performs different operations includes: Send a read / write command and corresponding test data to the memory, obtain the test pins of the memory that have not jumped, indicate them as non-signal pins, and update the configuration file.

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