Manufacturing method of array substrate, array substrate and display panel

Abstract

Embodiments of the present application disclose a manufacturing method of an array substrate for displaying images, an array substrate and a display panel. The manufacturing method comprises: forming a gate electrode, a gate insulating layer, a semiconductor layer and a conductive metal layer on a substrate surface. A patterned photoresist layer is formed on the surface of the conductive metal layer. Wherein, on the corresponding ramp position area corresponding to the edge of the gate electrode and the connection of the substrate, the upper surface of the patterned photoresist layer has a first height relative to the surface of the conductive metal layer opposite to the gate electrode in the direction perpendicular to the substrate, and the patterned photoresist layer and the surface of the conductive metal layer have a second height on the flat area corresponding to the non-ramp position area in the direction perpendicular to the substrate, the first height is greater than the second height. By etching the conductive metal layer through the patterned photoresist layer with different heights and removing the patterned photoresist layer to form source electrodes and drain electrodes, the source electrodes and the drain electrodes can be effectively prevented from being disconnected on the ramp position area, so that the array substrate and the display panel have better ramp performance and better reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor display, and particularly relates to a manufacturing method of an array substrate, an array substrate and a display panel. BACKGROUND

[0002] The display panel has been widely applied in electronic products, wherein the display panel comprises a plurality of switching transistors for driving pixel units to perform image display. At present, liquid crystal display panels (LCD), organic light-emitting display panels (OLED) or micro organic light-emitting diode display panels (Micro LED TFT) all comprise switching transistors. However, in the manufacturing process of the switching transistors, the source and the drain are prone to disconnection at the climbing position corresponding to the edge of the gate, thereby causing poor reliability of the switching transistors and poor reliability of the display panel applying the switching transistors. SUMMARY

[0003] In view of the deficiencies of the prior art, the present application provides a manufacturing method of an array substrate, a display panel and a switching transistor with better reliability.

[0004] In a first aspect, the present application provides a manufacturing method of an array substrate, comprising the steps of:

[0005] forming a gate, a gate insulating layer, a semiconductor layer and a conductive metal layer on a substrate surface;

[0006] forming a patterned photoresist layer on the surface of the conductive metal layer, wherein the upper surface of the patterned photoresist layer has a first height relative to the surface of the conductive metal layer opposite to the gate in the direction perpendicular to the substrate at the climbing position area corresponding to the connection between the edge of the gate and the substrate; the patterned photoresist layer and the surface of the conductive metal layer have a second height in the direction perpendicular to the substrate at the flat area corresponding to the non-climbing position area, and the first height is greater than the second height;

[0007] etching the conductive metal layer according to the patterned photoresist layer and removing the patterned photoresist layer to form a source and a drain, the semiconductor layer between the gate and the source is a conductive channel, the source and the drain are located on opposite sides of the conductive channel, and the gate, the gate insulating layer, the semiconductor layer, the source and the drain constitute a switching transistor.

[0008] In an embodiment of the present application, forming a patterned photoresist layer on the surface of the conductive metal layer further comprises:

[0009] coating a positive photoresist material on the surface of the conductive metal layer to form an initial photoresist layer;

[0010] exposing the initial photoresist layer by a mask plate, wherein, the ramp position area is not exposed, and the flat area is partially exposed;

[0011] developing the initial photoresist layer after the exposure to remove the initial photoresist layer which is exposed to form the patterned photoresist layer.

[0012] In an embodiment of the present application, a vacuum treatment is performed on the initial photoresist layer before the exposure to increase the contact area between the initial photoresist layer and the conductive metal layer at the ramp position area.

[0013] In an embodiment of the present application, a soft baking treatment is performed on the initial photoresist layer after the vacuum treatment, wherein, the soft baking temperature ranges from 90°C to 130°C, and the soft baking time ranges from 120s to 180s.

[0014] In an embodiment of the present application, a hard baking treatment is performed on the patterned photoresist layer, wherein, the hard baking temperature ranges from 120°C to 180°C, and the hard baking time ranges from 120s to 180s.

[0015] In an embodiment of the present application, after the hard baking treatment of the patterned photoresist layer, the patterned photoresist layer corresponding to the ramp position area has a first width along the extension direction of the gate, and the patterned photoresist layer corresponding to the flat area has a second width along the extension direction of the gate, wherein, the first width is greater than the second width.

[0016] In an embodiment of the present application, the mask plate includes a shielding area and a semi-transparent area, the shielding area is a non-transparent area, and the semi-transparent area is a semi-transparent partial area, wherein, during the exposure, the shielding area is opposite to the ramp position area, and the semi-transparent area corresponds to the flat area.

[0017] In a second aspect, the present application provides an array substrate formed by the above manufacturing method, wherein, the switching transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain which are sequentially stacked from the substrate surface, the source and the drain are located on opposite sides of the conductive channel formed by the semiconductor layer, the source and the drain corresponding to the gate edge connected to the substrate at the ramp position have a first line width along the extension direction of the gate, and the source and the drain corresponding to the position of the gate surface or the substrate surface have a second line width, wherein, the first line width is greater than the second line width.

[0018] In an embodiment of the present application, the source and the drain have an included angle with the semiconductor layer at the ramp position where the gate edge is connected to the substrate, and the included angle ranges from 30° to 40°.

[0019] In the embodiment, the width of the source electrode and the drain electrode in the region corresponding to the climbing position of the gate edge and the connecting position of the substrate is larger than the width of the source electrode and the drain electrode in other positions, thereby effectively avoiding or reducing the risk of breakage of the source electrode and the drain electrode at the climbing position, and effectively improving the reliability of the transistor.

[0020] In a third aspect, a display panel for performing image display is provided, comprising an array substrate, a display medium layer and a counter substrate, wherein the display medium layer is arranged between the array substrate and the counter substrate, the array substrate comprises a substrate and a driving element layer, and the driving element layer comprises at least one of the aforementioned switching transistors.

[0021] Compared with the prior art, when the conductive metal layer is etched by patterning the photoresist layer, that is, the thickness of the photoresist layer corresponding to the climbing position region of the gate edge climbing position recess is larger than the thickness of the photoresist layer in other flat regions, or the photoresist layer corresponding to different positions of the conductive metal layer has different heights relative to the substrate, thereby the included angle between the source electrode, the drain electrode and the substrate formed by the etched conductive metal layer is smaller, which is more conducive to metal climbing, can effectively avoid or reduce the risk of disconnection of the conductive metal layer during etching into the source electrode and the drain electrode, and has better climbing performance, thereby effectively improving the reliability of the source electrode, the drain electrode, the switching transistor, and the array substrate and the display panel applying the switching transistor. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0023] Figure 1 FIG. 1 is a planar structure schematic diagram of a display panel in an embodiment of the present application;

[0024] Figure 2 FIG. 2 is a side structure schematic diagram of the display panel shown in FIG. 1; Figure 1

[0025] Figure 3 FIG. 3 is a planar layout structure schematic diagram of a display panel in an embodiment of the present application; Figure 1

[0026] Figure 4 FIG. 4 is an equivalent circuit schematic diagram of any one pixel unit shown in FIG. 3; Figure 3

[0027] FIG. 5 is an equivalent circuit schematic diagram of any one pixel unit shown in FIG. 3 in a modified embodiment; Figure 5 Figure 3

[0028] ​​​​Figure 6 A flow chart of manufacturing steps of the switch transistor in the array substrate shown in Figures 4-5

[0029] Figure 7 A structural schematic diagram in the manufacturing process of the switch transistor in the array substrate shown in Figure 6

[0030] Figure 8 A structural schematic diagram of the side surface of the patterned photoresist layer

[0031] Figure 9 A planar structural schematic diagram of the mask plate in an embodiment of the present application

[0032] Figure 10 A structural schematic diagram of the top view of the patterned photoresist layer after the hard baking process

[0033] Figure 11 A structural schematic diagram of the hard baking process of the patterned photoresist layer and the etching process

[0034] Explanation of reference signs:

[0035] Display panel-100, display area-AA, non-display area-NA, pixel unit-P, array substrate-10, display medium layer-20, counter substrate-30, first direction-F1, second direction-F2, third direction-F3, substrate-101, driving element layer-102, first arrangement direction-Fs1, second arrangement direction-Fs2, m data lines-D1~Dm, n scan lines-G1~Gn, timing control circuit-11, data driving circuit-12, scan driving circuit-13, display capacitor-C1, storage capacitor-C2, driving transistor-T, pixel electrode-IT, jth data line-Dj, ith scan line-Gi, driving switch-M2, first node-N1, driving node-Nd, second node-N2, control switch-M1, first energy storage element-C3, first power supply end-VDD, second power supply end-VSS, light emitting element-L, gate-G1, gate insulating layer-GI, semiconductor layer-S1, conductive metal layer-A1, source-S, drain-D, source-drain metal layer-SD, upper surface-PP10, bottom surface area surface-A11, top surface area surface-A12, ramp height-hp, first height-h1, ramp position-X, ramp position area-Re1, flat area-Re2, recess-A10, initial photoresist layer-PP1, patterned photoresist layer-PP2, mask plate-MS, mask pattern-MS0, shielding area-MS1, semi-transparent area-MS2, second height-h2, third height-h3, fourth height-h4, first width-d1, second width-d2, third width-d3, third width-d4, width difference-d5, conductive channel-CH, included angle-b, steps-1000~3000.​​ DETAILED DESCRIPTION

[0036] For the purposes of the present application, a more complete description of the application will be presented in the following reference to the accompanying drawings. The drawings presented herein are of preferred embodiments of the application. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0037] The following description of several embodiments with reference to the additional drawings is used to illustrate specific embodiments in which the application can be implemented. The numbers of components in this document, such as "first", "second", etc., are only used to distinguish the described objects and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the application, unless otherwise specified, include direct and indirect connections (couplings). The direction terms mentioned in the application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side" and the like, are only the direction of the attached drawings. Therefore, the direction terms used are for better, clearer illustration and understanding of the application, and are not intended to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0038] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be broadly understood, for example, it can be a fixed connection, or it can be a detachable connection, or it can be an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the connection between two elements inside. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances. It should be noted that the terms "first", "second" and the like in the specification and claims and drawings of the application are used to distinguish different objects, and are not used to describe a specific order.

[0039] In addition, the terms "include", "may include", "contain" or "may contain" used in the application indicate the presence of the corresponding functions, operations, elements, etc. disclosed, and do not limit other one or more functions, operations, elements, etc. In addition, the terms "include" or "contain" indicate the presence of the corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusion. In addition, when describing the embodiments of the application, "may" is used to indicate "one or more embodiments of the application". And the term "exemplary" is intended to refer to an example or illustration.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0041] Referring to Figure 1 , which is a schematic diagram of a planar structure of a display panel in an embodiment of the present application. The display panel 100 has a display area AA and a non-display area NA. The display area AA is provided with a plurality of pixel units P arranged in a matrix, and the non-display area NA is provided with a driving circuit for driving the pixel units P to emit light to perform image display, and signal lines or power supply lines for transmitting signals, which can include one or more of data signal lines, scanning signal lines, and common signal lines. Figure 3 Figure 3

[0042] Referring to Figure 2 , which is a schematic diagram of a side structure of the display panel 100 as shown in Figure 1 . The display panel 100 includes an array substrate 10, a display medium layer 20, and a counter substrate 30 stacked in sequence. The array substrate 10 contains driving elements for driving the display medium layer 20 to emit light to perform image display.

[0043] The display medium layer 20 can be a liquid crystal molecule layer, i.e., the display medium is a liquid crystal molecule. Of course, the display medium layer can also be an organic light-emitting material layer, i.e., the display medium is an organic light-emitting material.

[0044] The array substrate 10 includes at least a substrate 101 and a driving element layer 102.

[0045] The substrate 101 can be a flexible substrate, and the material of the flexible substrate can include polyimide. The substrate 101 can be a single-layer structure, a double-layer structure, or a triple-layer structure. For example, when the substrate 101 is a single-layer structure, the substrate 101 can be a polyimide base material layer; when the substrate 101 is a double-layer structure, the substrate 101 can be a laminated structure of a polyimide base material layer and an inorganic layer; and when the substrate 101 is a triple-layer structure, the substrate 101 can be two polyimide base material layers and an inorganic layer sandwiched between the two polyimide base material layers. It can be understood that the structure of the substrate 101 is not specifically limited in the present application.

[0046] The driving element layer 102 is disposed on one side of the substrate 101, and at least includes a switching transistor Ts for driving Figure 8 ​​) and other elements, including signal traces and / or capacitances, wherein the switching transistor Ts includes a gate metal layer, a gate insulating layer, a semiconductor layer, a source, and a drain, which are stacked in sequence.

[0047] Please refer to Figure 3 , Figure 3 For Figure 1 The planar layout structure of the display panel 100 is shown in the figure.

[0048] As Figure 3 shown, the display panel 100 corresponding to the display area AA includes m data lines D1-Dm and n scan lines G1-Gn arranged in a grid shape. The m data lines D1-Dm extend along a first arrangement direction Fs1, and the n scan lines G1-Gn extend along a second arrangement direction Fs2. The first arrangement direction Fs1 and the second arrangement direction Fs2 are perpendicular to each other. The intersection of the n scan lines G1-Gn and the m data lines D1-Dm corresponds to the pixel unit P. The pixel unit P receives the data voltage corresponding to the gray scale value of the data signal provided by the m data lines D1-Dm under the control of the n scan lines S1-Sn in a predetermined time period, and drives the display medium layer 20 to emit light of a corresponding brightness according to the image signal, so as to achieve image display.

[0049] Corresponding to the non-display area NA of the display panel 100, further including the timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 arranged in the display panel 100 for driving the pixel unit P to perform image display.

[0050] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, for receiving the encoded image signal of RGB from the outside, and outputting the corresponding clock signal, synchronization signal, and decoded image signal (data signal Data) to the data driving circuit 12 and the scan driving circuit 13, so as to control the working time sequence of the two, specifically, the timing control circuit 11 outputs the corresponding timing control signal to the data driving circuit 12 and the scan driving circuit 13, so as to control when the scan driving circuit 13 outputs the corresponding scan signal and control when the data driving circuit 12 outputs the data signal of the corresponding image signal.

[0051] The data driving circuit 12 is electrically connected to the m data lines D1-Dm, for transmitting the image signal to be displayed to the plurality of pixel units P in the form of the data voltage corresponding to the data signal Data in the form of analog.

[0052] The scan driver circuit 13 is electrically connected to the n scan lines G1-Gn and is configured to output scan signals to the pixel unit P via the n scan lines G1-Gn to control when the pixel unit P receives the data signal Data. The scan driver circuit 13 sequentially outputs scan signals from the n scan lines G1-Gn, which are arranged in a positional order, from the scan lines G1, G2, ..., Gn according to temporally consecutive scan cycles within each frame of image display. It will be appreciated that the display panel 100 also includes other functional modules, such as a power supply module and an image processing module, which are not listed in this embodiment.

[0053] See also Figure 4 , Figure 4 for Figure 3 The equivalent circuit diagram of any pixel unit is shown in FIG. Figure 4 As shown, the pixel unit P is a specific circuit structure when the corresponding display medium layer 20 is a liquid crystal molecule.

[0054] The pixel unit P includes a driving transistor T, a display capacitor C1, and a storage capacitor C2. The gate of the driving transistor T is connected to the i-th scan line Gi and is used to control whether the driving transistor T is turned on or off. The source of the driving transistor T is connected to the j-th data line Dj, and the drain of the driving transistor T is connected to the pixel electrode IT. Under the control of the i-th scan line Gi, the driving transistor T receives a data signal from the j-th data line Dj and transmits it to the pixel electrode IT. In this embodiment, the driving transistor T is a thin film transistor.

[0055] It can be understood that the display capacitor C1 is formed by the pixel electrode IT, the liquid crystal molecules serving as the display medium layer 20, and the common electrode, wherein the display capacitor C1 and the storage capacitor C2 are connected in parallel and are used to maintain the electric field of the display capacitor C1 between the pixel electrode IT and the common electrode through the storage capacitor C2 before the next data signal is loaded.

[0056] See also Figure 5 , Figure 5 In a modified embodiment Figure 3 The equivalent circuit diagram of any pixel unit is shown in FIG. Figure 5 As shown, the pixel unit P is a specific circuit structure corresponding to when the display medium layer 20 is an organic light-emitting material. In this embodiment, the pixel unit P includes a control switch tube M1, a driving switch tube M2 and a first energy storage element C3.

[0057] The driving switch tube M2 is connected to the control switch tube M1 through the first node N1, and the driving switch tube M2 is also connected to the first power supply terminal VDD through the second node N2, and is connected to the light-emitting element L through the driving node Nd. The light-emitting element L is connected to the driving node Nd and the second power supply terminal VSS. The first energy storage element C3 is connected to the first node N1 and the second node N2. In this embodiment, the light-emitting element L is an organic light-emitting diode. The anode of the light-emitting diode serving as the light-emitting element L is connected to the driving node Nd, and the cathode is connected to the second power supply terminal VSS. The second power supply terminal VSS can be the ground terminal GND. It can be understood that the light-emitting element L can be directly formed on Figure 2 In the display medium layer 20 shown.

[0058] The control switch tube M1 is connected to the data line Dj, the scan line Gi and the first node N1. The control switch tube M1 is used to receive a scan signal and a data signal during a data writing period of a frame image display period. The scan signal is used to control the corresponding control switch tube M1 to transmit the received data signal to the first energy storage element C3. The data signal is used to control the drive switch tube M2 to cooperate with the drive power Ids provided by the first power supply terminal VDD to output a corresponding drive current to the light-emitting element L during a light-emitting period of a frame image display period, so as to drive the light-emitting element L to emit light to display an image.

[0059] In this embodiment, the control switch tube M1 and the drive switch tube M2 are P-type low-temperature polysilicon (LTPS) or indium gallium zinc oxide (IGZO) thin film transistors (TFT). Of course, in other embodiments of the present application, the control switch tube M1 and the drive switch tube M2 may also be N-type thin film transistors.

[0060] I understand. Figure 4 or Figure 5 The driving transistor T, the control switch tube M1 and the driving switch tube M2 are used as the switching transistor Ts, and the signal wiring and capacitors are all set in Figure 2 In the driving element layer 102 of the array substrate 10 shown.

[0061] Please also refer to Figure 6 and Figure 7 , Figure 6 For example Figures 4-5 The manufacturing process flow chart of the switching transistor in the array substrate is shown in FIG. Figure 7 for Figure 6 The schematic diagram of the structure of the switching transistor in the array substrate during the manufacturing process is shown.

[0062] likeFigures 6-7 As shown,

[0063] Step 1000, forming a transistor gate G1, a gate insulating layer GI, a semiconductor layer S1 and a conductive metal layer A1 on the surface of the substrate 101.

[0064] Specifically, a substrate 101 is provided, which can be a glass substrate or a flexible substrate.

[0065] A first metal layer (not shown in the figure) is formed on the substrate 101, and the first metal layer is etched to form the gate G1.

[0066] A gate insulating layer GI covering the gate G1 is formed on the substrate 101.

[0067] A metal oxide film is formed on the gate insulating layer GI, which can be an IGZO film or an LTPS film in the embodiment, and the metal oxide film is a full-surface covering on the gate insulating layer GI. Among them, if the metal oxide film is an IGZO film, the proportion of indium, gallium and zinc it contains can be 1:1:1. In the embodiment, the metal oxide film is the semiconductor layer S1.

[0068] A conductive metal layer A1 is formed on the surface of the semiconductor layer S1, which can be a metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. in the embodiment, or a composite film composed of multiple metal films, such as a composite film composed of Mo and Al, or a composite film composed of Mo, Al and Mo.

[0069] In the embodiment, since the gate G1 is a structure protruding from the surface of the substrate 101, the gate G1 edge and the substrate 101 surface connection ramp position present a certain height difference to form a ramp position area Re1, and the subsequent gate insulating layer GI, semiconductor layer S1 and conductive metal layer A1 covering the gate G1 correspond to the gate G1 ramp position X, which presents a ramp phenomenon. Since the conductive metal layer A1 has little ductility, the conductive metal layer A1 has a certain depression A10 at the ramp position X. And at the corresponding non-ramp position, the conductive metal layer A1 is in a flat state, that is, outside the non-ramp position area Re1 can be a flat area Re2.

[0070] Step 2000, forming a patterned photoresist layer on the surface of the conductive metal layer A1.

[0071] Specifically, a positive photoresist material (Positive Photoresist) is coated on the surface of the conductive metal layer A1 to form an initial photoresist layer PP1. In the embodiment, the photoresist material can include a mixture of resin, photosensitive agent and solvent.

[0072] Among them, as Figure 8As shown, Figure 8 Figure 1 is a schematic side view of the structure of a patterned photoresist layer PP2. The distance between the top surface PP10 of the initial photoresist layer PP1 and the bottom surface A11 of the conductive metal layer A1 is a first height h1. In this embodiment, the first height h1 is the flat height corresponding to the non-slope position. The top surface of the initial photoresist layer PP1, corresponding to the slope position X, has a slope height hp relative to the top surface A12 of the conductive metal layer A1 facing the top surface of the gate G1 in the second direction F2. In this embodiment, the first height h1 is the same as the slope height hp, and its value can range from 2.6 to 3.0 μm. It can be understood that due to the thickness of the gate insulation layer GI, semiconductor layer S1, and conductive metal layer A1 at the slope position X facing the edge of the gate G1, the photoresist layer at this location relative to the top surface A12 of the conductive metal layer A1 is greater than the first height h1.

[0073] In this embodiment, the surface A11 of the bottom area of ​​the conductive metal layer A1 is the upper surface of the conductive metal layer A1 in the area corresponding to the non-gate G1, and the surface A12 of the top area of ​​the conductive metal layer A1 is the upper surface of the conductive metal layer A1 in the area facing the gate G1.

[0074] In one embodiment of the present application, a vacuum treatment is performed on the initial photoresist layer PP1. In this embodiment, the substrate 101, the gate G1, the gate insulating layer GI, the semiconductor layer S1, the conductive metal layer A1, and the initial photoresist layer PP1 can be placed in a vacuum pumping device and subjected to a vacuum treatment. The vacuum pressure can be 10 Pa, and the vacuum time range can be 120s to 180s. By performing a vacuum treatment on the initial photoresist layer PP1, the initial photoresist layer PP1 can be controlled to cover the conductive metal layer A1 as much as possible and fill the recess A10 at the climbing position X, thereby increasing the contact area between the photoresist material of the initial photoresist layer PP1 and the conductive metal layer A1 in the recess A10.

[0075] In one embodiment of the present application, a soft baking treatment is performed on the initial photoresist layer PP1. In this embodiment, the substrate 101, the gate G1, the gate insulating layer GI, the semiconductor layer S1, the conductive metal layer A1 and the initial photoresist layer PP1 can be soft baked as a whole. The soft baking temperature range can be 90°C to 130°C, and the soft baking time is 120s to 180s. By performing a soft baking treatment on the initial photoresist layer PP1, the adhesion between the initial photoresist layer PP1 and the conductive metal layer A1 is effectively increased, so that the etching liquid or other liquid in the subsequent process is not easy to penetrate into the conductive metal layer, that is, to prevent the liquid from damaging the conductive metal layer and causing the subsequently formed metal electrode to be broken, thereby having better climbing performance.

[0076] In an embodiment of the present application, the initial photoresist layer PP1 is patterned by the mask plate MS.

[0077] Specifically, the initial photoresist layer PP1 is exposed by the mask plate MS with a preset pattern.

[0078] Please refer to Figure 9 which is a schematic diagram of a planar structure of the mask plate MS in an embodiment of the present application, as Figure 9 shown, the mask plate MS includes at least two mask patterns MS0 in a rectangular shape, and the two mask patterns MS0 correspond to the positions of the source and the drain of the transistor Ts respectively. The mask pattern MS0 includes a shielding area MS1 and a semi-transparent area MS2. The shielding area MS1 is located between the two semi-transparent areas MS2, and the shielding area MS1 is a completely opaque area, and the semi-transparent area MS2 can transmit part of the light. In the embodiment, the shielding area MS1 of the mask plate MS is opposite to the ramp position area Re1 including the ramp position X, and the semi-transparent area MS2 corresponds to the position flat area Re2 of the conductive metal layer A1 excluding the ramp position X.

[0079] In an embodiment of the present application, the initial photoresist layer PP1 is exposed by the mask plate MS. The light for exposure can be ultraviolet light (UV light), and the energy range of the light emitted during exposure is 40-60 mj. In the embodiment, since the initial photoresist layer PP1 is a positive photoresist, during the exposure process, the photoresist material corresponding to the fully open position where the mask plate MS is not shielded is fully exposed to the reaction, the photoresist corresponding to the semi-transparent area MS2 of the mask plate MS is partially reacted, and the photoresist corresponding to the shielding area MS1 of the mask plate MS is not reacted. In the embodiment, since the shielding area MS1 of the mask plate MS is opposite to the ramp position X of the conductive metal layer A1, the initial photoresist layer PP1 corresponding to the ramp position area Re1 including the ramp position X of the conductive metal layer A1 does not react, and the photoresist material corresponding to the semi-transparent area MS2 of the mask plate MS at other positions of the initial photoresist layer PP1, such as the flat area Re2, is partially reacted.

[0080] In the embodiment, the width of the shielding area MS1 and the semi-transparent area MS2 is greater than or equal to 2.5 um, and the length is designed according to the length of the source, the drain and the corresponding metal trace of the switching transistor Ts. The material of the mask plate MS can be quartz glass or soda glass, which has high thermal stability, chemical stability and good optical performance.

[0081] In one embodiment of the present application, the initial photoresist layer PP1 that has undergone exposure processing is developed. In this embodiment, the photoresist that is not blocked and has completely reacted with the exposure in the corresponding mask plate MS fully reacts with the developer to melt and is removed, and the photoresist corresponding to the semi-transparent area MS2 in the mask plate MS partially reacts with the developer and is partially melted and removed. The photoresist that has not reacted with the exposure in the blocked area MS1 in the mask plate MS is completely retained, that is, the initial photoresist layer PP1 corresponding to the climbing position X of the conductive metal layer A1 is completely retained, and the photoresist material in the semi-transparent area MS2 in the mask plate MS is partially removed, thereby completing the patterning of the initial pattern layer PP1, that is, forming the patterned photoresist layer PP2.

[0082] In this embodiment, the developer may be a 2.3% to 2.5% TMAH developer, and the development reaction time is 60 to 80 seconds.

[0083] In this embodiment, the photoresist portion corresponding to the semi-transparent area MS2 of the mask MS is removed by the developer. This portion of the photoresist layer has a second height h2. Specifically, excluding the photoresist at the ramping location X, the remaining photoresist layer, i.e., the photoresist layer undergoing partial exposure and development, has a second height h2 from the top surface A12 and the bottom surface A11 of the conductive metal layer A1 in the second direction F2. In this case, the second height h2 corresponds to the flat height, and the first height h1 and the ramping height hp are greater than the second height h2 and the flat height. In this embodiment, the second thickness h2 ranges from 1.3 to 1.5 μm, and the ramp angle of the photoresist in the patterned photoresist layer PP2 corresponding to the ramping location Re1 ranges from 30° to 60°.

[0084] In one embodiment of the present application, the patterned photoresist layer PP2 is hard baked, wherein the hard baking temperature ranges from 120°C to 180°C, and the hard baking time ranges from 120s to 180s. Figure 10 FIG. 1 shows a top view of the patterned photoresist layer PP2 after a hard bake process. The hard bake process fully reflows the patterned photoresist layer PP2, causing the photoresist corresponding to the recess A10 at the ramp position X to flatten and extend in the third direction F3, having a first width d1. The photoresist corresponding to the non-recess A10 has a second width d2, where the first width d1 is greater than the second width d2. In this embodiment, the third direction F3 is perpendicular to the first direction F1, and the first and third directions F1 and F3 lie in the same plane. The plane containing the first and third directions F1 and F3 lies in the same plane as the substrate 101 and the display panel 100.

[0085] In this embodiment, the gate G1 extends along the third direction F3, and the extension direction of the gate G1 is perpendicular to the first direction F1. Therefore, the first width d1 of the patterned photoresist layer PP2 in the third direction F3 at the climbing position X is the size of the patterned photoresist layer PP2 in the third direction F3, and the size of the patterned photoresist layer PP2 in the first direction F1 at the climbing position X is the width at the climbing position X.

[0086] In step 3000 , the conductive metal layer A1 is etched based on the patterned photoresist layer PP2 and the patterned photoresist layer PP2 is removed to form a source / drain metal layer SD. The source / drain metal layer SD includes a source electrode S and a drain electrode D.

[0087] In this embodiment, the conductive metal layer A1 can be etched by dry etching or wet etching. After the etching is completed, the patterned photoresist layer PP2 is removed, thereby forming the source electrode S and the drain electrode D in the source-drain metal layer SD. It can be understood that there is a conductive channel CH between the source electrode S and the drain electrode D. The conductive channel CH directly faces the gate electrode G1. That is, the conductive channel CH overlaps with the projection of the gate electrode G1 on the substrate 101. At the same time, the source electrode S and the drain electrode D are located on opposite sides of the conductive channel CH.

[0088] In this embodiment, the source and drain electrodes S and D formed by etching the patterned photoresist layer PP2 correspond to the location of the recess A10. The first linewidth of the source and drain electrodes S and D in the source / drain metal layer SD at the slope position X is larger than the width at other locations, for example, larger than the second linewidth at the flat region Re2. This effectively avoids or reduces the risk of source and drain electrode fracture at the slope position, effectively improving the reliability of transistor Ts. It can be understood that the first and second linewidths of the source and drain electrodes S and D are the dimensions along the third direction F3 extending from the gate G1.

[0089] Specifically, if Figure 11 As shown, it is a schematic diagram of the hard baking treatment of the patterned photoresist layer and the etching process. The exposed photoresist has a third height h3 and a third width d3. After the hard baking treatment, the photoresist is extended in the horizontal direction, so that the photoresist has a fourth height h4 and a fourth width d4, wherein the fourth height h4 is less than the third height h3, the fourth width d4 is greater than the third width d3, and the fourth width d4 and the third width d3 have a width difference d5.

[0090] When the conductive metal layer A1 is etched by the patterned photoresist layer PP2, that is, the photoresist thickness at the ramp position X where the edge of the gate G1 is connected to the substrate 101 in the ramp position area Re2 is greater than that in other flat areas Re2, that is, the photoresist thickness at the position corresponding to the recess A10 is greater than that in other flat areas Re2, or in other words, the patterned photoresist layer PP2 has different heights at different positions of the conductive metal layer A1 relative to the substrate 101. Thus, the included angle b between the source S, the drain D and the substrate 101 after etching of the conductive metal layer A1 is smaller. In this embodiment, the included angle b can range from 30° to 40°. Since the smaller taper angle (included angle) of the source S and the drain D after etching of the conductive metal layer A1 is more conducive to metal climbing, it can effectively avoid or reduce the risk of disconnection during etching of the conductive metal layer A1 into the source S and the drain D, thereby having better climbing performance, and thus effectively improving the reliability of the source S, the drain D, the switching transistor Ts and the entire display panel 100.

[0091] It can be understood that after the switching transistor Ts is completed, other element structures of the driving element layer 102 formed on the surface of the switching transistor Ts, the display medium layer 20 and the opposite substrate 30 can be formed.

[0092] It should be understood that the application of the present application is not limited to the above examples, and those of ordinary skill in the art can make improvements or changes according to the above description, and all such improvements and changes shall belong to the protection scope of the appended claims of the present application.

Claims

1. A method for manufacturing an array substrate, characterized in that: Including steps: forming a gate, a gate insulating layer, a semiconductor layer and a conductive metal layer on the surface of the substrate; Forming a patterned photoresist layer on the surface of the conductive metal layer specifically includes: coating a positive photoresist material on the surface of the conductive metal layer to form an initial photoresist layer; performing a hard baking process on the patterned photoresist layer, wherein after the hard baking process, the patterned photoresist layer corresponding to the climbing position area has a first width along the extension direction of the gate, and the patterned photoresist layer corresponding to the flat area has a second width along the extension direction of the gate, and the first width is greater than the second width; exposing the initial photoresist layer through a mask, wherein no exposure reaction is performed corresponding to the climbing position area, and a partial exposure reaction is performed corresponding to the flat area; developing the initial photoresist layer after the exposure process to remove the initial photoresist layer that has undergone the exposure reaction to form the patterned photoresist layer, wherein, in the climbing position area corresponding to the connection between the gate edge and the substrate, the upper surface of the patterned photoresist layer has a first height relative to the surface of the conductive metal layer facing the gate in a direction perpendicular to the substrate; in the flat area corresponding to the non-climbing position area and in a direction perpendicular to the substrate, the patterned photoresist layer has a second height with respect to the surface of the conductive metal layer, and the first height is greater than the second height; The conductive metal layer is etched according to the patterned photoresist layer and the patterned photoresist layer is removed to form a source and a drain. The semiconductor layer between the gate and the source is a conductive channel. The source and the drain are located on opposite sides of the conductive channel. The gate, the gate insulating layer, the semiconductor layer, the source and the drain constitute a switching transistor formed on the substrate.

2. The method for manufacturing an array substrate according to claim 1, wherein: Before exposing the initial photoresist layer, a vacuum treatment is performed on the initial photoresist layer to increase a contact area between the initial photoresist layer and the conductive metal layer in the climbing position region.

3. The method for manufacturing an array substrate according to claim 2, wherein: The initial photoresist layer is subjected to a vacuum treatment and then a soft baking treatment, wherein the soft baking treatment temperature range is 90° C. to 130° C., and the soft baking time is 120s to 180s.

4. The method for manufacturing an array substrate according to claim 3, wherein: The hard baking temperature range is 120℃~180℃, and the hard baking time is 120s~180s.

5. The method for manufacturing an array substrate according to any one of claims 2 to 4, wherein: The mask includes a blocking area and a semi-transparent area, the blocking area is an opaque area, and the semi-transparent area is a semi-transmissive area. During exposure processing, the blocking area faces the climbing position area, and the semi-transparent area corresponds to the flat area.

6. An array substrate formed by the method for manufacturing an array substrate according to any one of claims 1 to 5, characterized in that: The switching transistor includes a gate, a gate insulating layer, a semiconductor layer, a source and a drain, which are stacked in sequence from the surface of a substrate, wherein the source and the drain are located on opposite sides of a conductive channel with the semiconductor layer as the conductive channel, the source and the drain correspond to the climbing positions where the gate edge is connected to the substrate, and have a first line width along the direction in which the gate extends, and the source and the drain have a second line width at positions corresponding to the gate surface or the substrate surface, and the first line width is greater than the second line width.

7. The array substrate according to claim 6, wherein: At a climbing position corresponding to where the gate edge is connected to the substrate, the source electrode, the drain electrode, and the semiconductor layer have an angle, and the angle ranges from 30° to 40°.

8. A display panel for performing image display, characterized in that: The array substrate comprises any one of claims 6-7, and further comprises a display medium layer and a counter substrate, wherein the display medium layer is arranged between the array substrate and the counter substrate, the array substrate comprises a substrate and a driving element layer, and the driving element layer comprises at least one of the switching transistors.

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