System, device, method and integrated circuit chip for parallel extraction of compressed data

Abstract

The present invention provides a system, device, method and integrated circuit chip for extracting compressed data in parallel. The system includes: at least two compressed data segmentation groups and a timing adjustment unit, wherein the timing adjustment unit is arranged between the two compressed data segmentation groups connected in series, and the compressed data segmentation group includes a plurality of compressed data segmentation sub-units, wherein the compressed data segmentation group is used to receive a compressed data stream from the outside or the timing adjustment unit, and output the compressed data stream to the outside after extracting the valid data in the compressed data stream in parallel, and transmit the compressed data stream without extracting the valid compressed data to the timing adjustment unit; the timing adjustment unit is used to receive the compressed data stream from the compressed data segmentation group, and output it to the next compressed data segmentation group after adjusting the timing. The technical solution according to the present invention can reduce delay and improve data processing efficiency while realizing parallel compressed data extraction.

Description

Technical Field

[0001] The present invention relates to the technical field of computer data processing, and in particular to a system, device, method and integrated circuit chip for extracting compressed data in parallel. Background Art

[0002] With the advent of the big data era, how to quickly process compressed data and extract effective information has become a cutting-edge research hotspot in the artificial intelligence industry. Data compression can significantly reduce the amount of data that needs to be stored, which is particularly important for systems with limited storage capacity, such as embedded systems or mobile devices. Embedded systems or mobile devices often need to store as much information as possible within a limited storage space. Therefore, these systems can compress data and use storage space more efficiently, thereby storing more data or applying larger programs.

[0003] At present, the commonly used method for quickly processing compressed data includes extracting compressed data in parallel. In applications that require high-speed decompression of large amounts of data or real-time data processing, extracting compressed data in parallel can greatly improve the processing speed of compressed data. Parallel extraction of compressed data usually obtains multiple compressed data by removing the delimiters between compressed data in the compressed data stream. Among them, delimiter detection is usually implemented by a sequence detection circuit, including two common methods: a shift register or a state machine.

[0004] In digital circuits, a sequence detector is a device used to detect a specific sequence. It is often used in digital communications and data transmission to ensure the integrity and accuracy of data. Hardware sequence detectors can be implemented using state machines, lookup tables (LUTs), or other hardware implementation methods. According to specific delimiters, a sequence detector is applied to extract valid data from a compressed data stream. A state machine is a model that describes the behavior of a system state change. It can determine the next state based on the current state and input signal, and output the corresponding signal or perform the corresponding operation. In a sequence detection circuit, the state machine determines the current state based on the input data stream, and looks for a specific sequence pattern based on the current state and input signal. Once a matching sequence pattern is found, the state machine outputs a signal or performs a specific operation. However, both shift registers and state machines have the defects of many clock cycles (large delay) and low efficiency during use, which affects the performance of the decompression circuit.

[0005] To this end, a technical solution is needed that can reduce latency and improve data processing efficiency while achieving parallel compressed data extraction. Summary of the invention

[0006] The present invention aims to provide a system, device and method for parallel extraction of compressed data, which can reduce delay and improve data processing efficiency while realizing parallel compressed data extraction.

[0007] According to one aspect of the present invention, a system for extracting compressed data in parallel is provided, comprising: at least two compressed data segmentation groups and a timing adjustment unit, wherein the timing adjustment unit is arranged between the two compressed data segmentation groups connected in series, the compressed data segmentation group comprises a plurality of compressed data segmentation sub-units,

[0008] The compressed data segmentation group is used to receive a compressed data stream from the outside or the timing adjustment unit, extract valid data from the compressed data stream in parallel and then output it to the outside, and transmit the compressed data stream without extracting valid compressed data to the timing adjustment unit;

[0009] The timing adjustment unit is used to receive the compressed data stream from the compressed data segmentation group, and after adjusting the timing, transmit the compressed data stream to the next compressed data segmentation group.

[0010] According to some embodiments, each of the compressed data segmentation subunits extracts valid data from the compressed data stream and outputs it externally, and transmits the compressed data stream from which valid data has not been extracted to the next compressed data segmentation subunit.

[0011] According to some embodiments, the system further comprises a combinatorial logic for detecting delimiters on the compressed data in parallel, the combinatorial logic being configured to:

[0012] Read the compressed data stream bit by bit to obtain the compressed data segment to be detected;

[0013] Shifting the compressed data segment to be detected to obtain a first deformed data segment;

[0014] Performing a bitwise AND operation on the first deformed data segment and the compressed data segment to be detected to obtain a second deformed data segment;

[0015] Shifting the second deformation data segment to obtain a third deformation data segment;

[0016] Performing a bitwise AND operation on the third deformed data segment and the second deformed data segment to obtain a deformed compressed data segment to be detected;

[0017] The second deformed data segment is subjected to a bitwise XOR operation with the deformed compressed data segment to be detected to obtain separator detection data of the compressed data segment to be detected.

[0018] According to some embodiments, the compressed data segmentation group includes 4-32 of the compressed data segmentation sub-units.

[0019] According to some embodiments, the timing adjustment unit includes: a data synchronizer, and the data synchronizer enables the system timing to converge.

[0020] According to another aspect of the present invention, there is provided a device for extracting compressed data in parallel, which is applied to the system as described above, and the device comprises: a compressed data segmentation group, the compressed data segmentation groups are connected in series in the system, and the compressed data segmentation group comprises at least one compressed data segmentation subunit,

[0021] The at least one compressed data segmentation sub-unit is used to receive a compressed data stream from the outside or the previous compressed data segmentation group, use combinational logic to extract valid data from the compressed data stream in parallel within a clock cycle and then output it to the outside, and transmit the compressed data stream without extracting valid compressed data to the next compressed data segmentation group.

[0022] According to some embodiments, the compressed data segmentation unit is configured to:

[0023] receiving compressed data and delimiter detection data obtained by preprocessing the compressed data, wherein each delimiter in the delimiter detection data occupies one bit;

[0024] The delimiter detection data is traversed: a valid compressed data is obtained from the compressed data according to the bit position of the delimiter; the remaining compressed data is shifted left according to the bit position of the delimiter, thereby removing the corresponding valid compressed data and the delimiter.

[0025] According to another aspect of the present invention, a method for extracting compressed data in parallel is provided, which is applied to the system as described in any one of the above items, and the method comprises:

[0026] Read the compressed data stream bit by bit to obtain the compressed data segment to be detected;

[0027] Shifting the compressed data segment to be detected to obtain a first deformed data segment;

[0028] Performing a bitwise AND operation on the first deformed data segment and the compressed data segment to be detected to obtain a second deformed data segment;

[0029] Shifting the second deformation data segment to obtain a third deformation data segment;

[0030] Performing a bitwise AND operation on the third deformed data segment and the second deformed data segment to obtain a deformed compressed data segment to be detected;

[0031] Performing bitwise XOR operation on the second deformed data segment and the deformed compressed data segment to be detected to obtain delimiter detection data of the compressed data segment to be detected, wherein each delimiter in the delimiter detection data occupies one bit;

[0032] The delimiter detection data is traversed: according to the bit position of the delimiter, a valid compressed data is obtained from the compressed data; the remaining compressed data is shifted left according to the bit position of the delimiter, thereby removing the corresponding valid compressed data and the delimiter. According to another aspect of the present invention, a computer program product is provided, comprising: a computer program, which implements any of the methods described above when executed by a processor.

[0033] According to another aspect of the present invention, an integrated circuit chip is provided, comprising the system or device as described in any one of the above items.

[0034] According to another aspect of the present invention, there is provided a computing device, comprising:

[0035] Processor; and

[0036] A memory storing a computer program, which, when executed by the processor, enables the processor to execute any of the methods described above.

[0037] According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, and when the instructions are executed by a processor, the processor is caused to execute any of the above methods.

[0038] According to an embodiment of the present invention, effective information is extracted from the compressed data stream by applying the compressed data segmentation groups connected in series with each other, wherein each of the compressed data segmentation groups includes a plurality of compressed data segmentation sub-units connected in series, and the compressed data sub-unit can extract a valid compressed data of the compressed data stream, thereby realizing efficient parallel multi-data extraction; the timing adjustment unit is set between the compressed data segmentation groups connected in series, so that the design timing in the system can be converged, the delay can be reduced, and the data processing efficiency can be further improved.

[0039] According to some embodiments, the design of the present invention realizes delimiter detection through logical operations, and the implementation circuit is simple. Compared with the traditional method of using a state machine to perform delimiter detection, the compressed data extraction time is shortened by dozens of times, the efficiency is improved by dozens of times, and the power consumption is also reduced accordingly.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0042] Figure 1 A schematic diagram of a system for extracting compressed data in parallel according to an example embodiment is shown.

[0043] Figure 2 A schematic diagram of compressed data partitioning groups of a system for extracting compressed data in parallel according to an example embodiment is shown.

[0044] Figure 3 A method flow chart of combinatorial logic for detecting delimiters on the compressed data in parallel according to an example embodiment is shown.

[0045] Figure 4 An example of delimiter detection data obtained based on delimiter detection according to an example embodiment is shown.

[0046] Figure 5 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0048] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0049] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0050] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0051] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0052] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0053] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0054] For embedded systems or mobile devices with limited storage capacity, it is often necessary to store as much information as possible within the limited storage space. Data compression can significantly reduce the amount of data that needs to be stored. Therefore, these systems often compress data to efficiently utilize storage space, thereby storing more data or applying larger programs.

[0055] At present, the commonly used method for fast processing of compressed data includes extracting compressed data in parallel. In applications that require high-speed decompression of large amounts of data or real-time data processing, extracting compressed data in parallel can greatly improve the processing speed of compressed data. Parallel extraction of compressed data usually adopts the method of removing the delimiters between compressed data in the compressed data stream to obtain multiple compressed data. Among them, the delimiter detection is usually implemented in the form of a sequence detection circuit, and the sequence detection circuit usually includes a shift register or a state machine. In digital circuits, a sequence detector is a device for detecting a specific sequence. It is usually used in digital communication and data transmission to ensure the integrity and accuracy of data. The hardware sequence detector can be implemented using a state machine, a lookup table (LUT) or other hardware implementation methods. For example, the compressed data stream is 32 bits, and the bit width of a single compressed data (including the delimiter 2`b11) is 3 bits to 8 bits. Compressed data stream [31:0]: 0110_0110_1101_0011_0101_0011_0100_0011, where "11" is the delimiter. The 6 valid compressed data are: 0, 00, 0, 0100, 010100, 010000. The traditional state machine (FSM) needs to detect the compressed data stream bit by bit to obtain valid data. When two consecutive 11s are detected, the previous data is output (valid compressed data). For a 32-bit compressed data stream, it takes 32 clock cycles to obtain 6 valid compressed data; as the bit width of the compressed data stream increases to 64 bits, 128 bits, and 512 bits, more and more clock cycles are used (large delay), which is inefficient, seriously affecting the performance of the decompression circuit and increasing unnecessary power consumption.

[0056] To this end, a technical solution is needed that can reduce delay and improve data processing efficiency while realizing parallel compressed data extraction. According to an embodiment, effective information is extracted from the compressed data stream by applying the compressed data segmentation groups connected in series, wherein each of the compressed data segmentation groups includes a plurality of compressed data segmentation sub-units connected in series, and the compressed data sub-units can extract a valid compressed data of the compressed data stream, thereby realizing efficient parallel multi-data extraction; the timing adjustment unit is set between the compressed data segmentation groups connected in series, so that the design timing in the system can be converged, the delay is reduced, and the data processing efficiency is further improved.

[0057] According to some embodiments, the design of the present invention implements delimiter detection through logical operations, and the implementation circuit is simple. Compared with the traditional method of using a state machine to perform delimiter detection, the compressed data extraction time is shortened by dozens of times, the efficiency is improved by dozens of times, and the power consumption is also reduced accordingly.

[0058] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0059] Figure 1 A schematic diagram of a system for extracting compressed data in parallel according to an example embodiment is shown.

[0060] Figure 2 A schematic diagram of compressed data partitioning groups of a system for extracting compressed data in parallel according to an example embodiment is shown.

[0061] See also Figure 1 and Figure 2 According to an example embodiment, a system for extracting compressed data in parallel is shown in the figure, including: at least two compressed data segmentation groups (delimit_grp) and a timing adjustment unit (DFF), and the timing adjustment unit is arranged between the two compressed data segmentation groups connected in series. The compressed data segmentation group includes a plurality of compressed data segmentation sub-units (delimit_unit), and the compressed data segmentation group is used to receive a compressed data stream from the outside or the timing adjustment unit, and output the valid data in the compressed data stream in parallel, and transmit the compressed data stream without extracting valid compressed data to the timing adjustment unit. The timing adjustment unit can also cache the extracted valid compressed data. The cascaded multiple compressed data segmentation sub-units process data in the same clock cycle, and can therefore be regarded as parallel.

[0062] According to some embodiments, each segmentation group is responsible for processing a portion of the compressed data stream, and each of the compressed data segmentation groups receives the data stream to be decompressed from the outside or the previous timing adjustment unit, extracts valid data from these data streams in parallel, and outputs the extracted results. The number of delimit_units inside delimit_grp can be configured by parameters to achieve the effect of designing and extracting compressed data, thereby shortening the system development cycle and reducing the complexity of system design.

[0063] According to some embodiments, the timing adjustment unit is used to receive the compressed data stream from the compressed data segment group, and after adjusting the timing, transmit the compressed data stream to the next compressed data segment group. In some application scenarios, if the timing can meet the requirements, the timing adjustment unit can also be omitted.

[0064] According to some embodiments, the timing adjustment unit is arranged between two compressed data segmentation groups, and is used to coordinate the data streams between different segmentation groups, receive the compressed data stream that has not been completely extracted from the previous compressed data segmentation group, and adjust the transmission timing of these data. The adjusted data stream is passed to the next compressed data segmentation group for further processing. Such a system can distribute the workload between multiple compressed data segmentation groups, thereby realizing fast parallel decompression of data, and the timing adjustment unit ensures the smooth transition of the data stream between the segmentation groups, so that the design timing converges.

[0065] According to some embodiments, the compressed data segmentation group includes 4-32 compressed data segmentation sub-units. Since delimit_grp contains more combinatorial logic, when delimit_unit is cascaded to a certain number, it will cause the timing of the design to be difficult to converge. Generally speaking, this number limit depends on the scale of the subsequent decompression circuit module, weighing the power consumption and area of ​​the entire module, and depending on the process and clock frequency. For a 12nm process and an operating frequency of 1GHz, one segmentation contains 4 segmentation sub-units; 500MHz contains 8; 250MHz contains 16. If the sub-unit exceeds the range, the timing requirements cannot be met, and it needs to be divided into two or more groups, and a timing adjustment module is inserted in the middle. As the bit width of idata increases, the system (delimit_module) can parameterize multiple delimit_grps, and DFF is automatically inserted in the middle of each delimit_grp to interrupt the combinatorial logic path, so that the design timing converges. This system has the advantages of flexibility and scalability. Such a system design scheme can make full use of the capabilities of multi-core processors to speed up the decompression speed, and is particularly suitable for processing large or high-throughput data streams.

[0066] According to some embodiments, each of the compressed data segmentation subunits extracts a valid data from the compressed data stream for external output, and transmits the compressed data stream without extracting valid data to the next compressed data segmentation subunit. Each compressed data segmentation subunit in the compressed data segmentation group can extract 1 valid compressed data from the compressed data stream, and its output idata_nxt serves as the input (idata) of the next delimit_unit. If 6 delimit_units are cascaded, 6 valid compressed data can be obtained at a time. Compared with the traditional state machine, the efficiency is improved by dozens of times, and the power consumption is correspondingly reduced.

[0067] According to some embodiments, depending on the requirements of the actual computing scenario, the number of compressed data segmentation subunits and compressed data segmentation groups actually required can be configured through parameters. Such a system solution can greatly shorten the R&D cycle and reduce design complexity.

[0068] According to some embodiments, the system further comprises a combinatorial logic for detecting delimiters of the compressed data in parallel, wherein the combinatorial logic is configured as follows: reading the compressed data stream bit by bit to obtain a compressed data segment to be detected; shifting the compressed data segment to be detected to obtain a first deformed data segment; performing a bitwise AND operation on the first deformed data segment and the compressed data segment to be detected to obtain a second deformed data segment; shifting the second deformed data segment to obtain a third deformed data segment; performing a bitwise AND operation on the third deformed data segment and the second deformed data segment to obtain a deformed compressed data segment to be detected; performing a bitwise XOR operation on the second deformed data segment and the deformed compressed data segment to be detected to obtain delimiter detection data of the compressed data segment to be detected. The delimiter detection data of the compressed data segment to be detected will determine which data is considered valid data and extract valid data from the compressed data segment to be detected. The valid data that is not extracted will be passed to the next compressed data segmentation subunit for further processing.

[0069] According to some embodiments, the timing adjustment unit includes: a data synchronizer, which enables the system timing to converge. When the compressed data segmentation sub-units in the compressed data segmentation group are cascaded to a certain number, it will cause the design timing to be difficult to converge, so a data synchronizer (DFF) is automatically inserted in the middle of each compressed data segmentation group to interrupt the combinational logic path so that the design timing converges. Adding DFF is to converge the timing under advanced technology, work at a higher operating frequency, and exert better performance. Figure 3 A method flow chart of combinatorial logic for detecting delimiters on the compressed data in parallel according to an example embodiment is shown.

[0070] See also Figure 3 , the combinational logic is configured to execute the following method.

[0071] In S301, the compressed data stream is read bit by bit to obtain a compressed data segment to be detected.

[0072] According to some embodiments, the compressed data stream is read bit by bit to obtain the compressed data segment to be detected. For example, the compressed data stream is 32 bits, and the bit width of a single compressed data (including the delimiter 2`b11) is 3 bits to 8 bits. Compressed data stream [31:0]: 0110_0110_1100_0111_0101_0011_0100_0011.

[0073] In S303, a logical transformation is performed on the compressed data segment to be detected to obtain a transformed compressed data segment to be detected.

[0074] According to some embodiments, the compressed data segment to be detected is shifted to obtain a first deformed data segment; the first deformed data segment and the compressed data segment to be detected are bitwise ANDed to obtain a second deformed data segment; the second deformed data segment is shifted to obtain a third deformed data segment; the third deformed data segment and the second deformed data segment are bitwise ANDed to obtain a deformed compressed data segment to be detected. In this way, the compressed data segment to be detected is logically converted, and the compressed data segment to be detected is converted into a deformed compressed data segment to be detected that is easy to detect through logical operations, and then the delimiter detection is performed on the deformed compressed data segment to be detected, making the overall detection method simpler and more efficient.

[0075] In S305, delimiter detection is performed on the deformed compressed data segment to be detected to obtain delimiter detection data.

[0076] According to some embodiments, delimiter detection is performed on the deformed compressed data segment to be detected, and specific delimiters in the compressed data are identified to extract valid compressed data. For example, the second deformed data segment is subjected to bitwise XOR operation with the deformed compressed data segment to be detected to obtain delimiter detection data of the compressed data segment to be detected.

[0077] According to some embodiments, the delimiter is detected based on the data, usually to obtain the position information of the delimiter and to intercept valid data from the original data stream. Specifically, each valid compressed data starts from the next bit of the end position of a delimiter and ends at the previous bit of the start position of the next delimiter.

[0078] Figure 4 An example of delimiter detection data obtained based on parallel delimiter detection according to an example embodiment is shown.

[0079] According to an exemplary embodiment, for example, the compressed data stream is 32 bits, and the bit width of a single compressed data (including the separator 2`b11) is 3 bits to 8 bits. Compressed data stream [31:0]: 0110_0110_1100_0111_0101_0011_0100_0011, where "11" is the separator. Then the specific method of performing the logical transformation is:

[0080] First, the compressed data segment [31:0] to be detected is shifted left by 1 bit to obtain the first deformed data segment: 1100_1101_1000_1110_1010_0110_1000_0110 .

[0081] Then, the first deformed data segment and the compressed data segment to be detected are subjected to a bitwise AND operation to obtain a second deformed data segment: 0100_0100_1000_0110_0000_0010_0000_0010.

[0082] Then, the second deformation data segment is shifted to obtain a third deformation data segment: 1000_1001_0000_1100_0000_0100_0000_0100.

[0083] Afterwards, the third deformed data segment and the second deformed data segment are bitwise ANDed to obtain the deformed compressed data segment to be detected: 0000_0000_0000_0100_0000_0000_0000_0000.

[0084] Then, the second deformed data segment and the deformed compressed data segment to be detected are subjected to a bitwise XOR operation to obtain the separator detection data of the compressed data segment to be detected: 0100_0100_1000_0010_0000_0010_0000_0010.

[0085] Thus, for the compressed data: 0110_0110_1100_0111_0101_0011_0100_0011, after performing combinational logic operations, the delimiter detection data is obtained: 0100_0100_1000_0010_0000_0010_0000_0010, see Figure 4 (The green in the figure is valid compressed data, and the red is the separator).

[0086] According to an exemplary embodiment, a device for extracting compressed data in parallel may be provided, comprising: a compressed data segmentation group, the compressed data segmentation groups are connected in series in the system, and the compressed data segmentation group includes at least one compressed data segmentation sub-unit. The device may be applied to the aforementioned system for extracting compressed data in parallel. In the device, the at least one compressed data segmentation sub-unit is used to receive a compressed data stream from the outside or the previous compressed data segmentation group, extract valid data from the compressed data stream in parallel in one clock cycle using combinational logic, and then output it to the outside, and transmit the compressed data stream without extracting valid compressed data to the next compressed data segmentation group.

[0087] According to some embodiments, the compressed data segmentation unit in the device is configured to: receive compressed data and delimiter detection data obtained by preprocessing the compressed data, each delimiter in the delimiter detection data occupies one bit; traverse the delimiter detection data: according to the bit position of the delimiter, obtain a valid compressed data from the compressed data; the remaining compressed data is shifted left according to the bit position of the delimiter, thereby removing the corresponding valid compressed data and delimiter. In this way, multiple compressed data segmentation units (delimit_unit) are cascaded to obtain multiple valid compressed data at one time. Compared with traditional state machines, the efficiency has been improved by dozens of times, and the power consumption has been reduced accordingly.

[0088] For example, following the above example, since the bit width of a single compressed data is 1 to 6 bits, plus the delimiter 2`b11, it is 3 bits to 8 bits. The compressed data segment to be detected is 32 bits, which contains at most 32 / 3 = 10 compressed data and at least 32 / 8 = 4 compressed data. Therefore, to extract a single compressed data, a maximum of 6 judgments are required (equivalent to the maximum bit width of a single compressed data). The corresponding pseudo code (delimit_unit) is, for example:

[0089] input [31:0] idata / / Input compressed data stream

[0090] output [31:0] idata_nxt / /

[0091] output [5:0] cp_data / / Output the effective compressed data after segmentation

[0092] wire [31:0] flag ; / / Obtained after logical conversion and delimiter detection of idata[31:0]

[0093] always_combobegin

[0094] if(flag

[30] ) / / The 30th bit of the delimiter is equal to 1

[0095] cp_data ={5'b0, idata

[31] } / / The effective compressed data is the 31st bit

[0096] idata_nxt = { idata[28:0], 3'b0} / / Shift the remaining data 3 bits to the left, removing the first valid compressed data and delimiter.

[0097] else if(flag

[29] ) / / The 29th bit of the delimiter is equal to 1, and the effective compressed data is [31:30], a total of 2 bits ......

[0098] else if(flag

[25] ) / / The 25th bit of the delimiter is equal to 1

[0099] cp_data ={idata[31:26]} / / The effective compressed data is [31:26], a total of 6 bits

[0100] idata_nxt = { idata[23:0], 8'b0} / / Shift the remaining data 8 bits to the left, removing the first valid compression and delimiter

[0101] end

[0102] According to some embodiments, as shown in the above pseudo code, the idata_nxt output by each if statement is different, and the input data is shifted left according to the judgment condition. {idata[28:0], 3'b0} is shifted left by 3 bits, idata_nxt ={idata[23:0], 8'b0} is shifted left by 8 bits, and so on.

[0103] The circuit implemented by the pseudo code (delimit_unit) can extract one valid compressed data from the compressed data stream, and its output idata_nxt is used as the input (idata) of the next delimit_unit. Six delimit_units can be cascaded to obtain six valid compressed data at a time.

[0104] According to some embodiments, the design scheme of the present invention can be used for the design and development of computer program products. When the computer program is executed by a processor, the following process is implemented: the compressed data stream is read bit by bit to obtain the compressed data segment to be detected; the compressed data segment to be detected is shifted to obtain the first deformed data segment; the first deformed data segment and the compressed data segment to be detected are bitwise ANDed to obtain the second deformed data segment; the second deformed data segment is shifted to obtain the third deformed data segment; the third deformed data segment and the second deformed data segment are bitwise ANDed to obtain the deformed compressed data segment to be detected; the second deformed data segment and the deformed compressed data segment to be detected are bitwise XORed to obtain the delimiter detection data of the compressed data segment to be detected, each delimiter in the delimiter detection data occupies one bit; the delimiter detection data is traversed: according to the bit position of the delimiter, a valid compressed data is obtained from the compressed data; the remaining compressed data is left-shifted according to the bit position of the delimiter, thereby removing the corresponding valid compressed data and delimiter. In this way, the computer program product can process large quantities of compressed data and improve data processing efficiency.

[0105] According to some embodiments, the design scheme of the present invention can be used for a device for extracting compressed data in parallel. When the device is running, the method described above is executed, so that the device can realize parallel compressed data extraction while reducing latency and improving data processing. Compared with the traditional system using a state machine, the system for extracting compressed data in parallel of the present invention shortens the compressed data extraction time by dozens of times, improves the efficiency by dozens of times, and reduces power consumption accordingly.

[0106] Figure 5 A block diagram of a computing device according to an example embodiment of the present invention is shown.

[0107] like Figure 5 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0108] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0109] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 may read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0110] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0111] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0112] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0113] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when the program is executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0114] An embodiment of the present invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0115] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0116] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0117] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0118] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0121] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0122] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. A system for extracting compressed data in parallel, characterized in that: include: at least two compressed data segmentation groups and a timing adjustment unit, wherein the timing adjustment unit is arranged between the two compressed data segmentation groups connected in series, and the compressed data segmentation group includes a plurality of compressed data segmentation sub-units, The compressed data segmentation group is used to receive a compressed data stream from the outside or the timing adjustment unit, extract valid data from the compressed data stream in parallel and then output it to the outside, and transmit the compressed data stream without extracting valid compressed data to the timing adjustment unit; The timing adjustment unit is used to receive the compressed data stream from the compressed data segmentation group, and after adjusting the timing, transmit the compressed data stream to the next compressed data segmentation group. The compressed data segmentation group further includes a combination logic for detecting separators of the compressed data stream in parallel, and the combination logic is configured as follows: Read the compressed data stream bit by bit to obtain the compressed data segment to be detected; Shifting the compressed data segment to be detected to obtain a first deformed data segment; Performing a bitwise AND operation on the first deformed data segment and the compressed data segment to be detected to obtain a second deformed data segment; Shifting the second deformation data segment to obtain a third deformation data segment; Performing a bitwise AND operation on the third deformed data segment and the second deformed data segment to obtain a deformed compressed data segment to be detected; The second deformed data segment is subjected to a bitwise XOR operation with the deformed compressed data segment to be detected to obtain separator detection data of the compressed data segment to be detected.

2. The system according to claim 1, characterized in that Each of the compressed data segmentation sub-units extracts valid data from the compressed data stream and outputs it externally, and transmits the compressed data stream from which valid data has not been extracted to the next compressed data segmentation sub-unit.

3. The system according to claim 1, characterized in that The compressed data segmentation group includes 4-32 compressed data segmentation sub-units.

4. The system according to claim 1, characterized in that The timing adjustment unit includes: a data synchronizer, and the data synchronizer enables the system timing to converge.

5. A device for extracting compressed data in parallel, applied to the system according to any one of claims 1 to 4, characterized in that: The device comprises: a compressed data segmentation group, the compressed data segmentation groups are connected in series in the system, the compressed data segmentation group comprises at least one compressed data segmentation subunit, The compressed data segmentation subunit is used to receive a compressed data stream from the outside or the previous compressed data segmentation group, use combinational logic to extract valid data from the compressed data stream in parallel within a clock cycle and then output it to the outside, and transmit the compressed data stream without extracting valid compressed data to the next compressed data segmentation group.

6. The device according to claim 5, characterized in that The compressed data segmentation subunit is configured as follows: receiving compressed data and delimiter detection data obtained by preprocessing the compressed data, wherein each delimiter in the delimiter detection data occupies one bit; The delimiter detection data is traversed: a valid compressed data is obtained from the compressed data according to the bit position of the delimiter; the remaining compressed data is shifted left according to the bit position of the delimiter, thereby removing the corresponding valid compressed data and the delimiter.

7. A method for extracting compressed data in parallel, applied to a system according to any one of claims 1 to 4, characterized in that: The method comprises: Read the compressed data stream bit by bit to obtain the compressed data segment to be detected; Shifting the compressed data segment to be detected to obtain a first deformed data segment; Performing a bitwise AND operation on the first deformed data segment and the compressed data segment to be detected to obtain a second deformed data segment; Shifting the second deformation data segment to obtain a third deformation data segment; Performing a bitwise AND operation on the third deformed data segment and the second deformed data segment to obtain a deformed compressed data segment to be detected; Performing bitwise XOR operation on the second deformed data segment and the deformed compressed data segment to be detected to obtain delimiter detection data of the compressed data segment to be detected, wherein each delimiter in the delimiter detection data occupies one bit; The delimiter detection data is traversed: a valid compressed data is obtained from the compressed data according to the bit position of the delimiter; the remaining compressed data is shifted left according to the bit position of the delimiter, thereby removing the corresponding valid compressed data and the delimiter.

8. A computer program product, characterized in that include: A computer program, which, when executed by a processor, implements the method according to claim 7.

9. An integrated circuit chip, characterized in that: Comprising a system according to any one of claims 1-4 or an apparatus according to any one of claims 5-6.

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