Chip and chip detection method

Abstract

The present disclosure provides a chip, comprising: a plurality of multiplexing modules of the same structure, each multiplexing module having a module input end and a module output end; the detection input pins are connected to the module input ends of the multiplexing modules and are used for inputting the detection signals into the module input ends; the comparison module is provided with an input end and an output end, the input end of the comparison module is connected with the module output ends of the multiplexing modules, and the comparison module is used for receiving and comparing result signals output by the multiplexing modules at the respective module output ends for the detection signals; the output end of the comparison module outputs a comparison result representing whether the result signals of the output ends of all the modules connected with the comparison module are completely the same or not; and the comparison output pin is connected with the output end of the comparison module and is used for outputting a signal representing a comparison result. The invention further provides a chip detection method.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip detection, and in particular to a chip and a chip detection method. Background Art

[0002] With the evolution of chip manufacturing technology, the number of devices in the chip is increasing, the size is getting smaller, and the scale is getting larger, which increases the probability of defects. In order to screen out faulty chips and improve product quality, the chips need to be tested.

[0003] However, when testing a chip including a large number of multiplexed modules (such as multiplexed cores), the number of pins required for the chip is still large, and the testing process is complicated. Summary of the invention

[0004] The present disclosure provides a chip and a chip detection method.

[0005] In a first aspect, an embodiment of the present disclosure provides a chip, comprising:

[0006] A plurality of multiplexing modules with the same structure, each of the multiplexing modules having a module input end and a module output end;

[0007] A detection input pin, the detection input pin is connected to the module input end of each of the multiplexing modules, and is used to input a detection signal to the module input end;

[0008] A comparison module, wherein the comparison module has an input end and an output end, the input end of the comparison module is connected to the module output end of each of the multiplexing modules, the comparison module is used to receive and compare the result signals output by each of the multiplexing modules at their respective module output ends for the detection signal, and output a comparison result representing whether the result signals of all the module output ends connected thereto are completely identical at the output end of the comparison module;

[0009] A comparison output pin, wherein the comparison output pin is connected to an output end of the comparison module and is used to output a signal representing the comparison result.

[0010] In a second aspect, the embodiments of the present disclosure provide a method for detecting a chip, wherein the chip includes a plurality of multiplexing modules with the same structure, each of the multiplexing modules has a module input end and a module output end, and the method includes:

[0011] Acquire a detection signal, and synchronously transmit the detection signal to the module input end of each of the multiplexing modules;

[0012] Each of the multiplexing modules outputs a result signal at a respective module output terminal in response to the detection signal;

[0013] Comparing the result signals at the module output ends of the multiplexing modules, and generating a comparison result indicating whether the result signals are completely identical;

[0014] A signal representing the comparison result is output.

[0015] A comparison module is provided inside the chip of the disclosed embodiment, which compares the signals generated by multiple multiplexing modules and obtains a comparison result representing whether all the signals are the same. Since the multiplexing modules have the same structure, when the same detection signal is input to them through the detection input pins, the result signals they generate should theoretically be the same. If there are differences, it indicates that there are multiplexing modules with different structures. Therefore, by analyzing the comparison results, it is possible to determine to a certain extent whether the chip is faulty (for example, if the comparison results show that the result signals generated by the multiplexing modules are different, it means that at least some of the multiplexing modules are faulty), and it is not necessary to output the result signals of all the multiplexing modules. Therefore, the chip requires a small number of pins, a simple structure, and a simple and fast detection process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings of the embodiments of the present disclosure:

[0017] Figure 1 A block diagram of a chip provided in an embodiment of the present disclosure;

[0018] Figure 2 A block diagram of a multiplexing module in a chip provided by an embodiment of the present disclosure;

[0019] Figure 3 A block diagram of another chip provided in an embodiment of the present disclosure;

[0020] Figure 4 A block diagram of another chip provided in an embodiment of the present disclosure;

[0021] Figure 5 A circuit diagram of a comparison module in a chip provided in an embodiment of the present disclosure;

[0022] Figure 6 A circuit diagram of another comparison module in a chip provided by an embodiment of the present disclosure;

[0023] Figure 7 A flowchart of a chip detection method provided by an embodiment of the present disclosure;

[0024] Figure 8 A flowchart of another chip detection method provided by an embodiment of the present disclosure;

[0025] Fig. 9 A schematic diagram of a specific logic process of chip detection provided by an embodiment of the present disclosure;

[0026] The meanings of the reference numerals include:

[0027] 11. First AND gate unit; 12. First OR gate unit; 13. First XOR gate unit; 14. Second OR gate unit; 15. Second AND gate unit; 21. Second XOR gate unit; 22. Third OR gate unit; 23. Multiplexer unit. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the chip and the chip detection method provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0029] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0030] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0031] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0032] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0033] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0035] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0036] With the evolution of chip (such as logic chip, network chip, etc.) manufacturing technology, the number of devices (such as transistors, etc.) in the chip is increasing, the size is getting smaller, and the scale is getting larger, which increases the probability of defects (failures). For example, defects may include adhesion short circuits between circuits, circuits being incorrectly connected to unnecessary positions (such as high level or low level), delays due to circuit defects, etc.

[0037] In order to screen out faulty chips and improve product quality, it is necessary to test the chips.

[0038] However, the scale of the integrated circuits in the chip is very large, and the combinational logic and timing logic are very complex, so it is difficult to directly detect or observe the devices in it. To this end, a specific detection signal can be input into the chip, and the result signal generated by the chip can be analyzed to determine whether the chip structure has a fault.

[0039] Specifically, the test vector (a series of signals consisting of 0s and 1s) can be generated through the automatic test pattern generation (ATPG) technology and input into the chip through the input pins. At the same time, the result vector generated by the chip is obtained through the output pins. The automatic test equipment (ATE) compares the standard vector when there is no fault and the actual result vector to see if they are the same, thereby determining whether there is a fault in the chip.

[0040] In large-scale chips, multiple parts with the same structure, i.e., multiple "multiplexing modules", such as multiple logic cores (multiplexing cores), are often included. Since these multiplexing modules have the same structure, they can be detected with the same detection signal (such as detection vector). To this end, a shared input technology can be used, that is, the same detection signal is input to multiple multiplexing modules through one input pin of the chip at the same time, so as to reduce the number of input pins and simplify the input of the detection signal.

[0041] However, although the input detection signal can be shared, different multiplexing modules are independent of each other, so the result signals (such as result vectors) generated by their respective operations still need to be read out through different output pins and compared with standard results (such as standard vectors) to determine whether each multiplexing module is faulty. Therefore, the above method still requires the chip to have a large number of output pins, and still needs to detect and analyze each multiplexing module separately, so the total number of pins of the chip is still large, the structure is still complex, and the detection process is still complex.

[0042] Moreover, the testing cost is an important component of the chip cost. The time-consuming testing process will also delay the chip's time to market. Therefore, a complicated testing process will also lead to an increase in chip costs and affect its marketability.

[0043] First, refer to Figures 1 to 6 , an embodiment of the present disclosure provides a chip.

[0044] The embodiments of the present disclosure provide a relatively independently packaged chip with data processing capability, which includes but is not limited to a logic chip, a network chip, and the like.

[0045] Reference Figure 1 , the chip of the embodiment of the present disclosure includes:

[0046] A plurality of multiplexing modules with the same structure, each multiplexing module having a module input end and a module output end;

[0047] A detection input pin, which is connected to a module input terminal of each multiplexing module and is used to input a detection signal into the module input terminal;

[0048] A comparison module, wherein the comparison module has an input end and an output end, the input end of the comparison module is connected to the module output end of each multiplexing module, the comparison module is used to receive and compare the result signal output by each multiplexing module at the respective module output end for the detection signal, and output a comparison result representing whether the result signals of all the module output ends connected to it are completely identical at the output end of the comparison module;

[0049] The comparison output pin is connected to the output end of the comparison module and is used to output a signal representing the comparison result.

[0050] The chip of the embodiment of the present disclosure can be divided into multiple modules, and the structures and functions of some modules are exactly the same, and these modules are called multiplexing modules.

[0051] For example, in a multi-core chip, multiple identical logic cores, that is, multiple multiplexed cores (multiplexed modules), can be formed through wrapper chain technology.

[0052] The chip is also provided with multiple pins (i.e., I / O ports, such as Pins) for exchanging information with the outside, some of which are detection input pins for receiving detection signals, and the detection input pins are connected to the module input end to transmit the received detection signal to the module input pin, so that the multiplexing module operates according to the received detection signal and generates a corresponding result signal at its own module output end.

[0053] In some embodiments, each detection input pin is connected to the module input terminals at the same position of each multiplexing module, and is used to synchronously input the same detection signal to each module input terminal connected thereto.

[0054] Reference Figure 1 As one method of the embodiment of the present disclosure, each detection input pin can be simultaneously connected to the same module input terminal of multiple multiplexing modules, that is, a shared input terminal (shared-input) technology is adopted, so that inputting a detection signal to one detection input pin can make the module input terminals at the same position of all multiplexing modules synchronously receive the same detection signal, and then each multiplexing module will run synchronously and generate result signals synchronously.

[0055] It should be understood that if the shared input terminal technology is not adopted, it is also feasible to connect each detection input pin to only one module input terminal; in this case, when performing detection, the same detection signal needs to be simultaneously input to multiple detection input pins of the module input terminals corresponding to each multiplexing module.

[0056] Among them, the detection signal can specifically be a detection vector generated by automatic test pattern generation (ATPG, Automatic Test Pattern Generation) technology, that is, a signal composed of a series of 0s and 1s; correspondingly, according to the detection vector, each multiplexing module will also generate a result vector, which is also a signal composed of a series of 0s and 1s.

[0057] Among them, when the multiplexing module has no faults, the result vector it generates "should" be a standard signal, that is, a standard vector; if the multiplexing module has faults, the result vector it generates may be different from the standard vector in one or more bits.

[0058] Furthermore, ATPG-based detection can use scan chain technology, and the scan chain can be designed according to the requirements of Design For Test (DFT). Scan chain refers to a structure in which functional registers are replaced with scan registers and connected in series into a chain, in which a multiplexer (MUX) is newly added. Therefore, the detection signal can be effectively transmitted through the scan chain, and the result signal output by the device under test can be received to achieve detection. Under the control of the MUX selection signal (scan_enable) of the scan register, the scan chain usually has two working modes: functional mode and detection mode; in functional mode, the scan register performs the function of the register, is responsible for storing the data of the combinational logic, and works according to the original structure; in detection mode, the detection signal is shifted and input in sequence through the scan register, and after the detection result is obtained, it is shifted and output from the scan chain.

[0059] Furthermore, as the chip scale becomes larger and larger, the chip detection process becomes more time-consuming and costly, so scan chain compression technology can also be used, such as the EDT compression of the Tessent tool. EDT compression can convert an original large scan chain into multiple short scan chains to shorten the detection time and reduce the detection cost.

[0060] Reference Figure 1 The chip of the embodiment of the present disclosure also includes a comparison module, each comparison module is connected to the module output end of each multiplexing module, so that it can receive the result signals generated by these multiplexing modules according to the detection signals, compare whether all the result signals are exactly the same, and generate corresponding comparison results (such as using 0 to indicate that all the result signals are exactly the same, and using 1 to indicate that there is at least one difference among all the result signals), and then output them from the comparison output pin.

[0061] Among them, since the structures of all multiplexing modules should be the same in theory, when multiple multiplexing modules receive the same detection signal at the same time, if the multiplexing modules are all fault-free, the result signals generated by the module output ends of all multiplexing modules should also be exactly the same; if these result signals are not exactly the same, it means that the structures of all multiplexing modules are not exactly the same, that is, there is at least one faulty (different structure) multiplexing module.

[0062] It should be understood that each multiplexing module may actually have multiple module input terminals and multiple module output terminals. Different module input terminals of the same multiplexing module may require different detection signals, and different module output terminals of the same multiplexing module may also generate different result signals.

[0063] Therefore, each of the above detection input pins should be connected to the same module input terminal of each multiplexing module (such as all connected to the ath module input terminal), and each comparison module should also be connected to the same module output terminal of each multiplexing module (such as all connected to the bth module output terminal), and compare the result signals of these module output terminals at the same position.

[0064] For example, refer to Figure 2 Each multiplexing module can have (n+1) module input terminals, namely shared_dft_edt_in[n:0], and (m+1) module output terminals, namely dft_edtout_i[m:0]. Therefore, refer to Figure 3 The chip has a total of n detection input pins (such as EDT input pins), (m+1) comparison modules and comparison output pins, and may also have (m+1) detection output pins (such as EDT output pins) described later, multiplexer modules, etc.

[0065] Reference Figure 3 There are a total of (j+1) multiplexing modules in the chip, so the module output ends of all multiplexing modules are from dft_edtout_i_0[m:0] to dft_edtout_i_j[m:0]; and the module output ends of the kth comparison module, comparison output pin, detection output pin, and multiplexer module are connected from dft_edtout_i_0[k] to dft_edtout_i_j[k].

[0066] It should be understood that the module input and module output of each multiplexing module can be connected to other conventional results in the chip in addition to the detection input pins and comparison modules; moreover, the chip may also include other pins for input and output signals during normal operation.

[0067] A comparison module is provided inside the chip of the disclosed embodiment, which compares the signals generated by multiple multiplexing modules and obtains a comparison result representing whether all the signals are the same. Since the multiplexing modules have the same structure, when the same detection signal is input to them through the detection input pins, the result signals they generate should theoretically be the same. If there are differences, it indicates that there are multiplexing modules with different structures. Therefore, by analyzing the comparison results, it is possible to determine to a certain extent whether the chip is faulty (for example, if the comparison results show that the result signals generated by the multiplexing modules are different, it means that at least some of the multiplexing modules are faulty), and it is not necessary to output the result signals of all the multiplexing modules. Therefore, the chip requires a small number of pins, a simple structure, and a simple and fast detection process.

[0068] In some embodiments, the chip of the embodiment of the present disclosure further includes: a detection output pin, the detection output pin is connected to the module output end, and is used to output the result signal of the module output end.

[0069] As before, by comparing the results, it can be determined whether all multiplexing modules are exactly the same, but it cannot be determined whether a single multiplexing module is normal; Figure 3 The chip of the embodiment of the present disclosure may also be provided with a detection output pin, which can directly output the result (result signal) generated by the operation of the multiplexing module itself, so that by analyzing the result signal, it can be directly determined whether the corresponding multiplexing module itself has a fault.

[0070] In some embodiments, a multiplexer module has multiple input terminals, output terminals, and control terminals; the multiple input terminals of the multiplexer module are connected to multiple module output terminals, the control terminal of the multiplexer module is connected to the output selection signal terminal, and the multiplexer module is used to select the module output terminal connected to the output terminal of the multiplexer module according to the signal of the output selection signal terminal.

[0071] In some embodiments, when the chip further includes a detection output pin, the detection output pin is connected to an output end of the multiplexer module.

[0072] Reference Figure 3 , Figure 4 As one embodiment of the present disclosure, the chip may further include a multiplexer (MUX) module, and by outputting a signal (dft_edtout_sel[j:0]) at the selection signal terminal, the multiplexer module can "select" one output terminal that is connected to its own output terminal from the output terminals of the multiple modules connected to it, that is, select a result signal as its own output.

[0073] Further, see Figure 3 When the above detection output pins are provided, the detection output pins may be connected to the output end of the multiplexer module, that is, the multiplexer module may select which multiplexing module the detection output pins specifically output the result signal of.

[0074] As before, the number of multiplexer modules and detection output pins should correspond to the number of module output terminals of a single multiplexing module, which is (m+1); and at the same time, the signal at the output selection signal terminal (dft_edtout_sel[j:0]) should usually allow the multiplexer module and the detection output pin to output the result signal of one of the (j+1) multiplexing modules.

[0075] For example, it can be a reference Fig. 9First, select a multiplexing module and obtain the result signal generated by the output end of each module. If the result signal of the multiplexing module is correct, it can be determined that the multiplexing module is correct (such as a Golden core). Then, the comparison results can be further analyzed to see whether all the multiplexing modules are the same. If so, it means that all the multiplexing modules are correct and the chip is not faulty. If not, it means that at least one other multiplexing module is different from the Golden core and the chip is faulty.

[0076] It should be understood that it is also feasible if only the module output ends of some multiplexing modules (such as a selected multiplexing module) are directly connected to the corresponding detection output pins.

[0077] Among them, refer to Figure 3 As one method of an embodiment of the present disclosure, the detection output pin and the comparison output pin may be two physically independent pins, so that the two can output result signals and comparison results separately (including simultaneously).

[0078] In some embodiments, the chip of the embodiment of the present disclosure also includes: a processing module, the processing module having an input end and an output end, the input end of the processing module is respectively connected to the output end of the multiplexer module and the output end of the comparison module, the output end of the processing module is connected to the comparison output pin, and the processing module is used to process the result signal output by the output end of the multiplexer module to which it is connected and the comparison result output by the output end of the comparison module to which it is connected, and then output them to the comparison output pin.

[0079] As one embodiment of the present disclosure, reference may be made to Figure 3 , Figure 4 The output end of the multiplexer module (i.e., the result signal, that is, the module output end) and the output end of the comparison module (i.e., the comparison result) can be connected to the comparison output pin through the processing module respectively, so that the processing module can perform certain processing on the above result signal and comparison result, and then send the processed result to the comparison output pin.

[0080] In some embodiments, the processing module includes: a selection submodule, the selection submodule is used to select a signal representing a comparison result or a result signal to be output from a comparison output pin.

[0081] Reference Figure 4 As another embodiment of the present disclosure, the processing module may specifically include a selection submodule, which controls the comparison output pin to specifically output a signal representing a comparison result, or output a result signal; that is, the processing module performs a "selection" process on the result signal and the comparison result.

[0082] Therefore, the comparison result and result signal can be output in a “time-sharing” manner through a “common” physical pin (comparison output pin), so as to further reduce the number of chip pins.

[0083] Among them, the specific forms of the above selection submodules are various.

[0084] For example, as a simplest way, the module output end (such as the output end of the multiplexer module mentioned above) and the output end of the comparison module can be connected to the comparison output pin through a transistor (selection submodule) respectively, so that by controlling one of the transistors to be turned on and the other to be turned off, the selected signal can be output.

[0085] For example, you can also refer to Figure 4 , the selection submodule is an AND gate, whose two input ends are connected to the output end of the corresponding comparison module and the control end of the selection submodule respectively, and the output end is connected to the control end of the multiplexer (MUX) in the corresponding conversion submodule (subsequent description), and the module output end (such as the output end of the multiplexer module above) is connected to the comparison output pin through the multiplexer. Therefore, by setting the signal (dft_edtout_uncomp) of the control end of the selection submodule to 0, it can be ensured that the output of the AND gate must be 0, that is, the signal of the control end of the multiplexer is 0, so that the multiplexer continuously outputs the signal of the module output end, that is, the comparison output pin outputs the result signal; and by setting the signal (dft_edtout_uncomp) of the control end of the selection submodule to 1, the AND gate can actually output the comparison result signal, or the comparison result can be loaded to the control end of the multiplexer, and finally the comparison output pin outputs the signal representing the comparison result (subsequent description).

[0086] In some embodiments, the processing module includes:

[0087] The conversion submodule is used to generate a conversion comparison result based on the comparison result and the result signal as a signal representing the comparison result; wherein, when the comparison result represents that the result signals of all module output ends are exactly the same, the conversion comparison result is the same as the signal of the module output end; when the comparison result represents that the result signals of all module output ends are not exactly the same, the conversion comparison result is opposite to the signal of the module output end.

[0088] As mentioned above, the detection signal may be a detection vector generated by the ATPG technology, the signal at the output end of the corresponding module is a result vector, and the analysis process of the result is to compare the result vector with a preset standard vector.

[0089] However, the comparison result directly generated by the comparison module is completely determined by whether the signals of the multiplexing module are the same, and has nothing to do with the original forms of the result vector and the standard vector, so it is not convenient to analyze them.

[0090] For this purpose, please refer to Figure 3 , Figure 4 , a conversion submodule is set to convert the comparison result into the form of "converted comparison result", that is, the processing module performs the processing of "converting" the form of the comparison result according to the result signal, and the characteristics of the converted comparison result obtained are:

[0091] (1) If the comparison result at a certain moment indicates that the signals of all multiplexed modules are the same, then the corresponding bit of the conversion comparison result is the same as the corresponding bit of the result signal at the module output end;

[0092] (2) If the comparison result at a certain moment indicates that the signals of all multiplexed modules are different, then the corresponding bit of the converted comparison result is the inverse of the corresponding bit of the result signal at the module output end.

[0093] Therefore, the conversion comparison result (which represents the comparison result) can be analyzed in a similar manner to the analysis result vector in the related art, that is: the conversion comparison result is compared with the standard vector. If a bit therein is different from the standard vector, it can be determined that there is an error in the signal of at least one multiplexing module at the corresponding time.

[0094] Among them, the specific forms of the above conversion submodules are various.

[0095] For example, refer to Figure 3 , Figure 4 The conversion submodule may include the above multiplexer, the module output end (such as the output end of the above multiplexer module) is directly connected and inverted (such as through a NOT gate unit) to the two input ends of the multiplexer, and the control end of the multiplexer is connected to the output end of the comparison module (including the reference Figure 3 A direct link to, or reference to Figure 4 By selecting the AND gate connection of the submodule above, thus:

[0096] (1) When the comparison result is 0 (the signals of all multiplexed modules are the same), the comparison result controls the multiplexer to directly output the result signal;

[0097] (2) When the comparison result is 1 (the signal of at least one multiplexing module is different), the comparison result controls the multiplexer to output an inverted result signal.

[0098] It should be understood that reference Figure 4 When there are both a selection submodule and a conversion submodule, if the selection submodule controls the comparison output pin to output a result signal, the conversion submodule does not work at this time; and if the selection submodule controls the comparison output pin to output a signal representing the comparison result, the actual output is the conversion comparison result generated by the conversion submodule.

[0099] It should be understood that the specific forms of the processing module are diverse. For example, there may be only one of the selection submodule and the conversion submodule, or both, or there may be other submodules. Moreover, the selection submodule, conversion submodule, etc. may also be in other specific forms, which will not be described in detail here.

[0100] It should be understood that the selection submodule, conversion submodule, etc. may also be in other specific forms, which will not be described in detail here.

[0101] In some embodiments, the comparison module includes:

[0102] A first AND gate unit 11, the first AND gate unit 11 comprises a plurality of input terminals corresponding to the output terminals of each module connected to the comparison module, each input terminal being connected to the output terminal of the corresponding module;

[0103] A first OR gate unit 12, the first OR gate unit 12 comprises a plurality of input terminals corresponding to the output terminals of each module connected to the comparison module, each input terminal being connected to the output terminal of the corresponding module;

[0104] The first XOR gate unit 13 includes two input terminals respectively connected to the output terminal of the first AND gate unit 11 and the output terminal of the first OR gate unit 12 .

[0105] Reference Figure 5 As one embodiment of the present disclosure, each comparison module may specifically include a first AND gate unit 11 and a first OR gate unit 12, and all module output ends corresponding to the comparison module (such as a total of (j+1) segments) are respectively connected to the inputs of the first AND gate unit 11 and the first OR gate unit 12, and the outputs of the first AND gate unit 11 and the first OR gate unit 12 are then simultaneously connected to the input of the first XOR gate unit 13.

[0106] Therefore, if the signals at the output ends of all modules are the same (all 1 or all 0), the outputs of the first AND gate unit 11 and the first OR gate unit 12 must also be the same (all 1 or all 0), so that the comparison result of the outputs of the two after passing through the first XOR gate unit 13 is 0; and as long as the signals at the output ends of all modules are not exactly the same (some are 1 and some are 0), the output of the first AND gate unit 11 must be 0 and the output of the first OR gate unit 12 must be 1, so that the comparison result of the outputs of the two after passing through the first XOR gate unit 13 is 1.

[0107] In some embodiments, the comparison module further includes a second OR gate unit 14 and a second AND gate unit 15 corresponding to at least part of the module output terminals;

[0108] Each second OR gate unit 14 includes two input terminals connected to the corresponding module output terminal and the first shielding signal terminal, and an output terminal connected to the input terminal of the first AND gate unit 11;

[0109] Each second AND gate unit 15 includes two input terminals connected to the corresponding module output terminal and the inverted phase of the first shielding signal terminal, and an output terminal connected to the input terminal of the first OR gate unit 12:

[0110] The second OR gate unit 14 and the second AND gate unit 15 corresponding to the same module output terminal are connected to the same first shielding signal terminal.

[0111] In some cases, it may be desirable not to compare some multiplexing modules, and thus it is necessary to "shield" the information of the corresponding multiplexing modules so that it does not affect the comparison module.

[0112] For example, if it has been determined that a certain multiplexing module has a fault, the signal of the multiplexing module may be shielded to further analyze whether other multiplexing modules have faults.

[0113] For this purpose, please refer to Figure 5 In the comparison module, a second OR gate unit 14 is further arranged between each module output end and the corresponding first AND gate unit 11, and a second AND gate unit 15 is arranged between each module output end and the corresponding first OR gate unit 12, and the other output end of the second OR gate unit 14 and the second AND gate unit 15 corresponding to the same module output end are respectively connected to the same first shielding signal end and its inverse.

[0114] It should be understood that the "inversion" in the embodiment of the present disclosure means that the signals connected at the two positions are inverted, and the specific implementation methods are various, such as can be referred to Figure 5 A NOT gate unit is provided between the first shielding signal terminal and the second AND gate unit 15, or the two positions may be connected to different ports respectively, and the signals provided by the two ports are always inverted.

[0115] At the same time, the inversion of two signals is a relative concept rather than an absolute concept. For example, Figure 5 The NOT gate unit in the circuit can actually be arranged between the first shielding signal terminal and the second OR gate unit 14. In this case, it is sufficient to invert the signal provided by the first shielding signal terminal.

[0116] Among them, when it is necessary to shield the signal of a certain module output end, the signal of the corresponding first shielding signal end (dft_comp_mask_en[j:0]) can be set to 1, so that the output of the second OR gate unit 14 continues to be 1, and 1 "does not affect" the output of the subsequent first AND gate unit 11; at the same time, the inversion of the signal at the first shielding signal end is 0, so the output of the second AND gate unit 15 continues to be 0, and 0 also "does not affect" the output of the subsequent first OR gate unit 12.

[0117] For the module output terminal that does not need to be shielded, the signal at the corresponding first shielding signal terminal is set to 1, which is equivalent to the existence of the second AND gate unit 15 and the second OR gate unit 14 "not affecting" the result signal of the module output terminal.

[0118] That is to say, when the signal (dft_comp_mask_en[j:0]) of the first shielding signal terminal corresponding to the module output terminal is set to 1, the first AND gate unit 11 and the first OR gate unit 12 can work only according to the signal of the "other" module output terminal without being affected by the signal of the module output terminal, that is, the signal of the corresponding module output terminal is "shielded".

[0119] In some embodiments, the comparison module includes:

[0120] A plurality of second XOR gate units 21, one of the output ends of each module connected to the comparison module is simultaneously connected to an input end of all the second XOR gate units 21, and each of the other module output ends is respectively connected to another input end of each second XOR gate unit 21 in a one-to-one correspondence;

[0121] The third OR gate unit 22 includes a plurality of input terminals respectively connected to the output terminals of the second XOR gate units 21 .

[0122] Reference Figure 6 As another embodiment of the present disclosure, the comparison module may also include multiple (j) second XOR gate units 21, and one input end of all the second XOR gate units 21 is connected to the same module output end ( Figure 6 Module output terminal j is taken as an example), and each other module output terminal ( Figure 6 In the example, module output terminals 0 to j-1 are respectively connected to the other input terminal of a second XOR gate unit 21; thus, multiple second XOR gate units 21 are equivalent to comparing the signal of a selected module output terminal (module output terminal j) with the signal of each other module output terminal. If the results are the same, the outputs of all second XOR gate units 21 are 0, and the comparison result 0 can be generated through the third OR gate unit 22; and as long as the results are not the same, the output of the second XOR gate unit 21 will be 1, and the comparison result 1 can be generated through the third OR gate unit 22.

[0123] In some embodiments, the comparison module also includes a multiplexer unit 23 corresponding to at least part of the module output end; the module output end is directly connected and inversely connected to the two input ends of the corresponding multiplexer unit 23, the output end of the multiplexer unit 23 is connected to the corresponding second XOR gate unit 21, and the control end of the multiplexer unit 23 is connected to the second shielding signal end.

[0124] For reference Figure 6 The comparison module of the form also includes a multiplexer (MUX) unit 23 that plays a shielding role, and each module output terminal is directly connected and invertedly connected (such as by setting a NOT gate unit) to the multiplexer unit 23 at the same time. Therefore, through the signal at the second shielding signal terminal (dft_comp_mask_en[j:0]), the multiplexer unit 23 can be selected to be the original signal of the output module output terminal or its inverted signal.

[0125] Therefore, when it is determined that the result signal of a certain module output end is wrong at a certain time, the signal of the second shielding signal end can be used to control the corresponding multiplexer unit 23 to output its inverted signal, that is, to ensure that the signal entering the second XOR gate unit 21 from the module output end is always correct, so as to shield the influence of the signal of the module output end.

[0126] It should be understood that the chip may also include other structures, such as a beat logic module located in front of the detection output pin (including a shared comparison output pin), a register module directly connected to the output end of each module, a compression / decompression unit (Compressor / Decompressor) located in the multiplexing module, etc., which will not be described in detail here.

[0127] The effects achieved by the chip of the embodiment of the present disclosure are described in detail below.

[0128] For example, suppose a chip has 32 multiplexed cores, each multiplexed core has 6 output terminals, and the chip has 36 output pins.

[0129] Therefore, according to the ATPG detection method in the related art, a maximum of 36 / 6=6 multiplexed cores can be tested on the ATE device each time, so a total of 32 / 6≈6 tests are required, and the detection time is approximately 6T (the time for a single test is T).

[0130] If the method of the embodiment of the present disclosure is adopted, only one detection (if the comparison result and the result signal can be output simultaneously) or two detections (if the comparison result and the result signal are output separately) are required, and the detection time is approximately T or 2T, which is 1 / 6 or 1 / 3 of the related art.

[0131] Moreover, if the method of the embodiment of the present disclosure is adopted, only 6 output pins are actually needed (if the comparison result and the result signal are output through the comparison output pins in time sharing) or 12 (if the comparison result and the result signal are output through different pins), which can also greatly reduce the number of output pins to be used and save I / O resources.

[0132] Second, refer to Figures 1 to 9 , the embodiments of the present disclosure provide more than one chip detection method.

[0133] The chip detected by the method of the embodiment of the present disclosure includes a plurality of multiplexing modules with the same structure, and each multiplexing module has a module input end and a module output end.

[0134] It should be understood that the chip detection method of the embodiment of the present disclosure can be specifically used to detect any chip of the embodiment of the present disclosure.

[0135] Reference Figure 7 The chip detection method of the embodiment of the present disclosure includes:

[0136] S201, acquiring a detection signal, and synchronously transmitting the detection signal to a module input terminal of each multiplexing module.

[0137] S202 . Each multiplexing module outputs a result signal at its own module output terminal in response to the detection signal.

[0138] S203 , comparing the result signals at the module output terminals of the multiplexing modules, and generating a comparison result indicating whether the result signals are completely identical.

[0139] S204: Output a signal representing the comparison result.

[0140] In the chip detection method of the embodiment of the present disclosure, the chip first obtains the detection signal (such as received through the detection input terminal), and synchronously transmits it to the module input terminal of each multiplexing module inside it, so that each multiplexing module will work synchronously according to the detection signal and output the result signal at its respective module output terminal; thereafter, the chip can compare the result signals of the module output terminals of each multiplexing module, and generate a comparison result indicating whether they are all the same (such as generated in the comparison module); finally, the chip can output a signal representing the comparison result (such as output through a comparison output pin).

[0141] Therefore, by analyzing the signal representing the comparison result, it can be determined whether the multiplexing modules of the chip are completely consistent (that is, the consistency of the multiplexing modules is determined).

[0142] In some embodiments, the detection signal includes a detection vector generated based on ATPG technology.

[0143] In some embodiments, the chip further includes a detection input pin, each detection input pin is connected to a module input terminal at the same position of each multiplexing module; Figure 8 , obtaining a detection signal, and synchronously transmitting the detection signal to the module input end of each multiplexing module (S201) includes:

[0144] S2011. Acquire a detection signal through a detection input pin, and synchronously transmit the detection signal to input terminals of each module connected to the detection input pin.

[0145] When the chip adopts the above shared-input technology, the detection signal obtained through a detection input pin can be synchronously transmitted to the module input terminals at the same position of each multiplexing module.

[0146] It should be understood that it is also feasible not to use the shared input terminal technology. In this case, the same detection signal needs to be provided simultaneously to multiple detection input pins corresponding to the module input terminals of each multiplexing module.

[0147] In some embodiments, reference Figure 8 After each multiplexing module outputs a result signal at its respective module output terminal for the detection signal (S202), the method further includes:

[0148] S205. Output result signal.

[0149] During the chip detection process, the chip can also output (such as by detecting the output pin output, or by comparing the output pin time-sharing output) the result signal (such as the result vector) of the specific multiplexing module, so as to determine whether the corresponding multiplexing module is faulty by analyzing the result signal (such as comparing the result vector with the standard vector), that is, determine the correctness of the multiplexing module.

[0150] It should be understood that the above process of determining the consistency of the reused module and the process of determining the correctness of the reused module are relatively independent, and there is no necessary execution order, relationship, etc. between the two.

[0151] For example, the process of determining the consistency and correctness of the multiplexing module is divided into two steps, that is, the detection signal is inputted twice, and the comparison result and the result signal are obtained by comparing the output key respectively, and there is no necessary order for obtaining the two.

[0152] Alternatively, when the chip has separate comparison output pins and detection output pins, the comparison result and the result signal can be obtained simultaneously when the test signal is input once.

[0153] For example, refer to Fig. 9First, randomly select a multiplexing module (multiplexing core) and obtain its result signal (result vector), compare it with the standard result (standard vector), if they are the same, it is determined that the multiplexing module is normal (such as determining that it is a Golden core); then, input the result signals of all multiplexing modules into the comparison module, analyze and compare the results to be 0 or 1, if it is 0, it means that the structures of all multiplexing modules are the same (that is, the same as the Golden core), so the core can be determined to have no fault, if it is 1, it means that the structure of the multiplexing module is different (that is, different from the Golden core), so it can be determined that the chip has a fault.

[0154] Alternatively, you can first check whether all reused modules are the same, and perform different subsequent steps based on the results:

[0155] (1) If they are the same, it can be approximately considered that the chip is not faulty; or, a multiplexing module can be further selected for correctness detection. If the multiplexing module is normal, it is confirmed that the chip is not faulty.

[0156] (2) If they are different, the chip can be directly determined to be faulty and the process ends (if fault location is not required); alternatively, the correctness of one or more multiplexing modules can be further tested to locate the fault.

[0157] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0158] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0159] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A chip, wherein: include: A plurality of multiplexing modules with the same structure, each of the multiplexing modules having a module input end and a module output end; A detection input pin, the detection input pin is connected to the module input end of each of the multiplexing modules, and is used to input a detection signal to the module input end; A comparison module, wherein the comparison module has an input end and an output end, the input end of the comparison module is connected to the module output end of each of the multiplexing modules, the comparison module is used to receive and compare the result signals output by each of the multiplexing modules at their respective module output ends for the detection signal, and output a comparison result representing whether the result signals of all the module output ends connected thereto are completely identical at the output end of the comparison module; A comparison output pin, wherein the comparison output pin is connected to an output end of the comparison module and is used to output a signal representing the comparison result.

2. The chip according to claim 1, wherein: Each of the detection input pins is connected to the module input terminals at the same position of each of the multiplexing modules, and is used to synchronously input the same detection signal to each of the module input terminals connected thereto.

3. The chip according to claim 1, wherein: Also includes: A detection output pin is connected to the module output end and is used to output a result signal of the module output end.

4. The chip according to claim 1, wherein: Also includes: A multiplexer module, wherein the multiplexer module has a plurality of input terminals, an output terminal, and a control terminal; The multiple input ends of the multiplexer module are connected to the multiple module output ends, the control end of the multiplexer module is connected to the output selection signal end, and the multiplexer module is used to select the module output end connected to the output end of the multiplexer module according to the signal of the output selection signal end.

5. The chip according to claim 4, wherein: Also includes: A detection output pin is connected to an output end of the multiplexer module.

6. The chip according to claim 4, wherein: Also includes: A processing module, wherein the processing module has an input end and an output end, wherein the input end of the processing module is respectively connected to the output end of the multiplexer module and the output end of the comparison module, and the output end of the processing module is connected to the comparison output pin, and the processing module is used for processing the result signal output by the output end of the multiplexer module to which it is connected and the comparison result output by the output end of the comparison module to which it is connected, and then outputting them to the comparison output pin.

7. The chip according to claim 6, wherein: The processing module comprises: A selection submodule is used for selecting a signal representing the comparison result or the result signal to be output from the comparison output pin.

8. The chip according to claim 6, wherein: The processing module comprises: A conversion submodule, the conversion submodule is used to generate a conversion comparison result according to the comparison result and the result signal as a signal representing the comparison result; wherein, when the comparison result represents that the result signals of all the module output ends are exactly the same, the conversion comparison result is the same as the signal of the module output end; when the comparison result represents that the result signals of all the module output ends are not exactly the same, the conversion comparison result is opposite to the signal of the module output end.

9. The chip according to claim 1, wherein: The comparison module comprises: A first AND gate unit, the first AND gate unit comprising a plurality of input terminals corresponding to the module output terminals connected to the comparison module, each of the input terminals being connected to its corresponding module output terminal; A first OR gate unit, the first OR gate unit comprising a plurality of input terminals connected to the comparison module in one-to-one correspondence with the module output terminals, each of the input terminals being connected to its corresponding module output terminal; A first XOR gate unit, wherein the first XOR gate unit comprises two input terminals respectively connected to the output terminal of the first AND gate unit and the output terminal of the first OR gate unit.

10. The chip according to claim 9, wherein: The comparison module further comprises a second OR gate unit and a second AND gate unit corresponding to at least part of the module output terminals; Each of the second OR gate units comprises two input terminals respectively connected to the corresponding module output terminal and the first shielding signal terminal, and an output terminal connected to the input terminal of the first AND gate unit; Each of the second AND gate units includes two input terminals respectively connected to the corresponding module output terminal and the inverted first shielding signal terminal, and an output terminal connected to the input terminal of the first OR gate unit: The second OR gate unit and the second AND gate unit corresponding to the same module output terminal are connected to the same first shielding signal terminal.

11. The chip according to claim 1, wherein: The comparison module comprises: A plurality of second XOR gate units, one of the module output ends connected to the comparison module is simultaneously connected to an input end of all the second XOR gate units, and the other module output ends are respectively connected to the other input end of each of the second XOR gate units in a one-to-one correspondence; A third OR gate unit, wherein the third OR gate unit comprises a plurality of input terminals respectively connected to the output terminals of the second XOR gate units.

12. The chip according to claim 11, wherein: The comparison module also includes a multiplexer unit corresponding to at least part of the module output terminals; The module output end is directly connected and inversely connected to the two input ends of the corresponding multiplexer unit, the output end of the multiplexer unit is connected to the corresponding second XOR gate unit, and the control end of the multiplexer unit is connected to the second shielding signal end.

13. A chip detection method, wherein: The chip includes a plurality of multiplexing modules with the same structure, each of the multiplexing modules has a module input end and a module output end, and the method includes: Acquire a detection signal, and synchronously transmit the detection signal to the module input end of each of the multiplexing modules; Each of the multiplexing modules outputs a result signal at a respective module output terminal in response to the detection signal; Comparing the result signals at the module output ends of the multiplexing modules, and generating a comparison result indicating whether the result signals are completely identical; A signal representing the comparison result is output.

14. The method according to claim 13, wherein: The chip further comprises a detection input pin, each of the detection input pins being connected to the module input terminal at the same position of each of the multiplexing modules; The acquiring of the detection signal and synchronously transmitting the detection signal to the module input end of each of the multiplexing modules includes: acquiring the detection signal through the detection input pin, and synchronously transmitting the detection signal to each of the module input ends connected to the detection input pin.

15. The method according to claim 13, wherein: After each of the multiplexing modules outputs a result signal at a respective module output terminal for the detection signal, the method further includes: The result signal is output.

16. The method according to claim 13, wherein: The detection signal includes a detection vector generated based on the automatic detection vector generation ATPG technology.

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