Data transmission control method, memory controller and memory

Abstract

The invention discloses a data transmission control method, a controller of a memory and the memory. The data transmission control method comprises the following steps: monitoring the data volume of a specified cache unit; when the data volume in the specified cache unit meets a pause condition, sending a pause instruction to the storage medium so as to pause data transmission between the controller and the storage medium; and when the data volume in the cache unit meets a recovery condition, sending a recovery instruction to the storage medium so as to recover data transmission between the controller and the storage medium. Through the method, the power consumption loss of the memory can be greatly reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of storage technology, and in particular to a data transmission control method, a memory controller, and a memory. Background Art

[0002] Solid State Drives (SSD) are storage hard disks made of solid-state electronic storage chips. The storage hard disk includes a controller and a storage medium. Currently, the most mainstream solid-state hard disk uses flash memory chips as storage media to store data.

[0003] The controller of the solid-state drive mainly performs read, write and erase operations on the storage medium. With the continuous improvement of semiconductor technology, the operating frequency of the flash memory chip has increased significantly, which also puts forward higher requirements on the speed at which the controller of the flash memory chip processes data. When the operating frequency of the flash memory chip controller cannot adapt to the operating frequency of the flash memory chip, the data transmission between the controller and the flash memory chip will be interrupted. In the prior art, in this case, the controller and the flash memory chip still maintain the data transmission state, causing a large power loss to the entire storage system. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a data transmission control method, a memory controller, and a memory to solve the existing problems.

[0005] According to a first aspect of an embodiment of the present disclosure, a data transmission control method is provided, which is applied to a controller of a memory, wherein the memory further includes a storage medium coupled to the controller, including:

[0006] Monitor the data volume of the specified cache unit;

[0007] When the amount of data in the designated cache unit meets the pause condition, sending a pause instruction to the storage medium to pause data transmission between the controller and the storage medium; and

[0008] When the amount of data in the cache unit meets the recovery condition, a recovery instruction is sent to the storage medium to recover the data transmission between the controller and the storage medium.

[0009] Optionally, the designated cache unit is a read data cache unit, and the amount of data in the designated cache unit meets the pause condition includes: for the read data cache unit, determining that the read data in the read data cache unit is greater than or equal to a first threshold;

[0010] The amount of data in the cache unit satisfies the recovery condition, including: for the read data cache unit, it is determined that the write data therein is less than a second threshold, and the first threshold is greater than the second threshold.

[0011] Optionally, the designated cache unit is a write data cache unit, and the amount of data in the designated cache unit meets the pause condition includes: for the write data cache unit, determining that the write data in the write data cache unit is less than or equal to a third threshold;

[0012] The amount of data in the cache unit satisfies the recovery condition, including: for a write data cache unit, determining that the write data therein is greater than a fourth threshold, and the third threshold is less than the fourth threshold.

[0013] Optionally, the storage medium and / or the controller switches from the data transmission state to the idle or standby state according to the pause instruction, and the storage medium and / or the controller switches from the idle or standby state back to the data transmission state according to the resume instruction.

[0014] Optionally, a cache unit of the controller stores pointers to the pause instruction and the resume instruction, so as to obtain the pause instruction or the resume instruction when needed.

[0015] According to a second aspect of an embodiment of the present disclosure, a controller of a memory is provided, the memory further comprising a storage medium coupled to the controller, the controller comprising:

[0016] A media controller, used for controlling data interaction with the storage medium;

[0017] A data monitoring module, configured to monitor the data volume of a designated cache unit, and send a pause request to the media controller when the data volume in the designated cache unit meets a pause condition; and send a resume request to the media controller when the data volume in the cache unit meets a resume condition;

[0018] The flash memory controller is further configured to send a pause instruction to the storage medium according to the pause request so that the storage medium enters an idle or standby state; and send a resume instruction to the storage medium according to the resume request so that the storage medium resumes to a data transmission state.

[0019] Optionally, the designated cache unit is a read data cache unit, and the amount of data in the designated cache unit meets the pause condition includes: for the read data cache unit, determining that the read data in the read data cache unit is greater than or equal to a first threshold;

[0020] The amount of data in the cache unit satisfies the recovery condition, including: for the read data cache unit, it is determined that the write data therein is less than a second threshold, and the first threshold is greater than the second threshold.

[0021] Optionally, the designated cache unit is a write data cache unit, and the amount of data in the designated cache unit meets the pause condition includes: for the write data cache unit, determining that the write data in the write data cache unit is less than or equal to a third threshold;

[0022] The amount of data in the cache unit satisfies the recovery condition, including: for a write data cache unit, determining that the write data therein is greater than a fourth threshold, and the third threshold is less than the fourth threshold.

[0023] Optionally, the storage medium and / or the controller switches from the data transmission state to the idle or standby state according to the pause instruction, and the storage medium and / or the controller switches from the idle or standby state back to the data transmission state according to the resume instruction.

[0024] According to a third aspect of an embodiment of the present disclosure, a memory is provided, including:

[0025] A controller as described in any of the above items and a storage medium coupled to the controller.

[0026] Optionally, the storage medium is a flash memory chip.

[0027] The data transmission control method for the controller of the memory provided by the embodiment of the present disclosure monitors the amount of data in the specified cache unit, and when the pause condition is met, issues a pause instruction to suspend the data transmission between the controller and the storage medium, and when the data transmission situation meets the recovery condition, issues a recovery instruction to resume the data transmission between the controller and the storage medium. More specifically, the controller and / or the storage medium will switch to an idle or standby state according to the pause instruction, in which state, the controller and / or the storage medium will turn off the functions of the components related to the transmission, and similarly, the controller and / or the storage medium will switch to a data transmission state according to the recovery instruction, in which state, the controller and / or the storage medium will turn on the functions of the components related to the transmission. In this way, the power consumption loss of the entire storage system can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the embodiments of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 A schematic block diagram of a solid state drive is shown;

[0030] Figure 2 It is a timing diagram of signals transmitted between a controller and a storage medium of a solid state hard disk in the prior art;

[0031] Figure 3A flow chart of a data transmission control method according to an embodiment of the present disclosure is shown;

[0032] Figure 4 is a schematic diagram of data communication between a controller and a storage medium of a solid state drive according to an embodiment of the present disclosure;

[0033] Figure 5 is a schematic block diagram of various modules of a controller related to an embodiment of the present disclosure;

[0034] Figure 6 Schematic diagram of state changes of a media controller according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0036] The following describes the embodiments of the present disclosure based on the embodiments, but the embodiments of the present disclosure are not limited to these embodiments. In the detailed description of the embodiments of the present disclosure below, some specific details are described in detail. For those skilled in the art, the embodiments of the present disclosure can be fully understood without the description of these details. In order to avoid confusing the essence of the embodiments of the present disclosure, well-known methods, processes, processes, components and circuits are not described in detail.

[0037] Unless the context clearly requires otherwise, the words "include", "comprising", and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the embodiments of the present disclosure, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In addition, in the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0038] The specific implementation of the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. However, before describing in detail, it should be pointed out that the various embodiments of the present disclosure are applicable to both solid-state drives and other storage products such as UFS.

[0039] Figure 1 A schematic block diagram of a solid state drive according to an embodiment of the present disclosure is shown.

[0040] like Figure 1As shown, the computer system 100 includes a host 110 and a solid state drive, the solid state drive includes a controller 120 and a storage medium 130, the controller 120 is connected to the host 110, and is used to receive read and write commands from the host 110. The controller 120 is connected to the storage medium 130, and is used to read data from the storage medium 130 and write data to the storage medium 130. The controller 120 is also used to return the read data to the host 110 according to the read command, or receive data to be written to the storage medium 130 from the host 110.

[0041] The controller 120 includes a host interface 121, a processor 123, a cache unit 124 and a media controller 128. The host interface 121 of the controller 120 is connected to the host 110 to transmit data and read and write commands. The processor 123 is connected to the host interface 121, the cache unit 124 and the media controller 128, and the processor 123 parses the read and write commands and performs read and write operations. The cache unit 124 is, for example, an SRAM, which is used to store a mapping table. The processor 123 is also used to execute the core software layer of memory control, namely FTL (flash translation layer, flash conversion layer). The FTL consists of several programs. The processor 123 executes the program so that when a read and write command is received, the command can be converted to complete the reading and writing of the storage medium 130, so that the file system and operating system of the host 110 can access the storage medium like accessing its own memory. The FTL also has the characteristics of supporting bad block management, wear leveling, garbage collection, power failure recovery, write balancing technology, etc.

[0042] The cache unit 124 may use SRAM and / or DRAM. In comparison, SRAM as a cache has a speed advantage, but is more expensive and has a smaller storage capacity per unit space. Accordingly, in order to improve the utilization of cache space, a DRAM-less solid-state drive (no DRAM) uses a two-level mapping table for address management, that is, the first-level mapping table is stored in the SRAM, and the second-level mapping table is stored in the storage medium 130.

[0043] The media controller 128 controls data transmission with the storage medium 130. When the storage medium 130 is, for example, a flash memory chip array, in order to improve data read and write performance, the media controller 128 can read and write the flash memory chips of the storage medium 130 in parallel via multiple channels (for example, CH0 and CH2), and each channel is connected to a group of flash memory chips.

[0044] For solid-state drives, the best state is that the operating frequencies of the controller 120 and the storage medium 130 are adapted. However, in reality, due to reasons such as the increase in the operating frequency of the flash memory chip, the operating frequency of the controller 120 may be lower than the operating frequency of the storage medium 130. In this case, for write operations, when the storage medium 130 is waiting to receive write data, the media controller 128 may not be ready to send the write data. For read operations, when the storage medium 130 is continuously returning data, the read data in the cache corresponding to the media controller 128 may not have been processed, and thus more read data cannot be received. At this time, the data transmission between the controller 120 and the storage medium 130 has actually stopped, but the interface between the controller 120 and the storage medium 130 is still in a data transmission state. Although there is no data transmission in this state, the entire storage system still has considerable power consumption.

[0045] Figure 2 It is a timing diagram of the signals transmitted between the controller and the storage medium of the solid-state hard disk of the prior art. Referring to the figure, when no data communication is performed (corresponding to other stages in the figure), the controller and the storage medium are in an idle or standby state. At this time, except for the necessary control signals, other signals are in a floating state, so the IO power consumption is the lowest. Then the controller sends a "start data transmission" command to the storage medium, and then receives a "confirmation" feedback from the storage medium, thereby establishing a communication link. This process corresponds to the "start transmission" stage in the figure. Then the controller sends data to the storage medium or receives data from the storage medium. This process corresponds to the "transmission stage" stage in the figure. After the data transmission is completed, the controller can send a "end data transmission" command to the storage medium, and then receive a "confirmation" feedback from the storage medium to terminate the data transmission. This process corresponds to the "end stage" stage in the figure. Among them, the control signal is used to control the state switching of the IO bus and send commands to the storage medium, and the synchronous clock signal and the data signal are used to transmit data.

[0046] Continue to refer Figure 2 As shown, assuming that the data transmission has actually stopped at the stage indicated by INTER, according to the prior art, the synchronization clock signal and the data signal have not stopped transmitting, the data sending end (controller or storage medium) still maintains the driving of the IO bus, and the data receiving end (storage medium or controller) still maintains the power consumption of the receiving circuit, so the system as a whole still maintains the high power consumption state of the data transmission state.

[0047] In order to reduce the high power consumption of the system, the data transmission between the controller and the storage medium can be suspended in the INTER stage, so as to reduce the power consumption loss of the whole system. However, if the data transmission is frequently suspended, the data transmission between the controller 120 and the storage medium 130 will also have a negative impact.

[0048] Based on this, an embodiment of the present disclosure proposes a data transmission control method applied to a controller of a memory. Figure 3 The flow chart of the method is given, which specifically includes the following steps.

[0049] In step S301, the data volume of a designated cache unit is monitored.

[0050] In step S302, it is determined whether the amount of data in the designated cache unit meets the pause condition. If so, step S303 is executed, otherwise, step S304 is executed.

[0051] In step S303, a pause instruction is sent to the storage medium to pause data transmission between the controller and the storage medium.

[0052] In step S304, a recovery instruction is sent to the storage medium to transfer data between the storage media.

[0053] In this embodiment, the controller monitors the amount of data in the designated cache unit. When it is determined based on the amount of data that a data interruption has occurred or is about to occur, if it is determined that a transmission suspension condition is met, a pause instruction is sent to the storage medium. After the storage medium receives the pause instruction, the storage medium switches the storage medium from a data transmission state to a non-data transmission state (e.g., idle or standby). At the same time, the controller also switches from a data transmission state to a non-data transmission state (e.g., idle or standby). Thus, the IO interface also switches to a non-data transmission state, thereby suspending the data transmission between the controller and the storage medium. If it is determined that a recovery condition is met, a recovery instruction is initiated to the storage medium. After receiving the recovery request, the storage medium recovers to a data transmission state. At the same time, the controller can also switch from a non-data transmission state (e.g., idle or standby) to a data transmission state. Thus, the IO interface also switches back to a data transmission state, thereby recovering the data transmission between the controller and the storage medium.

[0054] Figure 4 The present invention is a schematic diagram of data communication between the controller and the storage medium of the solid-state hard disk of the embodiment of the present invention. As shown in the reference figure, in the transmission stage between the start of transmission and the end of transmission, if the controller detects that the amount of data in the designated cache unit meets the pause condition, the controller sends a pause instruction to the storage medium to make the storage medium enter the idle or standby state from the data transmission state, and the controller also enters the idle or standby state from the data transmission state, so that the data transmission between the controller and the storage medium can be suspended. If the controller detects that the amount of data in the designated cache unit meets the recovery condition, the controller sends a recovery instruction to the storage medium to make the storage medium return to the data transmission state, and the controller also returns to the data transmission state, so that the data transmission between the controller and the storage medium can be restored.

[0055] In this case, when the data transmission between the controller and the storage medium is suspended, the synchronous clock signal and data signal between the two will stop transmitting, and the data sending end (controller or storage medium) stops driving the IO bus, and the data receiving end (storage medium or controller) stops the power consumption of the receiving circuit, thereby saving the power loss caused by the IO bus being in a transmission state but not actually transmitting data. If the storage medium is a flash memory chip, when it is in an idle or standby state, the driving and ODT (ODT is used to improve signal stability) functions will be turned off, and the power supply of the comparison amplifier and other circuits in the IO input direction will be turned off to reduce power consumption. When it returns to the data transmission state, the driving and ODT (ODT is used to improve signal stability) functions will be turned on, and the power supply of the comparison amplifier and other circuits in the IO input direction will be turned on.

[0056] Figure 5 is a schematic block diagram of a controller of a solid state drive according to an embodiment of the present disclosure. Figure 5 As shown, the controller 500 includes a data monitoring module 510, a read data cache unit 511, a write data cache unit 512 and a controller data processing module 513. It should be understood that only modules related to the embodiment of the present disclosure are shown in the controller 500. Figure 1 As shown, one or more of the controller data processing module 513, the read data cache unit 511, the write data cache unit 512 and the data monitoring module are integrated into Figure 1 In a module of the controller 120 shown, a new module may be formed and arranged outside each module, for example, the controller data processing module 513 may be integrated into the media controller 128. Furthermore, each module may be a computer program composed of computer executable instructions, stored in the controller 400 in the form of software or firmware, and may be part of the FTL.

[0057] The data monitoring module 410 is used to monitor the data volume of the designated cache unit, and when the data volume in the designated cache unit meets the pause condition, send a pause request to the controller data processing module 513, and when the data volume in the designated cache unit meets the resume condition, send a resume request to the controller data processing module 513. When receiving the pause request, the controller data processing module 513 sends a pause instruction to the storage medium 130 according to the pause request to suspend data transmission. The specific operation is, for example, that the storage medium 130 enters an idle or standby state, and at the same time, it can also enter an idle or standby state from a data transmission state, and shut down unnecessary components in the idle or standby state; then, after receiving the resume request, send a resume instruction to the storage medium 130 according to the resume request to resume data transmission. The specific operation is, for example, that the storage medium 130 returns to a data transmission state, and at the same time, it can also return to a data transmission state, and start the components required in the data transmission state.

[0058] As shown in the figure, the designated cache unit may include a read data cache unit 511 and a write data cache unit 512. The write data cache unit 512 is used to cache write data to be sent to the storage medium, and the read data cache unit 511 is used to cache data received from the storage medium.

[0059] When the designated cache unit monitored by the data monitoring module 410 is the read data cache unit 511, the data monitoring module 410 sends a pause request to the controller data processing module 513 when it is detected that the read data in the read cache unit is greater than or equal to the first threshold value. When the controller data processing module 513 receives the pause request, it issues a pause instruction, and the storage medium 500 thereby pauses the read data transmission between the storage medium 500 and the controller data processing module 513. The data monitoring module 410 continues to monitor, and when it is detected that the read data in the read cache unit is less than the second threshold value, it sends a resume request to the controller data processing module 513. When the controller data processing module 513 receives the resume request, it issues a resume instruction, and the storage medium 500 resumes the read data transmission between the storage medium 500 and the controller data processing module 513.

[0060] For the read data cache unit 511, if the amount of read data therein is greater than or equal to the first threshold value, the first threshold value is generally a very large value, indicating that data blocking occurs in the read data. At this time, although the system still maintains the data transmission state, the controller data processing module 513 has no ability to continue to receive or can only receive read data intermittently. Therefore, the controller data processing module 513 determines that the transmission suspension condition is met, and then sends a pause instruction to the storage medium 130 to suspend the read data transmission. When the amount of read data in the read data cache unit 511 is less than the second threshold value, the controller data processing module 513 determines that the transmission recovery condition is met, and then sends a recovery instruction to the storage medium 130 to resume the read data transmission. The second threshold value is generally a smaller value, indicating that there is enough free space to resume data transmission. The second threshold value cannot be too large or too small. If it is too small, the data recovery waiting time will be too long, introducing a longer data transmission delay, or causing too much data to be filled in the cache unit, blocking new data. If the second threshold value is too large, it will cause frequent interruptions in data transmission, insert too many pause and resume commands in the transmission, resulting in reduced bandwidth utilization, reduced data transmission bandwidth, and even increased power consumption due to the pause and resume commands. Therefore, the first threshold value is generally greater than the second threshold value.

[0061] When the designated cache unit monitored by the data monitoring module 410 is the write data cache unit 512, the data monitoring module 410 sends a pause request to the controller data processing module 513 when it detects that the write data in the write cache unit is less than or equal to the third threshold value. When the controller data processing module 513 receives the pause request, it issues a pause instruction, and the storage medium 500 thus suspends the write data transmission between the controller data processing module 513. The data monitoring module 410 continues to monitor, and when it detects that the write data in the read cache unit is greater than the fourth threshold value, it sends a resume request to the controller data processing module 513. When the controller data processing module 513 receives the resume request, it issues a resume instruction, and the storage medium 500 resumes the write data transmission between the controller data processing module 513. For the write data cache unit 512, if the amount of the write data in it is less than or equal to the third threshold value, the third threshold value is generally a very small value, indicating that the write data is not ready yet. If the write data is sent at this time, the transmission process of the write data is also intermittent. Therefore, the controller data processing module 513 determines that the transmission pause condition is currently met, and then issues a pause instruction to the storage medium 130 to suspend the write data transmission. When the amount of read data in the write data cache unit 512 is less than the fourth threshold, the controller data processing module 513 determines that the transmission recovery condition is met, and then sends a recovery instruction to the storage medium 130 to resume the read data transmission. The fourth threshold is generally a larger value, indicating that the data transmission can be resumed; the fourth threshold cannot be too large or too small. If it is too large, it will cause the data recovery waiting time to be too long, introduce a longer data transmission delay, or cause insufficient remaining space in the cache unit, blocking new data; if the fourth threshold is too small, it will cause frequent interruptions in data transmission, insert too many pause and resume commands in the transmission, resulting in reduced bandwidth utilization, reduced data transmission bandwidth, and even increased power consumption due to pause and resume commands. Therefore, the third threshold is generally smaller than the fourth threshold. For example, the condition for pausing write data transmission is that the data in the cache is empty, that is, the third threshold is set to 0, and the fourth threshold for resuming data transmission may be half of the cache space, that is, the fourth threshold is set to 50%.

[0062] By monitoring the data volume of a designated cache unit and determining whether to suspend data transmission based on the data volume, it is possible to avoid the situation where data transmission is immediately performed as soon as data is detected, resulting in frequent exits and reentry into data suspension.

[0063] In some embodiments, the read data cache unit and the write data cache unit are first-in-first-out queues (FIFOs). For the FIFO as the read data cache unit, the read data that first enters the FIFO is first transmitted to the host, and for the FIFO as the write data cache unit, the write data that first enters the FIFO is first transmitted to the storage medium. Of course, it is not limited to that either the read data cache unit or the write data cache unit must be a FIFO.

[0064] In some embodiments, the first threshold and the second threshold as the threshold are configured through internal registers. These internal registers can be configured when the solid-state drive is initialized. The first threshold and the second threshold as the threshold have no specific range and should be adjusted according to the actual application: if the threshold is too small, the data is always suspended and restored, resulting in performance degradation; if the threshold is too large, it takes a long time to wait, and the data transmission delay becomes longer. By reasonably controlling the threshold, the optimal balance between power saving and data transmission delay can be achieved.

[0065] Figure 6 The media controller (which may also be Figure 4 Schematic diagram of the state change of the controller data processing module 513). Figure 6 More details of this embodiment are shown.

[0066] refer to Figure 6 First, the media controller is in a normal working state (S10), and determines whether a pause request is received (S11). When it is determined that a pause request is received, the pause process (S12) is entered. The pause process S12 may include checking whether the amount of data in the specified cache unit meets the pause condition according to the pause request. The pause process S12 may also include maintaining some field data, such as recording the physical address of the latest data. The pause process may also include issuing a pause instruction, and then continue with step S13. S13 determines whether the pause instruction is issued. If so, continue to wait for recovery (S14), determine whether a recovery request is received (S15), if so, determine whether the recovery condition is met (S16), if the recovery condition is met, issue a recovery instruction to the storage medium, and then determine whether the recovery instruction is issued (S18), and then return to the normal working state (S10).

[0067] It should be pointed out that the controller of the solid-state drive needs to be adapted to support storage media from all mainstream manufacturers (for example, flash memory chip manufacturers include YMTC, Micron, Hynix, KIOXIA, etc.), and the data transmission interruption processing methods of different manufacturers are different. The control method adopted in this embodiment can write the pointers of the adapted pause and resume instructions into the table of the cache unit inside the controller during the initialization phase of the solid-state drive. When it is needed to be sent to the storage medium later, the pause or resume instruction will be taken out of the table of the cache unit according to the information in the instruction set and sent out. In this way, the value of the cache unit table is modified or the instruction set is modified so that the pause instruction and the resume instruction are loosely coupled with the storage medium, which is conducive to the controller manufacturer to integrate the storage media of different manufacturers, and the universality and reliability are stronger.

[0068] In addition, an embodiment of the present disclosure further provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above embodiments when executing the computer program.

[0069] Furthermore, the embodiments of the present disclosure further provide a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above embodiments are implemented.

[0070] The embodiments according to the embodiments of the present disclosure are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present disclosure, so that those skilled in the art can make good use of the embodiments of the present disclosure and the modified use based on the embodiments of the present disclosure. The embodiments of the present disclosure are limited only by the claims and their full scope and equivalents.

Claims

1. A data transmission control method, applied to a controller of a memory, wherein the memory further comprises a storage medium coupled to the controller, the data transmission control method comprising: Monitor the data volume of the specified cache unit; When the amount of data in the designated cache unit meets the pause condition, sending a pause instruction to the storage medium to pause data transmission between the controller and the storage medium; as well as When the amount of data in the cache unit meets the recovery condition, a recovery instruction is sent to the storage medium to recover the data transmission between the controller and the storage medium.

2. The data transmission control method according to claim 1, wherein: If the designated cache unit is a read data cache unit, the amount of data in the designated cache unit satisfies the pause condition, including: for the read data cache unit, determining that the read data in the read data cache unit is greater than or equal to a first threshold; The amount of data in the cache unit satisfies the recovery condition, including: for the read data cache unit, it is determined that the write data therein is less than a second threshold, and the first threshold is greater than the second threshold.

3. The data transmission control method according to claim 1, wherein: If the designated cache unit is a write data cache unit, the amount of data in the designated cache unit satisfies the pause condition, including: for the write data cache unit, determining that the write data in the write data cache unit is less than or equal to a third threshold; The amount of data in the cache unit satisfies the recovery condition, including: for a write data cache unit, determining that the write data therein is greater than a fourth threshold, and the third threshold is less than the fourth threshold.

4. The data transmission control method according to claim 1, wherein: The storage medium and / or the controller switches from the data transmission state to the idle or standby state according to the pause instruction, and the storage medium and / or the controller switches from the idle or standby state back to the data transmission state according to the resume instruction.

5. The data transmission control method according to claim 1, wherein: The designated table of the cache unit of the controller stores pointers to the pause instruction and the resume instruction, so as to obtain the pause instruction or the resume instruction when needed.

6. A memory controller, the memory further comprising a storage medium coupled to the controller, the controller comprising: A media controller, used for controlling data interaction with the storage medium; A data monitoring module, configured to monitor the data volume of a designated cache unit, and send a pause request to the media controller when the data volume in the designated cache unit meets a pause condition; and send a resume request to the media controller when the data volume in the cache unit meets a resume condition; The media controller is further configured to send a pause instruction to the storage medium according to the pause request, so as to pause data transmission between the controller and the storage medium; And sending a recovery instruction to the storage medium according to the recovery request to recover the data transmission between the controller and the storage medium.

7. The controller according to claim 6, wherein: If the designated cache unit is a read data cache unit, the amount of data in the designated cache unit satisfies the pause condition, including: for the read data cache unit, determining that the read data in the read data cache unit is greater than or equal to a first threshold; The amount of data in the cache unit satisfies the recovery condition, including: for the read data cache unit, it is determined that the write data therein is less than a second threshold, and the first threshold is greater than the second threshold.

8. The controller according to claim 6, wherein: If the designated cache unit is a write data cache unit, the amount of data in the designated cache unit satisfies the pause condition, including: for the write data cache unit, determining that the write data in the write data cache unit is less than or equal to a third threshold; The amount of data in the cache unit satisfies the recovery condition, including: for a write data cache unit, determining that the write data therein is greater than a fourth threshold, and the third threshold is less than the fourth threshold.

9. The controller according to claim 6, wherein: The storage medium and / or the controller switches from the data transmission state to the idle or standby state according to the pause instruction, and the storage medium and / or the controller switches from the idle or standby state back to the data transmission state according to the resume instruction.

10. A memory comprising: The controller according to any one of claims 6 to 9 and a storage medium coupled to the controller.

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