Error injection test method, device, equipment and medium

Abstract

The invention relates to the technical field of computers, and discloses an error injection test method and device, equipment and a medium, and the method comprises the steps: obtaining a pre-configured error injection rule; analyzing the error injection rule to obtain an error injection behavior identifier and indication information corresponding to an error injection behavior; when the indication information is first indication information indicating to execute error injection operation, according to the error injection behavior identifier, matching an error execution instruction corresponding to the error injection behavior identifier from a pre-constructed resource pool; executing an error injection operation according to the error execution instruction, and obtaining error indication information and first state information; and storing the error indication information and the first state information. By directly performing the error injection test on the hardware level, hardware faults and extreme conditions can be simulated more truly, so that the fault-tolerant capability of the SSD equipment can be evaluated more accurately. The automatic error injection test process can reduce manual intervention and improve the test efficiency and accuracy.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an injection error testing method, device, equipment and medium. Background Art

[0002] Redundant Array of Independent Disks (RAID) technology works by combining multiple disks into a logical unit, providing data mirroring, striping, parity checking and other functions, thereby enhancing data security and access speed. However, the RAID system is not invulnerable, and it still faces risks such as hardware failure, data corruption, and system crash. In order to ensure the reliability of the RAID system, injection error testing has become an important means to evaluate and verify the fault tolerance of RAID cards.

[0003] Traditional fault injection testing methods usually rely on software-level simulation, such as simulating faults by modifying file system metadata or injecting I / O errors. However, these methods have limitations and cannot fully simulate hardware faults or extreme conditions that the system may encounter during power on and off.

[0004] With the rise of solid state drive (SSD) technology, the performance of storage devices has been significantly improved. SSD uses flash memory as the storage medium, which has faster read and write speeds, lower latency, and higher durability than traditional mechanical hard disks. However, the introduction of SSD also brings new challenges to RAID systems. For example, the number of writes to SSD is limited, and improper write operations may cause data loss. In addition, the firmware and interface of SSD may also become failure points. Summary of the invention

[0005] In view of this, the present invention provides an error injection test method, device, equipment and medium to solve the problems in traditional error injection test technology, such as the inability to accurately inject and capture errors between the test equipment and the SSD, and the inability to fully simulate hardware failures or extreme situations that the system may encounter during power on and off.

[0006] In a first aspect, the present invention provides an injection error testing method, which is performed by a solid state hard disk device, and the method comprises:

[0007] Get preconfigured error injection rules;

[0008] Parse the error annotation rule to obtain the error annotation behavior identifier and indication information corresponding to the error annotation behavior;

[0009] When the instruction information is the first instruction information indicating the execution of the error injection operation, according to the error injection behavior identifier, the error execution instruction corresponding to the error injection behavior identifier is matched from the pre-built resource pool;

[0010] Execute an error-notification operation according to the error execution instruction, and obtain error indication information and first status information corresponding to the solid-state hard disk device;

[0011] The error indication information and the first state information are stored.

[0012] The present invention provides a method for testing injection errors, which has the following advantages:

[0013] A preconfigured error injection rule is obtained, wherein the error injection rule includes an error injection behavior identifier and indication information corresponding to the error injection behavior. When the indication information indicates to execute the error injection behavior, an error execution instruction corresponding to the error injection behavior identifier is obtained from a pre-purchased resource pool according to the registered behavior identifier, and the error execution instruction is applied to the solid-state hard disk device to generate error indication information and first state information corresponding to the solid-state hard disk device. Then the error indication information and the first state information are stored. In this method, by directly performing an error injection test at the hardware level, hardware failures and extreme situations can be simulated more realistically, thereby more accurately evaluating the fault tolerance of the SSD device. The automated error injection test process can reduce manual intervention and improve test efficiency and accuracy. Storing error indication information and state information is helpful for subsequent rapid diagnosis and problem solving, and improves the maintainability of the system. Moreover, by capturing and storing errors in the above manner, higher test accuracy can be achieved. By simulating and capturing various complex errors, the fault tolerance and recovery capability of the test equipment system in actual operation are evaluated to ensure that the system can be restored in time and maintain stable operation when an error occurs.

[0014] In an optional embodiment, the method further includes:

[0015] When the instruction information is second instruction information for instructing to adjust the erroneous execution instruction in the resource pool, parsing the error annotation rule also includes acquiring an adjustment rule corresponding to the erroneous execution instruction in the resource pool;

[0016] According to the adjustment rules, the error execution instructions in the resource pool are adjusted;

[0017] The error execution instructions in the resource pool belong to different error types, and different error execution instructions correspond to different impact levels.

[0018] Adjustment operations include:

[0019] Obtaining from the resource pool an error type corresponding to the erroneous execution instruction and an impact level corresponding to the erroneous execution instruction;

[0020] Determine the type of adjustment operation according to the adjustment rule, wherein the adjustment operation type includes one or more of adding an erroneous execution instruction, deleting an erroneous execution instruction, or modifying an erroneous execution instruction;

[0021] An adjustment operation is performed on the erroneous execution instruction in the resource pool according to the type of the adjustment operation, the error type corresponding to the erroneous execution instruction, and / or the impact level corresponding to the erroneous execution instruction.

[0022] Specifically, in this method, the error execution instructions in the resource pool can be flexibly adjusted according to specific needs using adjustment rules to adapt to different test scenarios and requirements. It can also be adjusted for specific error types and impact levels, thereby improving the pertinence and effectiveness of the test. By adding, deleting or changing error execution instructions, the test cases can be optimized to better evaluate the fault tolerance of the SSD device. It is also possible to adjust the error execution instructions in a timely manner according to the emergence of new technologies or new situations to ensure the comprehensiveness and accuracy of the test. In the above method, because the error execution instructions are adjusted directly in the resource pool, the work of repeatedly writing or modifying the error execution instructions can be avoided, thereby improving the test efficiency. This method can also help to conduct more refined tests and discover potential problems and weak links. By reasonably adjusting the error execution instructions, the reliability of the SSD device is further enhanced. Better manage the error execution instructions in the resource pool and improve the utilization efficiency of resources.

[0023] In an optional implementation manner, storing the error indication information and the first state information specifically includes:

[0024] The error indication information and the first state information are stored in the persistent memory area.

[0025] Specifically, the persistent memory area is usually non-volatile, and the data stored in it will not be lost even if the system is powered off or restarted. Storing error indication information and status information here ensures the persistence of error indication information and status information, which is convenient for subsequent fault diagnosis and analysis. Reduce the risk of data loss or damage. Furthermore, the access speed of persistent memory is usually faster than that of traditional storage media (such as hard disks). Storing information in the persistent memory area can increase the speed of reading and writing data, which helps to quickly obtain and process error-related data. Furthermore, the persistent memory area can be used to store the history of error information, which is convenient for tracing and analyzing the status and problems of the system at different time points. This is very helpful for long-term system maintenance and optimization. After the system is powered on again, the controller of the test equipment can read the complete error code and status information from the persistent memory area to ensure that the test can be carried out continuously. Through the persistent memory area, the data integrity and system stability of the test equipment under long-term operation and frequent power on and off can be verified.

[0026] In an optional implementation, the first indication information is preset indication information other than 0xe0, and the second indication information is 0xe0.

[0027] In an optional embodiment, the method further includes:

[0028] When a preset abnormal situation occurs, an error execution instruction corresponding to the preset abnormal situation is matched from the resource pool;

[0029] Execute an error-notification operation according to an error execution instruction corresponding to a preset abnormal situation, and obtain error indication information corresponding to the preset abnormal situation and second state information corresponding to the solid-state hard disk device;

[0030] The error indication information corresponding to the preset abnormal situation and the second state information corresponding to the solid state disk device are stored in the persistent memory area.

[0031] Specifically, when a preset abnormal situation occurs, the corresponding error execution instruction can be quickly matched from the resource pool, and the error injection operation can be performed in time to reduce the impact time of the system failure. By matching the corresponding error execution instruction according to the preset abnormal situation, more targeted processing can be carried out to improve the efficiency of problem solving. The error indication information and server status information corresponding to the preset abnormal situation are stored in the persistent memory area to ensure the persistence and traceability of the data, which is convenient for subsequent fault analysis and diagnosis. By processing and storing information of preset abnormal situations, the system can be continuously optimized to improve the stability and reliability of the system. Analyzing the stored error indication information and status information can help predict possible failures and take preventive measures in advance. For example, if an abnormal situation occurs in the server in the future, relevant information can be quickly obtained, which helps to quickly restore the system and reduce the time of business interruption.

[0032] In an optional implementation, the preset abnormal situation includes: abnormal power failure of the system, or abnormal power off of the system.

[0033] Specifically, by simulating and capturing various complex errors, the fault tolerance and recovery capability of the test equipment system in actual operation are evaluated to ensure that the system can recover in time and maintain stable operation when an error occurs. Through power-on and power-off tests, the recovery capability of the test equipment system in the event of unexpected power outages and power fluctuations is verified to ensure the stability and reliability of the system in harsh environments.

[0034] In an optional implementation, after the preset abnormal situation is restored, the method further includes:

[0035] The data stored in the persistent memory area is recovered to generate recovered data, so that the independent disk redundant array can subsequently verify the error handling capability and data recovery capability of the independent disk redundant array in the event of abnormal power failure based on the data stored in the persistent memory area and the recovered data.

[0036] Specifically, by comparing the stored data and the recovered data in the persistent memory area, the error handling capability of the RAID card in the event of an abnormal power failure can be verified. If the recovered data is consistent with the stored data, it means that the RAID card can correctly handle the abnormal power failure and ensure the integrity of the data. Verifying the error handling capability and data recovery capability of the RAID card helps to evaluate the reliability of the system. If the RAID card can correctly handle errors and recover data in abnormal situations, the reliability of the entire system will be improved. If problems such as data inconsistency or recovery failure are found during the verification process, potential problems of the RAID card can be discovered in time, and corresponding measures can be taken to improve and optimize it. Based on the verification results, the configuration of the RAID card can be optimized to improve its performance and reliability in abnormal situations.

[0037] In a second aspect, the present invention provides an injection error testing device, which corresponds to a solid state hard disk device, comprising:

[0038] An acquisition module is used to obtain pre-configured error annotation rules;

[0039] A parsing module, used to parse the error-annotation rule to obtain the error-annotation behavior identifier and indication information corresponding to the error-annotation behavior;

[0040] A matching module, configured to match an error execution instruction corresponding to the error injection behavior identifier from a pre-built resource pool according to the error injection behavior identifier when the indication information is the first indication information indicating the execution of the error injection operation;

[0041] A processing module, configured to execute an error injection operation according to the error execution instruction, and obtain error indication information and first status information corresponding to the solid state hard disk device;

[0042] The error indication information and the first state information are stored.

[0043] The present invention provides a mis-injection testing device, which has the following advantages:

[0044] A preconfigured error injection rule is obtained, wherein the error injection rule includes an error injection behavior identifier and indication information corresponding to the error injection behavior. When the indication information indicates to execute the error injection behavior, an error execution instruction corresponding to the error injection behavior identifier is obtained from a pre-purchased resource pool according to the registered behavior identifier, and the error execution instruction is applied to the solid-state hard disk device to generate error indication information and first state information corresponding to the solid-state hard disk device. Then the error indication information and the first state information are stored. In this method, by directly performing an error injection test at the hardware level, hardware failures and extreme situations can be simulated more realistically, thereby more accurately evaluating the fault tolerance of the SSD device. The automated error injection test process can reduce manual intervention and improve test efficiency and accuracy. Storing error indication information and state information is helpful for subsequent rapid diagnosis and problem solving, and improves the maintainability of the system. Moreover, by capturing and storing errors in the above manner, higher test accuracy can be achieved. By simulating and capturing various complex errors, the fault tolerance and recovery capability of the test equipment system in actual operation are evaluated to ensure that the system can be restored in time and maintain stable operation when an error occurs.

[0045] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the injection error testing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0046] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the injection error testing method of the first aspect or any corresponding embodiment thereof.

[0047] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the error injection testing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 It is a flow chart of a method for testing injection errors provided by an embodiment of the present invention;

[0050] Figure 2It is a connection diagram of the injection error test system provided by the present invention;

[0051] Figure 3 It is a flowchart of another injection error testing method provided by an embodiment of the present invention;

[0052] Figure 4 It is a flowchart of another injection error testing method provided by an embodiment of the present invention;

[0053] Figure 5 It is a schematic diagram of the overall process structure of error injection and feedback provided by the present invention;

[0054] Figure 6 It is a structural block diagram of an injection error testing device provided by an embodiment of the present invention;

[0055] Figure 7 It is a schematic diagram of the hardware structure of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0057] In today's information age, the importance of data is becoming increasingly prominent, and the development of data storage technology has therefore become key to the field of information technology. Data storage not only needs to consider the expansion of storage capacity, but also needs to ensure the security and reliability of data. In order to achieve these goals, storage system designers have adopted a variety of technologies, among which Redundant Array of Independent Disks (RAID) technology has been widely used due to its balance in data redundancy, performance improvement and cost-effectiveness.

[0058] RAID technology works by combining multiple disks into a logical unit, providing data mirroring, striping, parity checking and other functions, thereby enhancing data security and access speed. However, the RAID system is not invulnerable, and it still faces risks such as hardware failure, data corruption, and system crash. In order to ensure the reliability of the RAID system, injection error testing has become an important means to evaluate and verify the fault tolerance of RAID cards.

[0059] Fault injection testing is a testing method that simulates fault conditions to detect the behavior and performance of the system under abnormal conditions. Through fault injection testing, potential problems can be discovered and fixed, improving the stability and reliability of the system. Traditional fault injection testing methods usually rely on simulation at the software level, such as simulating faults by modifying file system metadata or injecting I / O errors. However, these methods have limitations. They cannot fully simulate hardware failures or extreme conditions that the system may encounter during power on and off.

[0060] With the rise of solid-state drive (SSD) technology, the performance of storage devices has been significantly improved. SSD uses flash memory as the storage medium, which has faster read and write speeds, lower latency, and higher durability than traditional mechanical hard drives. However, the introduction of SSDs also brings new challenges to RAID systems. For example, SSDs have a limited number of writes, and improper write operations may cause data loss. In addition, the firmware and interface of SSDs may also become failure points.

[0061] In order to meet these challenges, a new error injection test method is needed that can fully simulate various fault conditions between SSD and test equipment, including hardware failure, firmware error, interface problem and errors during system power on and off. This requires the test method to be able to not only inject errors at the software level, but also simulate at the hardware level to ensure the comprehensiveness and accuracy of the test.

[0062] To solve the above problems, an embodiment of the present invention provides an injection error test embodiment. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system (computer device) including a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0063] In this embodiment, a method for testing injection errors is provided, which can be used for the above-mentioned terminal equipment, such as mobile phones, tablet computers, etc. Figure 1 is a flow chart of a method for testing injection errors provided by an embodiment of the present invention, such as Figure 1 As shown, the method is applied to an injection error test system, which includes a server, a RAID card and an SSD. Taking the Non-Volatile Memory Express (NVMe) SSD device as an example, the NVMe SSD device adopts a multi-core system and mainly runs in a server environment. The RAID card device can be adapted on the server.

[0064] The process includes the following steps:

[0065] Step S101, obtaining a preconfigured error annotation rule.

[0066] Specifically, the preconfigured error injection rule is forwarded to the SSD device by the RAID card after receiving the error injection rule sent by the server.

[0067] First, the server is turned on and the device runs normally. Because the device in the embodiment of the present application is an NVMe SSD device, the data transmission protocol adopted is the NVMe protocol. At the same time, in order to facilitate users and test personnel to operate more conveniently, it is necessary to design a customized NVMe tool in the server to issue commands. Because the customized NVMe tool needs to be compatible with the standard NVMe tool, relevant operation codes are added to achieve compatibility. The NVMe tool will obtain the data according to the parameters entered by the tester, and then encapsulate the data and issue it. Specifically, the issuance here is from the server to the RAID card. Among them, the customized NVMe tool sends commands to call the driver interface of the RAID card. The data mentioned here is the configured error injection rules. Among them, the parameters include, for example, the error injection behavior identifier and the indication information corresponding to the error injection behavior.

[0068] After receiving the encapsulation command, the RAID card parses the encapsulation command, extracts the error injection rule, and then encapsulates the error injection rule and sends it to the NVMe SSD device through the NVMe driver.

[0069] See Figure 2 As shown, Figure 2 The connection diagram of the injection error test system is shown in the figure, and the injection error test system includes a server, a test device and an NVMe SSD device. The test device in the embodiment of the present application can be understood as a RAID card in a specific example. Among them, the server includes a host computer customization tool, that is, a customized NVMe tool, and a driver module for calling the driver interface of the RAID card to realize data sending. The test device may include a command receiving module and an NVMe driver, wherein the command receiving module is used to receive the data sent from the server mentioned above to the RAID card.

[0070] Step S102: parsing the wrong annotation rule to obtain the wrong annotation behavior identifier and indication information corresponding to the wrong annotation behavior.

[0071] Specifically, as described above, the parameters configured in the error injection rule include the error injection behavior identifier and the indication information corresponding to the error injection behavior, etc., so these data can be obtained after parsing.

[0072] Step S103: when the indication information is the first indication information indicating the execution of the error injection operation, according to the error injection behavior identifier, an error execution instruction corresponding to the error injection behavior identifier is matched from a pre-built resource pool.

[0073] Specifically, the NVMe SSD device parses the pre-configured error injection rule and identifies the indication information. If the indication information does not indicate the execution of the error injection behavior, no processing is performed and the command is directly transmitted to the subsequent module for processing. If it is determined that the error injection behavior needs to be executed according to the indication information, it is necessary to determine what operation needs to be performed according to the specific parameter value of the indication information.

[0074] In a specific example, for example, if the indication information is the first indication information, such as 0xe1, it indicates that according to the injection error behavior identifier, the error execution instruction corresponding to the injection error behavior identifier is matched from the pre-built resource pool, and the injection error operation is completed. If the indication information is the second indication information, such as 0xe0, it indicates that the error execution instruction in the resource pool managed by the NVMe SSD device is adjusted. If the indication information is not an instruction starting with 0xe, it means that no processing is performed.

[0075] Therefore, when the instruction information is the first instruction information instructing to execute the error injection operation, the error execution instruction corresponding to the error injection behavior identifier is matched from the pre-built resource pool according to the error injection behavior identifier.

[0076] Step S104, performing an error injection operation according to the error execution instruction, and obtaining error indication information and first status information corresponding to the solid state hard disk device.

[0077] Step S105: store the error indication information and the first state information.

[0078] Specifically, an error annotation operation is performed according to the error execution instruction, that is, customized error annotation processing is performed according to the error execution command, thereby generating a specified error. For example, restrictive conditions such as delay and randomness are added to a specific command, and a specified error is returned when the conditions are met. Then, the error indication information and the first state information are stored.

[0079] The error injection test method provided in this embodiment obtains a preconfigured error injection rule, wherein the error injection rule includes an error injection behavior identifier and indication information corresponding to the error injection behavior. When the indication information indicates the execution of the error injection behavior, the error execution instruction corresponding to the error injection behavior identifier is obtained from the pre-purchased resource pool according to the registered behavior identifier, and the error execution instruction is applied to the solid-state hard disk device to generate error indication information and the first state information corresponding to the solid-state hard disk device. Then the error indication information and the first state information are stored. In this method, by directly performing the error injection test at the hardware level, hardware failures and extreme situations can be simulated more realistically, thereby more accurately evaluating the fault tolerance of the SSD device. The automated error injection test process can reduce manual intervention and improve test efficiency and accuracy. Storing error indication information and state information is helpful for subsequent rapid diagnosis and problem solving, and improves the maintainability of the system. Moreover, by capturing and storing errors in the above manner, higher test accuracy can be achieved. By simulating and capturing various complex errors, the fault tolerance and recovery capability of the test equipment system in actual operation are evaluated to ensure that the system can be restored in time and maintain stable operation when an error occurs.

[0080] In this embodiment, a method for testing injection errors is provided, which can be used in the above-mentioned mobile terminals, such as mobile phones, tablet computers, etc. Figure 3 is a flow chart of another injection error testing method provided by an embodiment of the present invention, such as Figure 3 As shown, based on the above method steps, the method also includes the following method steps:

[0081] Step S301, when the indication information is the second indication information for indicating to adjust the erroneous execution instruction in the resource pool, the error annotation rule is parsed, and the adjustment rule corresponding to the erroneous execution instruction in the resource pool is obtained.

[0082] Specifically, as described above, if the indication information is the second indication information, such as 0xe0, it indicates to adjust the erroneous execution instruction in the resource pool managed by the NVMe SSD device.

[0083] Therefore, the error-injection rules will also include adjustment rules.

[0084] Step S302: According to the adjustment rule, an adjustment operation is performed on the erroneous execution instruction in the resource pool.

[0085] Specifically, the error execution instructions in the resource pool belong to different error types, and different error execution instructions correspond to different impact levels;

[0086] The specific adjustment operation includes the following steps:

[0087] Step a1: Acquire the error type corresponding to the erroneous execution instruction and the impact level corresponding to the erroneous execution instruction from the resource pool.

[0088] Error execution instructions can belong to different error types and correspond to different impact levels. Therefore, after parsing the behavior identifier in the error annotation rule, not only can the error execution instruction corresponding to the error annotation behavior identifier be matched in the pre-built resource pool, but the error type and impact level corresponding to the error execution instruction can also be identified.

[0089] Step a2: Determine the type of adjustment operation according to the adjustment rule.

[0090] The adjustment operation type includes one or more of adding an erroneous execution instruction, deleting an erroneous execution instruction, or changing an erroneous execution instruction.

[0091] Step a3: performing an adjustment operation on the erroneous execution instruction in the resource pool according to the type of adjustment operation, the error type corresponding to the erroneous execution instruction, and / or the impact level corresponding to the erroneous execution instruction.

[0092] Specifically, when there is only one erroneous execution instruction that needs to be adjusted, there is no priority relationship, and the erroneous execution instruction can be adjusted directly according to the adjustment rules. However, in many cases, there may be multiple erroneous execution instructions that need to be adjusted. At this time, it is necessary to classify the multiple erroneous execution instructions into "primary and secondary". That is, according to the error severity and / or the error impact level, determine the priority of the multiple erroneous execution instructions to be adjusted, that is, the adjustment order. Then make adjustments based on the final adjustment order. Of course, the adjustments can be made sequentially by a single thread, or they can be made in parallel by multiple threads.

[0093] An error injection test method provided by an embodiment of the present invention can flexibly adjust the error execution instructions in the resource pool according to specific needs by using adjustment rules to adapt to different test scenarios and requirements. It can also be adjusted for specific error types and impact levels, thereby improving the pertinence and effectiveness of the test. By adding, deleting or changing the error execution instructions, the test cases can be optimized to better evaluate the fault tolerance of the SSD device. It is also possible to adjust the error execution instructions in a timely manner according to the emergence of new technologies or new situations to ensure the comprehensiveness and accuracy of the test. In the above method, because the error execution instructions are adjusted directly in the resource pool, the work of repeatedly writing or modifying the error execution instructions can be avoided, thereby improving the test efficiency. This method can also help to conduct more refined tests and discover potential problems and weak links. By reasonably adjusting the error execution instructions, the reliability of the SSD device is further enhanced. Better management of the error execution instructions in the resource pool improves the utilization efficiency of resources.

[0094] Further optionally, before performing the adjustment operation, necessary verification and confirmation steps may be performed to ensure the correctness and safety of the adjustment. Specific verification may include checking the validity of the adjustment rules, testing or simulating the adjusted instructions, and other operations. When adjusting the erroneously executed instructions, corresponding notifications and reports may also be generated so that relevant personnel can understand the adjustment. The notification may include information such as the content, cause, and impact of the adjustment.

[0095] Furthermore, based on the above method, a rollback mechanism can also be established to restore to the previous state when the adjustment operation goes wrong or has adverse effects. The rollback mechanism can ensure the stability and reliability of the system. In addition, the adjustment of erroneous execution instructions can be integrated with other system components, such as monitoring systems, log systems, or automation tools. This allows for more comprehensive error management and automated processing.

[0096] In an optional example, storing the error indication information and the first state information specifically includes:

[0097] The error indication information and the first state information are stored in the persistent memory area.

[0098] Specifically, when powered on, the server will initialize the PMR space through the controller and allocate a memory area specifically for storing error data. When powered off, the NVMe SSD will store data in the PMR space persistently.

[0099] PMR is usually non-volatile, and the data stored in it will not be lost even if the system is powered off or restarted. Storing error indication information and status information here ensures the persistence of error indication information and status information, which is convenient for subsequent fault diagnosis and analysis. Reduce the risk of data loss or damage. Furthermore, the access speed of persistent memory is usually faster than that of traditional storage media (such as hard disks). Storing information in PMR space can increase the speed of data reading and writing, which helps to quickly obtain and process error-related data. Furthermore, PMR space can also be used to store historical records of error information, which is convenient for tracing and analyzing the status and problems of the system at different time points. This is very helpful for long-term system maintenance and optimization. After the system is powered on again, the controller of the test equipment can read the complete error code and status information from the PMR space to ensure that the test can be carried out continuously. Through the persistent memory area, the data integrity and system stability of the test equipment under long-term operation and frequent power on and off can be verified.

[0100] Further optionally, in order to more comprehensively simulate the error triggering situation, the embodiment of the present application can not only support conventional command error injection, but also support error injection processing in the case of abnormal power-off. Therefore, the method also includes the following embodiments.

[0101] In this embodiment, a method for testing injection errors is provided, which can be used in the above-mentioned mobile terminals, such as mobile phones, tablet computers, etc. Figure 4 is a flow chart of another injection error testing method provided by an embodiment of the present invention, such as Figure 4 As shown, the process includes the following steps:

[0102] Step S401: when a preset abnormal situation occurs, an erroneous execution instruction corresponding to the preset abnormal situation is matched from a resource pool.

[0103] In an optional example, the preset abnormal situation includes: abnormal power failure of the system, or abnormal power off of the system.

[0104] Specifically, the server is turned on and the device is running normally. Using any of the above-mentioned method embodiments, the erroneous execution instruction is injected into the SSD device.

[0105] The error-executed instruction may be a simulated hardware failure, a data transmission error, etc.

[0106] Step S402, executing an error injection operation according to an error execution instruction corresponding to a preset abnormal situation, and obtaining error indication information corresponding to the preset abnormal situation and second state information corresponding to the solid state hard disk device.

[0107] Step S403: store the error indication information corresponding to the preset abnormal situation and the second state information corresponding to the solid state disk device in the persistent memory area.

[0108] Specifically, for example, when an abnormal power outage occurs, an abnormal NVMe SSD condition in the abnormal power outage can be triggered, that is, an error injection operation corresponding to the erroneous execution instruction is executed. Then, error indication information corresponding to the preset abnormal condition and second status information corresponding to the solid-state hard disk device are obtained. At the same time, the relevant error information and status are written to the specified position of the PMR space.

[0109] Further optionally, when the preset abnormal situation is restored, the method further includes:

[0110] The data stored in the persistent memory area is recovered to generate recovered data, so that the independent disk redundant array can subsequently verify the error handling capability and data recovery capability of the independent disk redundant array in the event of abnormal power failure based on the data stored in the persistent memory area and the recovered data.

[0111] Specifically, after the next power-on, the NVMe SSD will restore the PMR data. The RAID card reads the data in the PMR space to capture the errors that occur in the SSD system during abnormal power-off, and verifies the reliability and error recovery capabilities of the RAID card in handling various error situations during abnormal power-off.

[0112] In addition to simulating the injection error behavior in the case of abnormal power-off, it can also simulate the injection error behavior in the case of abnormal power-on.

[0113] Specifically, by injecting errors into the power-on situation, after the error injection is successful, the power is normally turned off. After the power is turned off successfully, the power-on operation is performed again. At this time, the power-on abnormality in the resource pool will be triggered, and the error information and status will be saved in the PMR space.

[0114] Then, the NVMe SSD will recover the data in the PMR, and the RAID card can obtain data by reading the data in the PMR space, thereby verifying the reliability and error recovery capability of the RAID card in handling various errors caused by abnormal power-on.

[0115] Moreover, the above operations can be performed through automated testing tools to perform large-scale power-on and power-off tests, thereby more fully verifying the error handling process.

[0116] In this method, when a preset abnormal situation occurs, the corresponding error execution instruction can be quickly matched from the resource pool, and the error injection operation can be performed in time to reduce the impact time of the system failure. By matching the corresponding error execution instruction according to the preset abnormal situation, more targeted processing can be carried out to improve the efficiency of problem solving. The error indication information and server status information corresponding to the preset abnormal situation are stored in the persistent memory area to ensure the persistence and traceability of the data, which is convenient for subsequent fault analysis and diagnosis. By processing and storing information of preset abnormal situations, the system can be continuously optimized to improve the stability and reliability of the system. Analyzing the stored error indication information and status information can help predict possible failures and take preventive measures in advance. For example, if an abnormal situation occurs in the server in the future, relevant information can also be quickly obtained, which helps to quickly restore the system and reduce the time of business interruption.

[0117] By simulating and capturing various complex errors, the fault tolerance and recovery capability of the test equipment system in actual operation are evaluated to ensure that the system can recover in time and maintain stable operation when an error occurs. Through power-on and power-off tests, the recovery capability of the test equipment system in the event of unexpected power outages and power fluctuations is verified to ensure the stability and reliability of the system in harsh environments.

[0118] Figure 5The overall process structure diagram of error injection and feedback is shown in FIG. Specifically, it includes:

[0119] The host computer (RAID card mounted on the server) sends instructions to the NVMe SSD device, and the Cmdfetch (command acquisition) module in the NVMe SSD device obtains the command issued by the RAID. Then, after the cmd fetch module obtains the command, it must first be handed over to the command error annotation module for processing. The command error annotation module will make a preliminary judgment on the command. If this command needs to be annotated, the error annotation processing flow will be carried out. If the command does not need to be annotated, the command error annotation module will not do any processing and directly transmit the command to the subsequent module for processing. Among them, the processing flow of the command error annotation module refers to the method steps introduced in the various error annotation test method embodiments above. Moreover, the command error annotation module will store the error indication information and the status information corresponding to the solid-state hard disk device in the Pmr space. For instructions that do not need to be processed by the command error annotation module, they will be processed by the subsequent command processing module, and the command completion structure will be uploaded to the host computer through the command completion upload module.

[0120] Should Figure 5 The processes that need to be emphasized in this application document have been described in detail in the previous text, so they will not be repeated here. The other contents are not the key contents of the embodiments of this application, so they will not be introduced here.

[0121] In this embodiment, an injection error testing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0122] This embodiment provides a mis-injection testing device, such as Figure 6 As shown, it includes: an acquisition module 601, a parsing module 602, a matching module 603, and a processing module 604.

[0123] An acquisition module 601 is used to acquire a preconfigured error annotation rule;

[0124] Parsing module 602, used to parse the wrong annotation rule to obtain the wrong annotation behavior identifier and indication information corresponding to the wrong annotation behavior;

[0125] A matching module 603 is used to match an error execution instruction corresponding to the error injection behavior identifier from a pre-built resource pool according to the error injection behavior identifier when the indication information is the first indication information indicating the execution of the error injection operation;

[0126] The processing module 604 is used to perform an error injection operation according to the error execution instruction, and obtain error indication information and first state information corresponding to the solid state hard disk device;

[0127] The error indication information and the first state information are stored.

[0128] In an optional example, the parsing module 602 is further configured to parse the error injection rule when the indication information is second indication information for indicating that the error execution instruction in the resource pool is to be adjusted, and further includes obtaining an adjustment rule corresponding to the error execution instruction in the resource pool;

[0129] The processing module 604 is further used to adjust the erroneous execution instructions in the resource pool according to the adjustment rules;

[0130] The error execution instructions in the resource pool belong to different error types, and different error execution instructions correspond to different impact levels.

[0131] Adjustment operations include:

[0132] Obtaining from the resource pool an error type corresponding to the erroneous execution instruction and an impact level corresponding to the erroneous execution instruction;

[0133] Determine the type of adjustment operation according to the adjustment rule, wherein the adjustment operation type includes one or more of adding an erroneous execution instruction, deleting an erroneous execution instruction, or modifying an erroneous execution instruction;

[0134] An adjustment operation is performed on the erroneous execution instruction in the resource pool according to the type of the adjustment operation, the error type corresponding to the erroneous execution instruction, and / or the impact level corresponding to the erroneous execution instruction.

[0135] In an optional example, the processing module 604 is specifically configured to store the error indication information and the first state information in a persistent memory area.

[0136] In an optional example, the first indication information is preset indication information other than 0xe0, and the second indication information is 0xe0.

[0137] In an optional example, the matching module 603 is further configured to match an erroneous execution instruction corresponding to the preset abnormal situation from a resource pool when a preset abnormal situation occurs;

[0138] The processing module 604 is further used to execute an error injection operation according to the error execution instruction corresponding to the preset abnormal situation, obtain error indication information corresponding to the preset abnormal situation, and second state information corresponding to the solid state hard disk device;

[0139] The error indication information corresponding to the preset abnormal situation and the second state information corresponding to the solid state disk device are stored in the persistent memory area.

[0140] In an optional example, the preset abnormal situation includes: abnormal power failure of the system, or abnormal power off of the system.

[0141] In an optional example, the device further includes: a data recovery module 605;

[0142] The data recovery module 605 is used to recover the data stored in the persistent memory area after the preset abnormal situation is recovered, and generate recovered data so that the independent disk redundant array can subsequently verify the error handling capability and data recovery capability of the independent disk redundant array in the abnormal power-off situation based on the data stored in the persistent memory area and the recovered data.

[0143] The injection error testing device in this embodiment is presented in the form of a functional module, where the module refers to an application specific integrated circuit (ASIC), a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0144] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0145] An error injection test device provided by an embodiment of the present invention obtains a preconfigured error injection rule, wherein the error injection rule includes an error injection behavior identifier and indication information corresponding to the error injection behavior. When the indication information indicates to execute the error injection behavior, the error execution instruction corresponding to the error injection behavior identifier is obtained from the pre-purchased resource pool according to the registered behavior identifier, and the error execution instruction is applied to the solid-state hard disk device to generate error indication information and first state information corresponding to the solid-state hard disk device. Then the error indication information and the first state information are stored. In this method, by directly performing the error injection test at the hardware level, hardware failures and extreme situations can be simulated more realistically, thereby more accurately evaluating the fault tolerance of the SSD device. The automated error injection test process can reduce manual intervention and improve test efficiency and accuracy. Storing error indication information and state information is helpful for subsequent rapid diagnosis and problem solving, and improves the maintainability of the system. Moreover, by capturing and storing errors in the above manner, higher test accuracy can be achieved. By simulating and capturing various complex errors, the fault tolerance and recovery capability of the test device system in actual operation are evaluated to ensure that the system can be restored in time and maintain stable operation when an error occurs.

[0146] The embodiment of the present invention also provides a computer device having the above Figure 6 The mis-injection test setup shown.

[0147] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0148] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit. The integrated circuit may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0149] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0150] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0151] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0152] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0153] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0154] The embodiment of the present invention also provides a computer-readable storage medium. The method provided in the above embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or is implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium and downloaded through a network, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0155] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0156] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for testing injection errors, characterized in that: The method is performed by a solid state hard disk device, and the method includes: Get preconfigured error injection rules; Parsing the error injection rule to obtain an error injection behavior identifier and indication information corresponding to the error injection behavior; When the indication information is the first indication information indicating the execution of the wrong injection operation, according to the wrong injection behavior identifier, matching the wrong execution instruction corresponding to the wrong injection behavior identifier from the pre-built resource pool; Execute the error injection operation according to the error execution instruction to obtain error indication information and first status information corresponding to the solid state hard disk device; The error indication information and the first status information are stored.

2. The method according to claim 1, characterized in that The method further comprises: When the indication information is second indication information for indicating adjustment of the erroneous execution instruction in the resource pool, the parsing of the error injection rule further includes acquiring an adjustment rule corresponding to the erroneous execution instruction in the resource pool; According to the adjustment rule, an adjustment operation is performed on the erroneous execution instruction in the resource pool; The error execution instructions in the resource pool belong to different error types, and different error execution instructions correspond to different impact levels. The adjustment operation includes: Acquire, from the resource pool, an error type corresponding to the erroneous execution instruction and an impact level corresponding to the erroneous execution instruction; Determine the type of adjustment operation according to the adjustment rule, wherein the type of adjustment operation includes one or more of adding an erroneous execution instruction, deleting an erroneous execution instruction, or modifying an erroneous execution instruction; An adjustment operation is performed on the erroneous execution instruction in the resource pool according to the type of the adjustment operation, the error type corresponding to the erroneous execution instruction, and / or the impact level corresponding to the erroneous execution instruction.

3. The method according to claim 1, characterized in that: Storing the error indication information and the first state information specifically includes: The error indication information and the first state information are stored in a persistent memory area.

4. The method according to claim 2, characterized in that: The first indication information is preset indication information other than 0xe0, and the second indication information is 0xe0.

5. The method according to claim 3, characterized in that: The method further comprises: When a preset abnormal situation occurs, matching an erroneous execution instruction corresponding to the preset abnormal situation from the resource pool; Execute the error injection operation according to the error execution instruction corresponding to the preset abnormal situation, and obtain error indication information corresponding to the preset abnormal situation and second state information corresponding to the solid state hard disk device; The error indication information corresponding to the preset abnormal situation and the second state information corresponding to the solid state disk device are stored in the persistent memory area.

6. The method according to claim 5, characterized in that The preset abnormal situation includes: abnormal power failure of the system, or abnormal power failure of the system.

7. The method according to claim 6, characterized in that When the preset abnormal situation is restored, the method further includes: The data stored in the persistent memory area is recovered to generate recovered data, so that the independent disk redundant array can subsequently verify the error handling capability and data recovery capability of the independent disk redundant array in the event of abnormal power failure based on the data stored in the persistent memory area and the recovered data.

8. A mis-injection testing device, characterized in that: The device corresponds to a solid state hard disk device, and the device includes: An acquisition module is used to obtain pre-configured error annotation rules; A parsing module, used to parse the error-annotation rule to obtain an error-annotation behavior identifier and indication information corresponding to the error-annotation behavior; A matching module, configured to match an error execution instruction corresponding to the error injection behavior identifier from a pre-built resource pool according to the error injection behavior identifier when the indication information is the first indication information indicating the execution of the error injection operation; A processing module, configured to execute the error injection operation according to the error execution instruction, and obtain error indication information and first status information corresponding to the solid state hard disk device; The error indication information and the first status information are stored.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the injection error testing method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the injection error testing method according to any one of claims 1 to 7.

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