Communication method, device, system and processor
By using registers to store access status information in a general input and output module to control access to multiprocessor cores, the problem of multiprocessor core access competition is solved and the stability and performance of the system is improved.
Patent Information
- Application Number
- CN202411111701.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-13
- Publication Date
- 2024-12-10
AI Technical Summary
In the processor of multiprocessor core, access competition is prone to occur when the multiprocessor core accesses the same general input and output pin group at the same time, resulting in performance degradation and stability problems. The existing technology solves the problem through shared memory and semaphores, but it is costly. And poor stability.
By introducing multiple registers in the general input and output module, the access status information of the processor core to the general input and output pin group is stored separately, and access control is performed based on this information, ensuring that only unreached cores can access the pin group, avoiding compete.
Without increasing too much cost, access competition is effectively avoided when multi-processor cores access the same general input and output pin group at the same time, improving system stability.
Smart Images
Figure CN119105982A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communications, and in particular to a communication method, device, system and processor. Background Art
[0002] At present, in a processor with multiple processor cores, such as a central processing unit (CPU), access contention is very likely to occur when multiple processor cores access the same general purpose I / O ports (GPIO) pin group at the same time. The access contention between processor cores will not only cause the processor core to fail to access the general purpose I / O pin group, but also cause the processor core to read or write incorrect data, and even cause the performance and stability of the processor to deteriorate.
[0003] In order to avoid access contention when multiple processor cores of a processor access the same general purpose input / output pin group at the same time, the prior art usually introduces a shared memory accessible to the multiple processor cores, and distributes semaphores to the multiple processor cores through the shared memory, so that only the processor core with the semaphore can access the general purpose input / output pin group within a period of time. However, the shared memory accessible to the multiple processor cores requires developers to design a matching read / write mechanism for it, which is costly. At the same time, since it needs to rely on programs to run, the stability of the shared memory itself is also poor, and it is easy to crash, resulting in the inability of each processor core to access the general purpose input / output pin group normally within a period of time. Summary of the invention
[0004] In view of this, embodiments of the present invention provide a communication method, device, system and processor to avoid access contention when multiple processor cores of a processor access the same general purpose input and output pin group at the same time without increasing costs too much.
[0005] At least two processor cores;
[0006] A general purpose input-output module, comprising at least one general purpose input-output pin group, wherein the general purpose input-output pin group is shared by a plurality of processor cores corresponding to the general purpose input-output pin group, and the general purpose input-output pin group comprises at least one general purpose input-output pin;
[0007] A plurality of registers, each of the registers being used to store access status information of a corresponding processor core to a corresponding general purpose input and output pin group;
[0008] Wherein, each of the processor cores is configured as:
[0009] Obtain access status information stored in each target register;
[0010] In response to the access status information indicating that each target processor core has not accessed the target general purpose input-output pin group, an access operation to the target general purpose input-output pin group is performed.
[0011] Furthermore, each of the processor cores is also configured as:
[0012] Before executing the access operation to the target general purpose input / output pin group, the access status information stored in the corresponding target register is updated to being accessed.
[0013] Furthermore, each of the processor cores is also configured as:
[0014] After updating the access status information stored in the corresponding target register to being accessed, before performing the access operation on the target general purpose input and output pin group, obtaining the access status information stored in each target register;
[0015] In response to the access status information indicating that the remaining target processor cores except the current processor core have not accessed the target general purpose input-output pin group, an access operation to the target general purpose input-output pin group is performed.
[0016] Furthermore, each of the processor cores is also configured as:
[0017] In response to the access status information indicating that any target processor core other than the current processor core is accessing the target general purpose input / output pin group, the access status information stored in the corresponding target register is updated to not accessed, and after a preset time period, the step of first acquiring the access status information stored in each of the target registers is returned.
[0018] Furthermore, each of the processor cores is also configured as:
[0019] After executing the access operation to the target general purpose input / output pin group, the access status information stored in the corresponding target register is updated to not accessed.
[0020] Furthermore, each of the processor cores is also configured as:
[0021] In response to the access status information indicating that any target processor core is accessing the target general purpose input / output pin group, the step of returning to the step of obtaining the access status information stored in each of the target registers after a preset time period.
[0022] Furthermore, the plurality of registers are registers in the general input and output module.
[0023] In a second aspect, an embodiment of the present invention provides a communication method, the method comprising:
[0024] Obtain access status information stored in each target register;
[0025] In response to the access status information indicating that each target processor core has not accessed a target general purpose input output pin group, an access operation to the target general purpose input output pin group is performed, wherein the target general purpose input output pin group is shared by each target processor core.
[0026] In a third aspect, an embodiment of the present invention provides a communication device, the device comprising:
[0027] An acquisition unit, used for acquiring access status information stored in each target register;
[0028] The execution unit is used for executing an access operation to the target general purpose input-output pin group in response to the access status information indicating that each target processor core has not accessed the target general purpose input-output pin group, wherein the target general purpose input-output pin group is shared by each target processor core.
[0029] In a fourth aspect, an embodiment of the present invention provides a processor, comprising at least two processor cores, each of the processor cores being configured to execute the method described in the second aspect.
[0030] The embodiment of the present invention stores the access status information of the corresponding processor core to the corresponding general input-output pin group in multiple registers respectively, and each processor core first obtains the access status information stored in each target register when accessing the target general input-output pin group, and then performs the access operation to the target general input-output pin group when the access status information indicates that each target processor core has not accessed the target general input-output pin group. Therefore, by introducing registers to store the access status information of the processor core to the general input-output pin group and the processor core accesses the general input-output pin group based on the stored access status information, the embodiment of the present invention can avoid access competition when multiple processor cores of the processor access the same general input-output pin group at the same time without increasing the cost too much and ensuring stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0032] Figure 1 is a schematic diagram of a communication system according to an embodiment of the present invention;
[0033] Figure 2is a flow chart of a communication method according to an embodiment of the present invention;
[0034] Figure 3 is another flow chart of the communication method according to an embodiment of the present invention;
[0035] Figure 4 FIG. 4 is a schematic diagram of a communication device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.
[0037] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0038] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".
[0039] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.
[0040] Figure 1 FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present invention. Figure 1 As shown, the communication system includes at least two processor cores 11, a general input and output module 12 and a plurality of registers. Figure 1 Shown in.
[0041] The processor cores 11 are multiple processor cores owned by a processor (e.g., a central processing unit). Each processor core 11 can be regarded as a complete processing unit. They have their own arithmetic logic unit (ALU), cache, and control logic, and can independently execute instructions, manage data, and process computing tasks. Through mutual cooperation, each processor core can realize the data processing function provided by the processor to the outside.
[0042] The general input and output module 12 is a functional module for managing the general input and output pins of the processor. Optionally, the general input and output module 12 can be integrated on the processor or externally mounted on other chips, which is not limited in the present application. The general input and output module 12 can include at least one general input and output pin group. Each general input and output pin group can have corresponding multiple processor cores 11, and the same general input and output pin group can be shared by multiple processor cores 11 corresponding thereto. Optionally, the processor cores 11 corresponding to different general input and output pin groups can be the same or different, which is not limited in the present application. Further, each general input and output pin group can include at least one (for example, 1, 4, 8, 16, 32 or more) general input and output pin. The general input and output pin is used to connect the processor with an external device. Each general input and output pin can be configured to include an input mode or an output mode. In the input mode, the general input and output pin can receive a digital signal (i.e., a high or low level signal) from an external device. In the output mode, the general input and output pin can send a digital signal to a corresponding circuit to drive an external device. By accessing the GPIO pins in the corresponding GPIO pin group, each processor core 11 of the processor can transmit data or instructions to an external device, or receive data or instructions from an external device.
[0043] Each register is used to store the access status information of the corresponding processor core 11 to the corresponding general purpose input and output pin group. Optionally, each register can be an unused idle register in the general purpose input and output module 12, or an unused idle register in other external devices, and the present application does not limit this. It should be understood that for some registers (such as registers that do not support bitwise operations), if a certain bit of data stored in the register is to be modified, it is usually necessary to first read out all the data stored in the register and then modify it, and then store the modified data back to the register. In this embodiment, in order to avoid the problem of data error overwriting when different processor cores 11 simultaneously update the storage status information in this part of the register, each register can only store the access status information of one processor core 11 to a corresponding general purpose input and output pin group. It should be understood that in some embodiments, under the premise of hardware permission, the access status information of each processor core 11 to the corresponding general purpose input and output pin group can also be stored in a corresponding manner according to actual needs. For example, the access status information of multiple processor cores 11 to the same general purpose input-output pin group can also be stored in the same register. For another example, the access status information of the same processor core 11 to multiple general purpose input-output pin groups can also be stored in the same register. For another example, the access status information of each processor core 11 to each general purpose input-output pin group can also be stored in the same register. No more examples are given here.
[0044] Specifically, in this embodiment, for any processor core 11, when the processor core 11 accesses the corresponding target general purpose input and output pin group, it can first obtain the access status information stored in each target register, and then perform the access operation on the target general purpose input and output pin group when the access status information indicates that each target processor core has not accessed the target general purpose input and output pin group. Among them, the target register is a register storing the access status information of each target processor core to the target general purpose input and output pin group, and each target processor core is a processor core corresponding to the target general purpose input and output pin group (that is, sharing the target general purpose input and output pin group).
[0045] Therefore, by introducing a register to store the access status information of the processor core to the general input and output pin group and the processor core accesses the general input and output pin group based on the stored access status information, the embodiment of the present invention can avoid access contention when multiple processor cores of the processor access the same general input and output pin group at the same time without increasing the cost too much and ensuring stability.
[0046] Further, in order to enable each processor core 11 to communicate with the universal input and output module 12, a bus 13 may also be included in the communication system. The bus 13 may be used to connect each processor core 11 with the universal input and output module 12. Optionally, the bus 13 may adopt an advanced eXtensible interface (AXI) and / or an advanced peripheral bus (APB). Among them, the advanced eXtensible interface is a high-speed, full-duplex, scalable bus that can support burst transmission and multi-channel operation. The advanced peripheral bus is a low-speed and low-power bus with low complexity and cost. At the same time, due to its low data transmission rate, it can run at a lower voltage, which helps to reduce power consumption. It should be understood that in actual application, the bus 13 may also adopt other types of buses, such as an advanced high-performance bus (AHB), and this application does not limit this.
[0047] I hope to explain that for ease of understanding, Figure 1 The communication system shown is a simplified communication system. In actual application, in order to meet the working requirements of the processor, the composition of the communication system is not limited to Figure 1 For example, in actual application, the communication system may also include a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), a watchdog timer (WDT), a universal asynchronous receiver / transmitter (UART) and / or a direct memory access (DMA) controller, etc.
[0048] Figure 2 FIG. 1 is a flow chart of a communication method according to an embodiment of the present invention. Figure 2 As shown, the communication method may specifically include the following steps:
[0049] It should be understood that Figure 2 The execution subject of the communication method shown may be any processor core in the above embodiments.
[0050] Step S100: Acquire access status information stored in each target register.
[0051] Specifically, when it is necessary to access the target general purpose input and output pin group, the processor core may first obtain the access status information stored in each target register. Among them, each target register may be a register storing the access status information of each target processor core to the target general purpose input and output pin group, and each target processor core is a processor core corresponding to the target general purpose input and output pin group (i.e., sharing the target general purpose input and output pin group). It should be understood that when only the access status information of one processor core to one general purpose input and output pin group is stored in one register, the number of target registers should be equal to the number of target processor cores.
[0052] Optionally, in this embodiment, the access status information obtained by the processor core in each target register may be a binary character, wherein a binary character of "1" may be used to indicate that the corresponding target processor core is currently accessing the target general purpose input and output pin group, and a binary character of "0" may be used to indicate that the corresponding target processor core is not currently accessing the target general purpose input and output pin group.
[0053] Step S200: determining whether the access status information indicates that each target processor core has not accessed the target general purpose input / output pin group.
[0054] Specifically, after obtaining the access status information stored in each target register, the processor core can determine whether the access status information indicates that each target processor core has not accessed the target GPIO pin group. If so, the processor core can continue to execute step S300, if not, the processor core can return to step S100.
[0055] Step S300: Execute an access operation to the target general purpose input / output pin group.
[0056] Specifically, when it is determined that the access status information indicates that each target processor core has not accessed the target general purpose input and output pin group, the processor core may perform an access operation to the target general purpose input and output pin group. The processor core performing an access operation to the target general purpose input and output pin group may specifically refer to the processor core reading a digital signal from a corresponding general purpose input and output pin in the target general purpose input and output pin group, or the processor core controlling a corresponding general purpose input and output pin in the target general purpose input and output pin group to output a digital signal.
[0057] Further, when it is determined that the access status information indicates that any target processor core is accessing the target general input / output pin group, the processor core may return to the step of obtaining the access status information stored in each target register (i.e., returning to step S100) after a preset time period (e.g., one clock cycle).
[0058] Optionally, in order to ensure the accuracy of the access status information stored in the register, the processor core needs to update the access status information stored in the corresponding register in real time according to its own access status to the corresponding general input and output pin groups. Specifically, taking the corresponding target register (that is, the register storing the access status information of the current processor core to the target general input and output pin group) as an example, after each power-on, the processor core can initialize all the access status information stored in the corresponding target register to not accessed. Before performing the access operation to the target general input and output pin group, the processor core can update the access status information stored in the corresponding target register from not accessed to being accessed. And, after performing the access operation to the target general input and output pin group, the processor core can re-update the access status information stored in the corresponding target register from being accessed to not accessed.
[0059] Optionally, in actual application, the communication system may have multiple processor cores that need to access the target general input and output pin group at the same time, and the multiple processor cores obtain the access status information stored in each target register at the same time. In this embodiment, in order to prevent access competition between multiple processor cores in this case, after updating the access status information stored in the corresponding target register to accessing, and before executing the access operation to the target general input and output pin group, the processor core can also obtain the access status information stored in each target register again (it should be understood that in order to prevent multiple processor cores from falling into an infinite loop, each processor core can be set to obtain the access status information stored in each target register again at different times after updating the access status information stored in the corresponding target register to accessing). At this time, if the access status information indicates that the remaining target processor cores except the current processor core have not accessed the target general input and output pin group, the processor core can perform the access operation to the target general input and output pin group. If the access status information indicates that any target processor core other than the current processor core is accessing the target general purpose input / output pin group, the processor core may update the access status information stored in the corresponding target register from being accessed to not being accessed, and after a preset time period (e.g., one clock cycle), return to the step of first acquiring the access status information stored in each target register (i.e., returning to step S100).
[0060] Figure 3 FIG. 4 is another flow chart of the communication method according to an embodiment of the present invention. Figure 3 As shown, the communication method may specifically include the following steps:
[0061] It should be understood that Figure 3 The execution subject of the communication method shown may also be the processor core in the above embodiment.
[0062] Step S100': obtaining access status information stored in each target register.
[0063] Specifically, when the processor core needs to access the target GPIO pin group, the access status information stored in each target register can be obtained first. Each target register can be a register storing the access status information of each target processor core sharing the target GPIO pin group to the target GPIO pin group.
[0064] Step S200': determine whether each target processor core has not accessed the target GPIO pin group.
[0065] Specifically, after acquiring the access status information stored in each target register, the processor core may determine whether each target processor core has not accessed the target general purpose input and output pin group according to the acquired access status information.
[0066] Step S300': update the access status information stored in the corresponding target register to "accessing".
[0067] Specifically, when it is determined that each target processor core has not accessed the target general purpose input and output pin group, the processor core may update the access status information stored in the corresponding target register to accessing.
[0068] It should be understood that when it is determined that any target processor core is accessing the target GPIO pin group, the processor core may return and execute step S100 ′ after a preset time period.
[0069] Step S400': obtaining access status information stored in each target register.
[0070] Specifically, after updating the access status information stored in the corresponding target register to being accessed, the processor core may obtain the access status information stored in each target register again.
[0071] Step S500': determine whether the remaining target processor cores have not accessed the target GPIO pin group.
[0072] Specifically, after acquiring the access status information stored in each target register for the second time, the processor core may determine whether the remaining target processor cores except the current processor core have not accessed the target general purpose input and output pin group according to the access status information.
[0073] Step S600': Execute an access operation to the target GPIO pin group.
[0074] Specifically, when it is determined that the target processor cores other than the current processor core have not accessed the target general purpose input-output pin group, the processor core may perform an access operation on the target general purpose input-output pin group.
[0075] Step S700': update the access status information stored in the corresponding target register to not accessed.
[0076] Specifically, when it is determined that any target processor core other than the current processor core is accessing the target GPIO pin group, the processor core may update the access status information stored in the corresponding target register to not accessed, and return to execute step S100' after a preset time period.
[0077] The embodiment of the present invention stores the access status information of the corresponding processor core to the corresponding general input-output pin group in multiple registers respectively, and each processor core first obtains the access status information stored in each target register when accessing the target general input-output pin group, and then performs the access operation to the target general input-output pin group when the access status information indicates that each target processor core has not accessed the target general input-output pin group. Therefore, by introducing registers to store the access status information of the processor core to the general input-output pin group and the processor core accesses the general input-output pin group based on the stored access status information, the embodiment of the present invention can avoid access competition when multiple processor cores of the processor access the same general input-output pin group at the same time without increasing the cost too much and ensuring stability.
[0078] Figure 4 FIG. 1 is a schematic diagram of a communication device according to an embodiment of the present invention. Figure 4 As shown, the communication device according to the embodiment of the present invention includes an acquisition unit 41 and an execution unit 42 .
[0079] Specifically, the acquisition unit 41 is used to acquire the access status information stored in each target register;
[0080] The execution unit 42 is used for executing an access operation on the target general purpose input output pin group in response to the access status information indicating that each target processor core has not accessed the target general purpose input output pin group, wherein the target general purpose input output pin group is shared by each target processor core.
[0081] The embodiment of the present invention stores the access status information of the corresponding processor core to the corresponding general input-output pin group in multiple registers respectively, and each processor core first obtains the access status information stored in each target register when accessing the target general input-output pin group, and then performs the access operation to the target general input-output pin group when the access status information indicates that each target processor core has not accessed the target general input-output pin group. Therefore, by introducing registers to store the access status information of the processor core to the general input-output pin group and the processor core accesses the general input-output pin group based on the stored access status information, the embodiment of the present invention can avoid access competition when multiple processor cores of the processor access the same general input-output pin group at the same time without increasing the cost too much and ensuring stability.
[0082] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A communication system, It is characterized in that The system comprises: At least two processor cores; A general purpose input-output module, comprising at least one general purpose input-output pin group, wherein the general purpose input-output pin group is shared by a plurality of processor cores corresponding to the general purpose input-output pin group, and the general purpose input-output pin group comprises at least one general purpose input-output pin; A plurality of registers, each of the registers being used to store access status information of a corresponding processor core to a corresponding general purpose input and output pin group; Wherein, each of the processor cores is configured as: Obtain access status information stored in each target register; In response to the access status information indicating that each target processor core has not accessed the target general purpose input-output pin group, an access operation to the target general purpose input-output pin group is performed.
2. The system according to claim 1, It is characterized in that Each of the processor cores is further configured to: Before executing the access operation to the target general purpose input / output pin group, the access status information stored in the corresponding target register is updated to being accessed.
3. The system according to claim 2, It is characterized in that Each of the processor cores is further configured to: After updating the access status information stored in the corresponding target register to being accessed, before performing the access operation on the target general input / output pin group, obtaining the access status information stored in each target register; In response to the access status information indicating that the remaining target processor cores except the current processor core have not accessed the target general purpose input-output pin group, an access operation to the target general purpose input-output pin group is performed.
4. The system according to claim 3, It is characterized in that Each of the processor cores is further configured to: In response to the access status information indicating that any target processor core other than the current processor core is accessing the target general purpose input / output pin group, the access status information stored in the corresponding target register is updated to not accessed, and after a preset time period, the step of first acquiring the access status information stored in each of the target registers is returned.
5. The system according to claim 2, It is characterized in that Each of the processor cores is further configured to: After executing the access operation to the target general purpose input / output pin group, the access status information stored in the corresponding target register is updated to not accessed.
6. The system according to claim 1, It is characterized in that Each of the processor cores is further configured to: In response to the access status information indicating that any target processor core is accessing the target general purpose input / output pin group, the step of returning to the step of obtaining the access status information stored in each of the target registers after a preset time period.
7. The system according to claim 1, It is characterized in that The plurality of registers are idle registers in the general purpose input and output module and / or the external device.
8. A communication method, It is characterized in that The method comprises: Obtain access status information stored in each target register; In response to the access status information indicating that each target processor core has not accessed a target general purpose input output pin group, an access operation to the target general purpose input output pin group is performed, wherein the target general purpose input output pin group is shared by each target processor core.
9. A communication device, It is characterized in that The device comprises: An acquisition unit, used for acquiring access status information stored in each target register; The execution unit is used for executing an access operation to the target general purpose input-output pin group in response to the access status information indicating that each target processor core has not accessed the target general purpose input-output pin group, wherein the target general purpose input-output pin group is shared by each target processor core.
10. A processor, It is characterized in that The processor comprises at least two processor cores, each of which is configured to execute the method according to claim 8 .