SOC-level memory access verification system and method and memory controller initialization method

Abstract

The invention provides an SOC-level memory access verification system and method and a memory controller initialization method. The system comprises a plurality of memory controllers and component-level verification environments corresponding to the memory controllers. Wherein each storage controller is connected with the component-level verification environment corresponding to the storage controller; the target storage controller is used for receiving a storage controller initialization sequence issued by the component-level verification environment for initialization; the target storage controller is any one storage controller in the plurality of storage controllers. According to the method and the device, the time of the initialization process of the whole SOC-level memory access verification can be shortened to be close to the time of component-level initialization of a single memory controller, and the verification efficiency of the SOC-level memory access verification is improved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a SOC-level memory access verification system and method, and a storage controller initialization method. Background Art

[0002] With the rapid development of integrated circuit technology, the scale of integrated circuits is getting larger and larger, and the cost is getting higher and higher. The cost of a single tape-out is very high. In order to fully verify the design within a limited time, simulation acceleration verification is becoming increasingly important.

[0003] In the design of processor chips, the memory storage controller is the most important module. All programs are run in the memory. Its function is to store the calculation data in the CPU and the data exchanged with external storage devices such as hard disks. Therefore, in order to ensure full verification, the CPU core memory access and peripheral memory access need to be fully verified. Verification includes component-level memory access verification and SOC (System-on-Chip) level memory access verification.

[0004] In the component-level memory access verification, including the storage controller and memory, the environment is mainly built with UVM methodology. The storage controller initialization sequence is sent through the register interface driver in the form of a transaction packet. The storage controller initialization sequence is entered on the component interface, which only takes a few minutes. After the initialization configuration is completed, the memory access program sequence is sent through the data interface driver in the form of a transaction packet. The verification program sequence is sent directly on the interface, and the verification speed is very fast.

[0005] In SOC-level memory access verification, the minimum environment also needs to integrate the processor core, storage controller, memory, and flash (flash memory). The stimulus is generally written in assembly or C language to write the storage controller initialization sequence, which is converted into a format and placed in the flash. The processor core obtains the storage controller initialization sequence from the flash and then sends it to each storage controller for storage controller initialization configuration. The SOC chip contains multiple storage controllers. For the system-level initialization configuration of multiple storage controllers, they are configured in a serial order. After the storage controller is initialized, the processor begins to access the normal memory data path. However, the methods and program implementations of SOC-level memory access verification are very different from those of component-level memory access verification, and the verification program needs to be redeveloped. The redevelopment of the verification program means that new program debugging risks may be introduced. When such risks occur, the verification speed will be slowed down.

[0006] In addition, as the scale of integrated circuits increases, the scale of SOC-level memory access verification also increases and becomes more complicated, which means that the initialization of the memory controller during verification takes several hours or even a day or several days. If the initialization time of the memory controller is too long, it will seriously affect the verification efficiency of the SOC. Summary of the invention

[0007] The purpose of the embodiments of the present application is to provide a SOC-level memory access verification system and method, and a storage controller initialization method, so as to improve the verification speed of the SOC-level memory access verification.

[0008] An embodiment of the present application provides a SOC-level memory access verification system, comprising: multiple storage controllers, and a component-level verification environment corresponding to each storage controller; wherein: each of the storage controllers is connected to the component-level verification environment corresponding to the storage controller; the target storage controller is used to: receive a storage controller initialization sequence sent by the component-level verification environment for initialization; the target storage controller is any storage controller among the multiple storage controllers.

[0009] In the above-mentioned SOC-level memory access verification system, since each of the storage controllers is connected to the component-level verification environment corresponding to the storage controller, based on the above-mentioned SOC-level memory access verification system, once SOC-level memory access verification is required, the component-level verification environment corresponding to each storage controller can be used to directly send the storage controller initialization sequence during the component-level memory access verification to each storage controller to realize the initialization of each storage controller. In this way, on the one hand, the storage controller initialization sequence used during the component-level memory access verification corresponding to each storage controller can be directly reused, without the need to redevelop the program of the storage controller initialization part, and no new program debugging risks will be introduced, thereby improving the verification efficiency; on the other hand, since the component-level verification environment corresponding to each storage controller can independently send the storage controller initialization sequence to each storage controller, it means that when performing SOC-level memory access verification, each storage controller can be initialized in parallel. In this way, the initialization time of the entire SOC-level memory access verification can be reduced to a level close to the component-level initialization time of a single storage controller, and the initialization time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of SOC-level memory access verification, improving the verification speed of SOC-level memory access verification, and improving the verification efficiency of SOC-level memory access verification.

[0010] Furthermore, the SOC-level memory access verification system also includes: a verification instruction issuing module, an arbitration module and a memory; wherein: different storage controllers are respectively connected to different memories, and each storage controller is connected to the component-level verification environment corresponding to each storage controller through a different arbitration module; and the arbitration module is also connected to the verification instruction issuing module; the target storage controller is used to: during the initialization stage, receive the storage controller initialization sequence issued by the component-level verification environment through the connected arbitration module, and perform initialization; and, after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module through the connected arbitration module to perform memory access verification.

[0011] In the above implementation, when performing SOC-level memory access verification, the arbitration module enables the storage controller to receive the storage controller initialization sequence for initialization during the initialization phase, and after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module for memory access verification. In this way, the normal verification function can be completed while the storage controller initialization sequence in the component-level verification environment is initialized, thereby ensuring the normal progress of the verification.

[0012] Furthermore, the component-level verification environment includes: the storage controller initialization sequence, a register agent, and an end controller; the register agent is used to send the storage controller initialization sequence to the connected arbitration module; the end controller is configured not to end the simulation after the storage controller initialization sequence is sent.

[0013] It can be understood that a normal component-level verification environment will include a register agent. In the above implementation scheme, the storage controller initialization sequence is externalized by reusing the register agent, without the need for additional modules. At the same time, by setting an end controller and configuring the end controller not to end the simulation after the storage controller initialization sequence is sent, the component-level verification environment can be distinguished from the process when executing component-level memory access verification, so that after the storage controller initialization sequence of the reused component-level verification environment is initialized, the simulation can continue, thereby completing the SOC-level memory access verification and improving the reliability of the scheme.

[0014] Furthermore, the end controller is implemented in the form of a class and has a judgment function; the judgment function is used to: after determining that a preset enable signal is received, call the target function; the target function is a function that can prevent the simulation from ending.

[0015] Through the above implementation, the function of not ending the simulation after the storage controller initialization sequence is sent can be easily realized, and the implementation is simple.

[0016] Furthermore, the component-level verification environment further includes: a data interface driver; the data interface driver is configured to be unused.

[0017] It can be understood that a normal component-level verification environment will include a data interface driver. In the above implementation scheme, by configuring the data interface driver to be unused, the component-level verification environment is prevented from generating erroneous data reception or transmission operations, thereby improving the reliability of the storage controller initialization sequence.

[0018] Furthermore, the verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core, the verification instruction storage module and each arbitration module are connected via the network module; the verification instruction storage module stores verification instructions; the processor core is used to obtain verification instructions from the verification instruction storage module and issue them to the arbitration module via the network module.

[0019] In the above implementation scheme, the processor core can implement memory access verification for each storage controller by fetching instructions (i.e., obtaining instructions) from the verification instruction storage module and issuing them through the network module, thereby ensuring the normal progress of verification and improving the reliability of the scheme. In addition, since the initialization of each storage controller is completed through the corresponding component-level verification environment of each storage controller, the storage controller initialization sequence does not need to be stored in the verification instruction storage module, thereby reducing the demand for the storage capacity of the verification instruction storage module and improving the feasibility of the system.

[0020] An embodiment of the present application also provides a storage controller initialization method during a SOC-level memory access verification process, which is applied to a target storage controller of a SOC-level memory access verification system; the SOC-level memory access verification system includes: multiple storage controllers and a component-level verification environment corresponding to each storage controller; wherein: each of the storage controllers is connected to the component-level verification environment corresponding to the storage controller; the target storage controller is any one of the multiple storage controllers; the method includes: receiving a storage controller initialization sequence issued by the connected component-level verification environment for initialization.

[0021] Based on the above implementation scheme, the storage controller initialization sequence during the component-level memory access verification is directly sent to each storage controller through the component-level verification environment corresponding to each storage controller, so as to realize the initialization of each storage controller. In this way, on the one hand, the storage controller initialization sequence used during the component-level memory access verification corresponding to each storage controller can be directly reused, without the need to redevelop the program of the storage controller initialization part, and no new program debugging risk will be introduced, thereby improving the verification efficiency; on the other hand, since the component-level verification environment corresponding to each storage controller can independently send the storage controller initialization sequence to each storage controller, it means that when performing SOC-level memory access verification, each storage controller can be initialized in parallel. In this way, the initialization process time of the entire SOC-level memory access verification can be reduced to a time close to the initialization time of a single storage controller, and the initialization process time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0022] An embodiment of the present application also provides a SOC-level memory access verification method, which is applied to a SOC-level memory access verification system; the SOC-level memory access verification system includes: a verification instruction issuing module, an arbitration module, a memory, multiple storage controllers, and a component-level verification environment corresponding to each storage controller; wherein: different storage controllers are respectively connected to different memories, and each storage controller is respectively connected to the component-level verification environment corresponding to each storage controller through a different arbitration module; and the arbitration module is also connected to the verification instruction issuing module; the method includes: the target storage controller receives the storage controller initialization sequence issued by the component-level verification environment through the connected arbitration module to perform initialization; after the initialization is completed, the target storage controller receives the verification instruction issued by the verification instruction issuing module through the connected arbitration module to perform memory access verification; the target storage controller is any storage controller among the multiple storage controllers.

[0023] Based on the above implementation, on the one hand, the storage controller initialization sequence used in the component-level memory access verification corresponding to each storage controller can be directly reused, without the need to redevelop the program of the storage controller initialization part, and no new program debugging risks will be introduced, thereby improving the verification efficiency; on the other hand, since the component-level verification environment corresponding to each storage controller can independently send the storage controller initialization sequence to each storage controller, it means that when performing SOC-level memory access verification, each storage controller can be initialized in parallel. In this way, the initialization process time of the entire SOC-level memory access verification can be reduced to a time close to the initialization time of a single storage controller, and the initialization process time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0024] Furthermore, the component-level verification environment includes: an end controller; before receiving the verification instruction issued by the verification instruction issuing module through the connected arbitration module, the method also includes: configuring the end controller not to end the simulation after the storage controller initialization sequence is sent.

[0025] Furthermore, the verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core, the verification instruction storage module and each arbitration module are connected through the network module; the verification instruction storage module stores verification instructions; wherein: the verification instruction received through the connected arbitration module is a verification instruction obtained by the processor core from the verification instruction storage module and issued through the network module. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A basic structural diagram of a SOC-level memory access verification system provided in an embodiment of the present application;

[0028] Figure 2 A structural diagram of a specific SOC-level memory access verification system provided in an embodiment of the present application;

[0029] Figure 3A more specific structural diagram of a SOC-level memory access verification system provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the structure of a component-level verification environment provided in an embodiment of the present application;

[0031] Figure 5 A flowchart of a storage controller initialization method in a SOC-level memory access verification process provided by an embodiment of the present application;

[0032] Figure 6 A flow chart of a SOC-level memory access verification method provided in an embodiment of the present application;

[0033] Figure 7 A structural diagram of a specific SOC-level memory access verification system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0035] Embodiment 1:

[0036] With the rapid development of integrated circuit technology, the scale of integrated circuits is getting larger and larger, and the cost is getting higher and higher. The cost of a single tape-out is very high. In order to fully verify the design within a limited time, simulation acceleration verification is becoming increasingly important.

[0037] In processor chip design, the memory storage controller is the most important module. All programs run in the memory. Its function is to store the calculation data in the CPU and the data exchanged with external storage devices such as hard disks. Therefore, in order to ensure sufficient verification, the CPU core memory access and peripheral memory access need to be fully verified.

[0038] In the SOC pre-silicon verification, various modes and various rates of various memories need to be fully verified. There are many verification scenarios and debugging takes a long time. Before the memory runs normally, the storage controller needs to be initialized and configured first. In the memory verification scenarios of different modes and different rates, the parameter configuration of the storage controller initialization is different. In general, to complete the initialization, it is necessary to configure thousands or even tens of thousands of storage controller registers, phy (physical layer) registers and DIMM (Dual-Inline-Memory-Modules) registers, which are referred to as the initialization of the storage controller in this application. After the storage controller initialization configuration is completed, the memory can work normally. At this time, the memory access request or DMA (Direct Memory Access) memory access request can access the memory.

[0039] In order to fully perform memory access verification, component-level memory access verification and SOC-level memory access verification are usually performed. The so-called component-level memory access verification refers to the memory access verification performed on a single storage controller module, which can also be called module-level memory access verification. The verification object is a single storage controller module in the chip design; the so-called SOC-level memory access verification refers to the memory access verification performed on the entire SOC. The verification object is all storage controllers in the SOC. Specifically:

[0040] In the component-level memory access verification, including the storage controller and memory, the environment is mainly built with UVM methodology. The storage controller initialization sequence is sent through the register interface driver in the form of a transaction packet. The storage controller initialization sequence is entered on the component interface, which only takes a few minutes. After the initialization configuration is completed, the memory access program sequence is sent through the data interface driver in the form of a transaction packet. The verification program sequence is sent directly on the interface, and the verification speed is very fast.

[0041] In SOC-level memory access verification, the minimum environment also needs to integrate the processor core, storage controller, memory, and flash (flash memory). The stimulus is generally written in assembly or C language to write the storage controller initialization sequence, which is converted into a format and placed in the flash. The processor core obtains the storage controller initialization sequence from the flash and then sends it to each storage controller for storage controller initialization configuration. The SOC chip contains multiple storage controllers. For the system-level initialization configuration of multiple storage controllers, they are configured in a serial order. After the storage controller is initialized, the processor begins to access the normal memory data path. However, the methods and program implementations of SOC-level memory access verification are very different from those of component-level memory access verification, and the verification program needs to be redeveloped. The redevelopment of the verification program means that new program debugging risks may be introduced. When such risks occur, the verification speed will be slowed down.

[0042] In addition, the scale of SOC-level memory access verification has gradually increased and become more complicated, which means that the initialization of the storage controller during verification takes several hours or even a day or a few days. However, when an error occurs in the SOC-level memory access verification and needs to be reproduced, or when the problem is solved and the SOC-level memory access verification needs to be re-performed, the initialization time is too long, which will cause a large time delay in debugging. In addition, when the program or code returns to stability, each program needs to be initialized. At the same time, a general SOC chip will also contain multiple storage controllers, and multiple storage controllers need to be initialized in turn. This program running time is unacceptable for verification. Therefore, it is unacceptable for the SOC-level memory access verification process to have an excessively long storage controller initialization time, which will seriously affect the verification efficiency of the SOC and thus affect the debugging time.

[0043] In order to improve the verification speed of SOC-level memory access verification, an embodiment of the present application provides a SOC-level memory access verification system, a storage controller initialization method in the SOC-level memory access verification process applied to the system, and a SOC-level memory access verification method.

[0044] See also Figure 1 As shown, Figure 1 The basic structural diagram of the SOC-level memory access verification system provided in the embodiment of the present application includes multiple storage controllers and a component-level verification environment corresponding to each storage controller, wherein each storage controller is connected to the component-level verification environment corresponding to the storage controller.

[0045] In the embodiment of the present application, the target storage controller can be initialized by receiving a storage controller initialization sequence sent by the connected component-level verification environment. The target storage controller can be any storage controller among the multiple storage controllers.

[0046] In the embodiment of the present application, the component-level verification environment corresponding to each storage controller refers to the environment used by the storage controller when performing component-level memory access verification, and includes a storage controller initialization sequence used by the storage controller when performing component-level memory access verification.

[0047] In the embodiment of the present application, once SOC-level memory access verification is required, the storage controller initialization sequence during the component-level memory access verification can be directly sent to each storage controller by using the component-level verification environment corresponding to each storage controller, so as to realize the initialization of each storage controller. In this way, on the one hand, the storage controller initialization sequence used during the component-level memory access verification corresponding to each storage controller can be directly reused, without the need to redevelop the program of the storage controller initialization part, and no new program debugging risk will be introduced, thereby improving the verification efficiency; on the other hand, since the component-level verification environment corresponding to each storage controller can independently send the storage controller initialization sequence to each storage controller, it means that when performing SOC-level memory access verification, each storage controller can be initialized in parallel. In this way, the initialization process time of the entire SOC-level memory access verification can be reduced to a time close to the component-level initialization time of a single storage controller, and the initialization process time of the entire SOC-level memory access verification can be reduced to the minute level, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0048] It can be understood that since the initialization time of the storage controller is shortened, when an error occurs in the SOC-level memory access verification and needs to be reproduced, or when the SOC-level memory access verification needs to be re-performed after the problem is solved, the initialization time of the storage controller is very fast, so the debugging time of the entire chip can be shortened. In addition, when the program or code returns to stability, the initialization time of the storage controller is very fast, so the running time of the program when it returns can also be shortened.

[0049] like Figure 2 As shown, in a feasible implementation of the embodiment of the present application, the SOC-level memory access verification system may further include: a verification instruction issuing module, an arbitration module and a memory. Among them:

[0050] Different storage controllers are respectively connected to different memories, and each storage controller is respectively connected to a component-level verification environment corresponding to each storage controller through a different arbitration module; and the arbitration module is also connected to the verification instruction issuing module.

[0051] The target storage controller is used to: during the initialization phase, receive the storage controller initialization sequence issued in the component-level verification environment through the connected arbitration module, and perform initialization; and, after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module through the connected arbitration module to perform memory access verification.

[0052] In this way, when performing SOC-level memory access verification, the arbitration module enables the storage controller to receive the storage controller initialization sequence for initialization during the initialization phase, and after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module for memory access verification. In this way, the normal verification function can be completed while the storage controller initialization sequence in the component-level verification environment is reused to complete the initialization, thereby ensuring the normal progress of the verification.

[0053] In the embodiment of the present application, the arbitration module can be implemented using Verilog. Exemplarily, a two-choice selector can be constructed using Verilog, which selects to send the storage controller initialization sequence from the component-level verification environment to the storage controller before the storage controller is initialized, and selects to send the verification instruction from the verification instruction sending module to the storage controller after the storage controller is initialized.

[0054] In the embodiments of the present application, the memory may be, but is not limited to, DDR, DDR2, DDR3, DDR4, DDR5, LPDDR4, LPDDR5, or even DDR6 under development, etc., but is not a limitation.

[0055] In the embodiments of the present application, Figure 3As shown, the verification instruction issuing module may include: a processor core, a verification instruction storage module and a network module. The processor core, the verification instruction storage module and each arbitration module are connected via the network module; the verification instruction storage module stores the verification instruction; the processor core is used to obtain the verification instruction from the verification instruction storage module and issue it to the arbitration module via the network module.

[0056] It can be understood that in the embodiment of the present application, the verification instruction storage module can be but is not limited to flash. In the embodiment of the present application, the network module can be but is not limited to NOC (network on chip).

[0057] Based on the above method, the processor core can implement memory access verification for each storage controller by fetching instructions (i.e., obtaining instructions) from the verification instruction storage module and issuing them through the network module, thereby ensuring the normal progress of verification and improving the reliability of the solution. In addition, since the initialization of each storage controller is completed through the corresponding component-level verification environment of each storage controller, the storage controller initialization sequence does not need to be stored in the verification instruction storage module, thereby reducing the demand for the storage capacity of the verification instruction storage module and improving the feasibility of the system.

[0058] In the embodiments of the present application, Figure 3 As shown, the verification instruction issuing module may also include: DMA (Direct Memory Access), so as to realize the DMA memory access verification by controlling DMA to access the memory connected to the memory controller to be verified. Exemplarily, the processor core may fetch instructions from the verification instruction storage module, and control DMA to access the memory connected to one or more memory controllers according to the instructions. Exemplarily, the DMA may also fetch instructions from the verification instruction storage module, and realize the DMA memory access verification according to the memory connected to the memory controller to be verified.

[0059] Of course, in some other feasible implementations of the embodiment of the present application, the arbitration module may not be set, but when SOC-level memory access verification is required, each storage controller is first connected to the component-level verification environment corresponding to each storage controller to complete the storage controller initialization. Then, the verification instruction issuing module is started to perform memory access verification.

[0060] In a feasible implementation of the embodiment of the present application, as Figure 4 As shown, the component-level verification environment may include: a storage controller initialization sequence, a register agent, and an end controller. The register agent is used to send the storage controller initialization sequence to the connected arbitration module; the end controller is configured not to end the simulation after the storage controller initialization sequence is sent.

[0061] It can be understood that a normal component-level verification environment will include a register agent. Therefore, based on the above feasible implementation method, the storage controller initialization sequence is externalized by reusing the register agent without adding additional modules. At the same time, by setting an end controller and configuring the end controller not to end the simulation after the storage controller initialization sequence is sent, the component-level verification environment can be distinguished from the process when executing component-level memory access verification, so that after the storage controller initialization sequence of the reused component-level verification environment is initialized, the simulation can continue, thereby completing the SOC-level memory access verification and improving the reliability of the solution.

[0062] In a feasible implementation of the embodiment of the present application, the end controller can be implemented in the form of a class and have a judgment function. The judgment function is used to: after determining that a preset enable signal is received, call the target function; the target function is a function that can prevent the simulation from ending.

[0063] Exemplarily, the end controller can be implemented in the form of a class with a judgment function inside. When the externally transmitted enable is turned on, the end controller calls the uvm function raise_objection() so that the simulation will not end.

[0064] In an embodiment of the present application, before the storage controller initialization sequence is sent, an enable signal can be passed through the top-level parameter passing method at the beginning of the simulation, so that the end controller calls the target function. The so-called top-level parameter passing method refers to the hierarchical reference of the tree class structure of UVM, which passes the parameters to the object in the class where the end controller is located.

[0065] In a feasible implementation of the embodiment of the present application, as Figure 4 As shown, the component-level verification environment may further include a data interface driver; the data interface driver is configured to be unused. It is understood that a normal component-level verification environment includes a data interface driver. In the above implementation, by configuring the data interface driver to be unused, the component-level verification environment is prevented from generating erroneous data receiving or sending operations, thereby improving the reliability of sending the storage controller initialization sequence.

[0066] It is understandable that the component-level verification environment may also include other modules, such as a virtual sequencer for obtaining a storage controller initialization sequence and a monitor for collecting data, etc., but this is not intended to be limiting.

[0067] Based on the same inventive concept, the embodiment of the present application also provides a storage controller initialization method in the SOC level memory access verification process, which can be applied to the target storage controller of the above-mentioned SOC level memory access verification system, see Figure 5 As shown, including:

[0068] S501: Receive a storage controller initialization sequence sent by a connected component-level verification environment to perform initialization.

[0069] In this way, the storage controller initialization sequence during the component-level memory access verification can be directly sent to each storage controller through the component-level verification environment corresponding to each storage controller, so as to realize the initialization of each storage controller. On the one hand, the storage controller initialization sequence used during the component-level memory access verification corresponding to each storage controller can be directly reused, without the need to redevelop the program of the storage controller initialization part, and no new program debugging risk will be introduced, thereby improving the verification efficiency; on the other hand, since the component-level verification environment corresponding to each storage controller can independently send the storage controller initialization sequence to each storage controller, it means that when performing SOC-level memory access verification, each storage controller can be initialized in parallel, so that the initialization process time of the entire SOC-level memory access verification can be reduced to a time close to the component-level initialization time of a single storage controller, and the initialization process time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0070] Based on the same inventive concept, the embodiment of the present application also provides a SOC-level memory access verification method, which can be applied to the above-mentioned SOC-level memory access verification, wherein: the above-mentioned SOC-level memory access verification system needs to include a verification instruction issuing module, an arbitration module, a memory, multiple storage controllers, and a component-level verification environment corresponding to each storage controller. Among them: different storage controllers are respectively connected to different memories, and each storage controller is connected to the component-level verification environment corresponding to each storage controller through a different arbitration module, and the arbitration module is also connected to the verification instruction issuing module.

[0071] See also Figure 6 As shown, the SOC level memory access verification method may include:

[0072] S601: The target storage controller receives a storage controller initialization sequence sent in a component-level verification environment through a connected arbitration module to perform initialization.

[0073] S602: After the initialization is completed, the target storage controller receives the verification instruction issued by the verification instruction issuing module through the connected arbitration module to perform memory access verification.

[0074] Based on the above-mentioned SOC-level memory access verification method, the above-mentioned implementation method can, on the one hand, directly reuse the storage controller initialization sequence used in the component-level memory access verification corresponding to each storage controller, without the need to redevelop the program of the storage controller initialization part, and will not introduce new program debugging risks, thereby improving the verification efficiency; on the other hand, since the component-level verification environment corresponding to each storage controller can independently send the storage controller initialization sequence to each storage controller, it means that when performing SOC-level memory access verification, each storage controller can be initialized in parallel. In this way, the initialization process time of the entire SOC-level memory access verification can be reduced to a time close to the component-level initialization time of a single storage controller, and the initialization process time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0075] It is understood that in the embodiment of the present application, when the component-level verification environment includes an end controller, before receiving the verification instruction issued by the verification instruction issuing module through the connected arbitration module, the end controller can be configured not to end the simulation after the storage controller initialization sequence is sent. It is understood that the configuration of the end controller can be configured by the engineer when setting the end controller.

[0076] In the embodiment of the present application, when the component-level verification environment includes a data interface driver, before the verification instruction issued by the verification instruction issuing module is received through the connected arbitration module, the data interface driver can also be configured to be unused. It can be understood that the configuration of the data interface driver can be set by the engineer when the component-level verification environment is connected to the SOC-level memory access verification system.

[0077] In an embodiment of the present application, when the verification instruction issuing module includes a processor core, a verification instruction storage module and a network module, and the processor core, the verification instruction storage module and each arbitration module are connected through the network module, and the verification instruction storage module stores the verification instruction, the processor core can continuously obtain the verification instructions of each storage controller from the verification instruction storage module by fetching instructions, and issue them to the corresponding arbitration module through the register interface bus in the network module, so as to be sent to the corresponding storage controller through the arbitration module. That is, at this time, the verification instructions received by each storage controller through the connected arbitration module are the verification instructions obtained by the processor core from the verification instruction storage module and issued through the network module.

[0078] It should be understood that, for the sake of brevity, some of the contents described in the first embodiment of the SOC-level memory access verification system will not be repeated in the above two method embodiments.

[0079] Embodiment 2:

[0080] To facilitate understanding of the solution of the embodiment of the present application, Figure 7 Taking the specific implementation structure shown as an example, the solution of this application is exemplified:

[0081] like Figure 7 As shown, the register interface of each storage control module is connected to the arbitration module. The arbitration module receives register requests from the component-level verification environment and the network module (specifically: the register request from the component-level verification environment is a request for the storage controller initialization sequence, and the register request from the network module is a verification instruction), and arbitrates and judges the register requests from both. Before the storage controller initialization is completed, the arbitration module will send the register request of the component-level verification environment (i.e., the storage controller initialization sequence) to the storage controller. After the initialization configuration is completed, the register request from the network module will be sent to the storage controller.

[0082] The software consists of two parts. One part is the storage controller initialization sequence implemented by SV (SystemVerilog, a hardware description and verification language) which is directly inherited from the component-level verification environment; the other part is the memory access function test program, which is developed and implemented by C program or assembler program, stored in the verification instruction storage module, and run by the processor core in the form of instruction fetch.

[0083] SOC-level memory access verification consists of two parts. After the simulation starts, the component-level verification environment will send the memory controller initialization sequence to the corresponding memory controller. After the memory controller initialization is completed, the memory access function test program starts to run and perform memory access testing. This not only ensures the consistency of SOC-level verification functions, but also greatly improves the efficiency of verification.

[0084] In the embodiments of the present application, Figure 7 As shown, the component-level verification environment includes a memory controller initialization sequence, a register agent, a data agent, a virtual sequencer, and an end controller.

[0085] The register agent includes a register interface driver, which is used to send the storage controller initialization sequence to the arbitration module; the data agent includes a data interface driver and a monitor, the data interface driver is configured to be in passive mode through the top-level parameters and is not used, and the monitor is used to collect interface data and send it to the reference model for comparison; after the end controller is enabled through the top-level parameter transmission method, the control simulation is not terminated after the storage controller initialization sequence is sent. Among them:

[0086] The reference model is a preset behavioral model of the design to be verified. It will be used to compare with the design function during the component-level memory access verification process to determine whether the design function behavior meets expectations.

[0087] The memory controller initialization sequence directly inherits the component-level verification environment.

[0088] The end controller is implemented in the form of a class with a judgment function inside. When the externally transmitted enable is turned on, the end controller calls the uvm function raise_objection() so that the simulation will not end.

[0089] The arbitration module is implemented using Verilog and is a two-choice selector. Before the storage controller is initialized, it chooses to send the storage controller initialization sequence from the component verification environment to the storage controller. When the initialization is completed, it chooses to send the register request from the network module to the storage controller.

[0090] The verification process is as follows:

[0091] Step 1: The simulator is compiled and run, and verification begins.

[0092] Step 2: The initial value of the storage controller's initialization completion mark signal is configured to be 0, the SOC is powered on and reset, and the processor core reset is not released (at this time, other circuits of the SOC except the processor core are restored to the initial state, and the register interface works normally). After the storage controller is powered on and reset, the component-level verification environment is started, and the controller is enabled and terminated by passing parameters, and the storage controller initialization sequence is sent to the arbitration module.

[0093] Step 3: The storage controller initialization sequence reaches the arbitration module through the register interface, and the arbitration module sends the storage controller initialization sequence to the storage controller.

[0094] Step 4: After the storage controller initialization configuration is completed, the storage controller initialization completion mark signal is configured to 1, the processor core reset is released, the arbitration module selects the channel switching, and no longer sends register requests from the component-level verification environment.

[0095] Step 5: The processor core starts to fetch instructions from the flash and perform memory access test.

[0096] Step 6: The memory access function test program is completed and the simulation ends.

[0097] In the existing SOC-level memory access verification, the initialization of the storage controller is configured through the processor core, and the configuration time takes several hours or even more than a day, which is unacceptable for debugging or regression verification. After using the above solution, for the same test stimulus, the initialization time can be reduced to the same time as the storage controller initialization in the component-level memory access verification, which can be completed within a few minutes, greatly improving the efficiency of the SOC-level memory access verification.

[0098] The solution of the present application reuses the component-level verification environment and the storage controller initialization sequence of the component-level verification environment. The developed arbitration module is simple to implement. The design only needs to make very simple connection modifications, and the arbitration module connection is used as part of the design. During operation, after the hardware initialization is completed, the bus is released and the software program starts working. For the program, the program behaviors of the two are completely consistent, but the verification efficiency can be improved. In addition, the solution of the present application does not need to develop an initialization program at the SOC level (i.e., the storage controller initialization sequence), and directly reuses the storage controller initialization sequence at the component level, reducing the time for writing and debugging the initialization program at the SOC level.

[0099] It can be understood that for the sake of convenience, the drawings of the present application only show the case of two storage controllers, but in actual applications, the number of storage controllers and register interface configuration simulators can be greater.

[0100] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The embodiments described above are merely illustrative. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be an indirect coupling or communication connection through some communication interface, device or unit, which can be electrical, mechanical or other forms.

[0101] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0102] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0103] As used herein, a plurality refers to two or more than two.

[0104] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A SOC level memory access verification system, characterized in that: include: Multiple storage controllers, and a component-level verification environment corresponding to each storage controller; wherein: each of the storage controllers is connected to the component-level verification environment corresponding to the storage controller; The target storage controller is used to: receive the storage controller initialization sequence sent in the component-level verification environment to initialize; The target storage controller is any storage controller among the multiple storage controllers.

2. The SOC level memory access verification system according to claim 1, characterized in that: The SOC-level memory access verification system further includes: a verification instruction issuing module, an arbitration module and a memory; wherein: Different storage controllers are respectively connected to different memories, and each storage controller is respectively connected to a component-level verification environment corresponding to each storage controller through a different arbitration module; and the arbitration module is also connected to the verification instruction issuing module; The target storage controller is used to: during the initialization phase, receive the storage controller initialization sequence issued in the component-level verification environment through the connected arbitration module, and perform initialization; and, after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module through the connected arbitration module to perform memory access verification.

3. The SOC level memory access verification system as claimed in claim 2, characterized in that: The component-level verification environment includes: the storage controller initialization sequence, register agent, and end controller; The register agent is used to send the storage controller initialization sequence to the connected arbitration module; The termination controller is configured not to terminate the simulation after the storage controller initialization sequence is sent.

4. The SOC level memory access verification system as claimed in claim 3, characterized in that: The end controller is implemented in the form of a class and has a judgment function; the judgment function is used to: after determining that a preset enable signal is received, call the target function; the target function is a function that can prevent the simulation from ending.

5. The SOC level memory access verification system as claimed in claim 3, characterized in that: The component-level verification environment further includes: a data interface driver; the data interface driver is configured to be unused.

6. The SOC level memory access verification system according to any one of claims 2 to 5, characterized in that: The verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core, the verification instruction storage module, and each of the arbitration modules are connected via the network module; The verification instruction storage module stores verification instructions; The processor core is used for obtaining the verification instruction from the verification instruction storage module and sending the verification instruction to the arbitration module through the network module.

7. A method for initializing a storage controller in a SOC-level memory access verification process, characterized in that: Applied to the target storage controller of the SOC-level memory access verification system; The SOC-level memory access verification system comprises: a plurality of storage controllers and a component-level verification environment corresponding to each storage controller; wherein: each of the storage controllers is connected to the component-level verification environment corresponding to the storage controller; the target storage controller is any storage controller among the plurality of storage controllers; the method comprises: Receive a storage controller initialization sequence sent by the connected component-level verification environment to perform initialization.

8. A SOC level memory access verification method, characterized in that: Applied in SOC-level memory access verification system; The SOC-level memory access verification system comprises: a verification instruction issuing module, an arbitration module, a memory, a plurality of storage controllers, and a component-level verification environment corresponding to each storage controller; wherein: different storage controllers are respectively connected to different memories, and each storage controller is respectively connected to the component-level verification environment corresponding to each storage controller through a different arbitration module; and the arbitration module is also connected to the verification instruction issuing module; the method comprises: The target storage controller receives the storage controller initialization sequence sent in the component-level verification environment through the connected arbitration module to perform initialization; After the initialization is completed, the target storage controller receives the verification instruction issued by the verification instruction issuing module through the connected arbitration module to perform memory access verification; The target storage controller is any storage controller among the multiple storage controllers.

9. The SOC level memory access verification method according to claim 8, characterized in that: The component-level verification environment includes: an end controller; Before receiving the verification instruction issued by the verification instruction issuing module through the connected arbitration module, the method further includes: The termination controller is configured not to terminate the simulation after the storage controller initialization sequence is sent.

10. The SOC level memory access verification method according to claim 8, characterized in that: The verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core, the verification instruction storage module and each arbitration module are connected via the network module; the verification instruction storage module stores the verification instruction; wherein: The verification instruction received by the connected arbitration module is a verification instruction obtained by the processor core from the verification instruction storage module and issued by the network module.

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