Method for forming copper metal layer
By adopting gradient annealing and planarization in the production process of copper metal layer, the problem of hole defects after annealing of copper metal layer is solved, and the reliability and yield of semiconductor integrated circuits are improved.
Patent Information
- Application Number
- CN202411188562.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2024-12-10
AI Technical Summary
In the rear-stage process of semiconductor integrated circuits, the copper metal layer is prone to form hole defects after annealing, affecting the reliability and yield of the product.
The gradient annealing treatment method is adopted, including two annealing treatments, each annealing temperature is higher than the previous one, and the grain boundary diffusion repair is promoted through lower temperature annealing, stress is released at a higher temperature, and cover layer is removed by planarization.
Through gradient annealing treatment and planarization processes, the structure of the copper metal layer is improved and the reliability and yield of the product are improved.
Smart Images
Figure CN119108342A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for forming a copper metal layer. Background Art
[0002] The semiconductor integrated circuit manufacturing process includes the front end of line (FEOL) process and the back end of line (BEOL) process. Among them, the back end process is to form several layers of conductive metal wiring on the wafer integrated with transistors. The metal wirings at different levels are electrically connected through contact holes (via), and the different metal wirings are insulated and isolated through the interlayer dielectric (ILD) layer.
[0003] In the back-end process, especially below 65 nanometer (nm) process, copper metal layer is generally used as metal connection medium. The copper metal layer is usually formed by depositing barrier layer and seed layer in sequence, and then depositing copper layer by electrochemical plating (ECP) process, and then annealing. Then, after annealing the copper metal layer, there is a certain probability of forming void defects in the metal layer, which affects the reliability and yield of the product. Summary of the invention
[0004] The present application provides a method for forming a copper metal layer, which can solve the problem in the related art that hole defects are easily formed in the copper metal layer due to annealing. The method comprises:
[0005] A wafer is provided, wherein a semiconductor device is formed on the wafer, an interlayer dielectric layer is formed above the semiconductor device, the interlayer dielectric layer fills the gap of the semiconductor device, a groove is formed in the interlayer dielectric layer, and the groove is used to form a metal connection line or a contact hole in a metal interconnection structure of the semiconductor device;
[0006] forming a barrier layer on the surface of the groove in the interlayer dielectric layer;
[0007] forming a copper seed layer on the barrier layer;
[0008] forming a copper metal layer on the copper seed crystal layer by an electrochemical plating process;
[0009] Performing edge cleaning on the wafer;
[0010] Performing at least two annealing treatments, each annealing treatment having a temperature higher than that of the previous annealing treatment;
[0011] A planarization process is performed to remove the barrier layer, the copper seed crystal layer and the copper metal layer outside the trench.
[0012] In some embodiments, the at least two annealing treatments include a first annealing treatment and a second annealing treatment;
[0013] The temperature of the first annealing treatment is lower than the temperature of the second annealing treatment, and the temperature of the first annealing treatment ranges from 100 degrees Celsius to 150 degrees Celsius.
[0014] In some embodiments, the temperature of the second annealing treatment ranges from 180 degrees Celsius to 250 degrees Celsius.
[0015] In some embodiments, the first annealing treatment lasts for 30 seconds to 60 seconds.
[0016] In some embodiments, the second annealing treatment lasts for 10 seconds to 50 seconds.
[0017] In some embodiments, the barrier layer includes a tantalum nitride layer.
[0018] The technical solution of this application has at least the following advantages:
[0019] In the manufacturing process of the copper metal interconnect structure, after the copper metal layer is formed, a gradient annealing treatment with gradually rising temperature is performed. Since the lower temperature annealing treatment can promote grain boundary diffusion, the defects and holes on the grain boundaries can be repaired. Especially when heated by a heating plate, the grain boundary holes gradually diffuse upward along the heat transfer direction due to the effect of grain boundary energy, and gradually make the grain boundary holes in the structural layer area diffuse upward to the covering layer area. The higher temperature annealing treatment can fully release the stress. After the subsequent planarization process, the covering layer area is removed, thereby achieving the improvement of the grain boundary holes in the structural layer area, and improving the reliability and yield of the product to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 is a flow chart of a method for forming a copper metal layer provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0022] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0023] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0024] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0025] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0026] refer to Figure 1 , which shows a flow chart of a method for forming a copper metal layer provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:
[0027] Step S1, providing a wafer, on which a semiconductor device is formed, an interlayer dielectric layer is formed above the semiconductor device, the interlayer dielectric layer fills the gap of the semiconductor device, and a groove is formed in the interlayer dielectric layer, which is used to form a metal connection or contact hole in the metal interconnection structure of the semiconductor device.
[0028] Step S2, forming a barrier layer on the interlayer dielectric layer and the surface of the trench.
[0029] Exemplarily, the barrier layer includes a tantalum nitride (TaN) layer, and the TaN layer can be deposited by a physical vapor deposition (PVD) process.
[0030] Step S3, forming a copper seed layer on the barrier layer.
[0031] Step S4, forming a copper metal layer on the copper seed crystal layer by an electrochemical plating process.
[0032] For example, the thickness of the copper metal layer formed by the electrochemical plating process is 7000 angstroms. To 55,000 angstroms.
[0033] Step S5, performing edge cleaning on the wafer.
[0034] Exemplarily, the range of the edge cleaning process is a predetermined width from the outermost edge of the wafer inward, and the predetermined width is greater than or equal to 1 millimeter (mm).
[0035] Step S6, performing at least two annealing treatments, wherein the temperature of each annealing treatment is higher than the temperature of the previous annealing treatment.
[0036] Exemplarily, the following takes two annealing treatments (the first annealing treatment and the second annealing treatment, the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment) as an example to explain step S6: the first annealing treatment is performed, the temperature of the first annealing treatment ranges from 100 degrees Celsius (℃) to 150 degrees Celsius, and the time of the first annealing treatment is 30 seconds (s) to 60 seconds; the second annealing treatment is performed, the temperature of the second annealing treatment ranges from 180 degrees Celsius to 250 degrees Celsius, and the time of the second annealing treatment is 10 seconds to 50 seconds. Through at least two gradient annealing treatments (annealing treatments with gradually rising temperatures), the annealing treatment at a lower temperature can promote grain boundary diffusion, so that defects and holes on the grain boundaries are repaired, especially when heated by a heating plate, along the heat transfer direction, the grain boundary holes gradually diffuse upward due to the effect of grain boundary energy, and gradually make the grain boundary holes in the structural layer area diffuse upward to the cover layer area, and the annealing treatment at a higher temperature can fully release the stress.
[0037] Step S7, performing a planarization process to remove the barrier layer, the copper seed crystal layer and the copper metal layer outside the trench.
[0038] For example, a planarization process may be performed by a chemical mechanical polishing (CMP) process to remove the barrier layer, the copper seed layer, and the copper metal layer outside the trench.
[0039] To summarize, in the embodiments of the present application, in the manufacturing process of the copper metal interconnect structure, after the copper metal layer is formed, a gradient annealing treatment with gradually rising temperature is performed. Since the annealing treatment at a lower temperature can promote grain boundary diffusion, defects and holes on the grain boundaries are repaired. In particular, when heated by a heating plate, the grain boundary holes gradually diffuse upward along the heat transfer direction due to the effect of grain boundary energy, and gradually cause the grain boundary holes in the structural layer area to diffuse upward to the covering layer area. The annealing treatment at a higher temperature can fully release the stress. After the subsequent planarization process, the covering layer area is removed, thereby achieving an improvement in the grain boundary holes in the structural layer area, and to a certain extent improving the reliability and yield of the product.
[0040] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for forming a copper metal layer, characterized in that: include: A wafer is provided, wherein a semiconductor device is formed on the wafer, an interlayer dielectric layer is formed above the semiconductor device, the interlayer dielectric layer fills the gap of the semiconductor device, a groove is formed in the interlayer dielectric layer, and the groove is used to form a metal connection line or a contact hole in a metal interconnection structure of the semiconductor device; forming a barrier layer on the interlayer dielectric layer and the surface of the trench; forming a copper seed layer on the barrier layer; forming a copper metal layer on the copper seed crystal layer by an electrochemical plating process; Performing edge cleaning on the wafer; Performing at least two annealing treatments, each annealing treatment having a temperature higher than that of the previous annealing treatment; A planarization process is performed to remove the barrier layer, the copper seed crystal layer and the copper metal layer outside the trench.
2. The method according to claim 1, characterized in that The at least two annealing treatments include a first annealing treatment and a second annealing treatment; The temperature of the first annealing treatment is lower than the temperature of the second annealing treatment, and the temperature of the first annealing treatment ranges from 100 degrees Celsius to 150 degrees Celsius.
3. The method according to claim 2, characterized in that The temperature of the second annealing treatment ranges from 180 degrees Celsius to 250 degrees Celsius.
4. The method according to claim 3, characterized in that The first annealing treatment lasts for 30 seconds to 60 seconds.
5. The method according to claim 4, characterized in that The second annealing treatment lasts for 10 seconds to 50 seconds.
6. The method according to any one of claims 1 to 5, characterized in that: The barrier layer includes a tantalum nitride layer.