Method of aligning semiconductor wafer for singulation

Abstract

The invention relates to a method of aligning a semiconductor wafer for singulation. Implementations of a method for aligning a semiconductor wafer for singulation may include providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of dies, and the plurality of dies may be separated by lanes. The semiconductor wafer may include an edge ring surrounding a perimeter of the wafer on a second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to form an edge exclusion region, and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion region on a second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion region.

Description

[0001] This application is a divisional application of the invention patent application with the application date of January 6, 2020, application number 202010008015.8, and invention name “Method of aligning semiconductor wafers for splitting”.

[0002] Cross-references to related patent applications This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 796,687 to Seddon et al., entitled “METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION,” filed on January 25, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Background Art 1. Technical Field Aspects of this document generally relate to systems and methods for aligning substrates for singulation. More detailed implementations relate to semiconductor substrates. 2. Background technology The semiconductor substrate is used to form various semiconductor devices. The semiconductor devices are usually distributed on the flat surface of the semiconductor substrate in multiple dies. The multiple dies are separated from each other using a singulation process (such as sawing). Summary of the invention

[0005] A specific implementation of a method for aligning a semiconductor wafer for singulation may include providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of dies, and the plurality of dies may be separated by a track. The semiconductor wafer may include an edge ring surrounding a periphery of the wafer located on the second side of the wafer. The wafer may also include a metal layer located on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to form an edge exclusion region, and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion region located on the second side of the wafer. Aligning the wafer may include using two or more alignment features located in the edge exclusion region.

[0006] Specific implementations of the method for aligning a semiconductor wafer may include one, all, or any of the following: The metal layer may include copper having a thickness of 15 microns.

[0007] The method may further include singulating the plurality of semiconductor dies using one of sawing, laser action, or plasma etching.

[0008] The method may further include mounting the wafer to a pick-up tape.

[0009] Grinding the edge ring may also include washing debris from the wafer.

[0010] The metal layer may include one of gold, copper, nickel, or any combination thereof.

[0011] The camera may be an infrared camera and the semiconductor wafer may include silicon.

[0012] A specific implementation of a method for aligning a semiconductor wafer for singulation may include providing a semiconductor wafer having a first side and a second side. The semiconductor wafer may include an edge ring around a perimeter of the wafer located on the second side of the wafer. The method may include applying a metal coating to the second side of the wafer. The metal coating may extend substantially over the edge ring. The method may also include forming an edge exclusion zone by removing the edge ring. The method may also include aligning the wafer for singulation using an infrared camera. The infrared camera may use two or more alignment features located in the edge exclusion zone.

[0013] Specific implementations of the method for aligning a semiconductor wafer may include one, all, or any of the following: The metal coating may be applied by one of sputtering, evaporation or electroplating.

[0014] The method may further include mounting the wafer to a film frame.

[0015] The method may further include singulating a plurality of semiconductor dies from the semiconductor wafer using one of sawing, laser action, and plasma etching.

[0016] The metal coating may have a thickness of at least 15 microns.

[0017] Removing the edge ring may include grinding and washing the semiconductor wafer.

[0018] Singulation may include one of sawing, laser action, and plasma etching.

[0019] A specific implementation of a method for aligning a semiconductor wafer for singulation may include mounting a first side of the semiconductor wafer to a back grinding belt. The semiconductor wafer may include an edge ring around the perimeter of the wafer located on a second side of the wafer. The method may also include applying a metal layer to the second side of the wafer. The metal layer may extend substantially over the edge ring. The metal layer may include grinding the edge ring and removing the metal layer in a peripheral region of the wafer. The method may include aligning the wafer for singulation using a camera and two or more alignment features located in a peripheral region of the wafer.

[0020] Specific implementations of the method for aligning a semiconductor wafer may include one, all, or any of the following: The metal layer may be applied by one of sputtering, evaporation and electroplating.

[0021] The method may also include using a laser to singulate a plurality of semiconductor dies from the semiconductor wafer.

[0022] The metal layer may include copper having a thickness of 15 microns.

[0023] Removing the ring by grinding may also include washing debris from the wafer.

[0024] The camera may be an infrared camera and the semiconductor wafer may be silicon.

[0025] The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Specific implementations will be described below in conjunction with the accompanying drawings, in which like reference numerals represent like elements, and: Figure 1 is a side view of a specific implementation of a system for aligning a semiconductor wafer having a metal layer substantially covering an edge ring; and Figure 2 A side view of an implementation of a system for aligning a semiconductor wafer having an implementation of an edge exclusion region formed via grinding is shown. DETAILED DESCRIPTION

[0027] The present disclosure, its aspects, and specific implementations are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly processes, and / or method elements known in the art that are consistent with the intended method of aligning semiconductor wafers for segmentation will be readily apparent for use with specific specific implementations of the present disclosure. Thus, for example, although the present invention discloses specific implementations, such specific implementations and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, etc. of such methods and implementation components and methods known in the art for aligning semiconductor wafers for segmentation that are consistent with the intended operation and method.

[0028] For semiconductor dies with a thickness of less than 50 microns, there are specific processing challenges. Die handling, die strength, and performing processing operations with the die all present specific challenges, as die and wafer breakage can significantly reduce yield and / or affect device reliability. Die strength is negatively impacted by traditional singulation options, such as sawing, which causes die breakage and cracks along the die lanes. These fragments and cracks formed during the sawing process can eventually propagate during operation and reliability testing, resulting in die failure.

[0029] See also Figure 1 , showing a cross-sectional side view of a substrate 2 coupled to a plurality of layers. The term "substrate" refers to a semiconductor substrate, because a semiconductor substrate is a common type of substrate, but "substrate" is not a specialized term used to refer to all semiconductor substrate types. Similarly, the term "substrate" may refer to a wafer, because a wafer is a common type of substrate, but "substrate" is not a specialized term used to refer to all wafers. By way of non-limiting example, the various semiconductor substrate types disclosed in this document that may be utilized in various implementations may be circular, rounded, square, rectangular, or any other closed shape. In various implementations, by way of non-limiting example, the substrate 2 may include substrate materials such as single crystal silicon, silicon dioxide, glass, gallium arsenide, sapphire, ruby, silicon on insulator, silicon carbide, any of the foregoing in polycrystalline or amorphous form, and any other substrate material that may be used to construct semiconductor devices. In a particular implementation, the substrate may be a silicon on insulator substrate.

[0030] See also Figure 1In various embodiments disclosed in this document, the semiconductor substrate 2 includes a plurality of semiconductor dies 4 that have been processed using a semiconductor manufacturing process to form one or more semiconductor devices (not shown) in or on the semiconductor substrate. The die 4 may include a plurality of metal layers, such as copper and aluminum, by way of non-limiting example. Each of the plurality of dies may be separated by a track. The plurality of layers may be patterned, and in various embodiments, may be patterned (or otherwise removed) to not be located above the die track 12 in the substrate 2. By way of non-limiting example, the plurality of layers may include one or more metal layers 4 and 6, one or more passivation layers 10, any other layers, and any combination thereof. In various embodiments, by way of non-limiting example, the plurality of dies may include power semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), or any other power semiconductor devices. In other embodiments, the plurality of dies may include non-power semiconductor devices.

[0031] After the fabrication process is completed (or in some implementations, during some portions of the fabrication process), the semiconductor substrate 2 is thinned to a desired substrate thickness on a side 6 of the semiconductor substrate 2 opposite to the side on which one or more semiconductor devices 4 have been formed. The thinning process is performed using back grinding, polishing, etching, any combination thereof, or any other technique for substantially uniformly removing material of the semiconductor substrate over the largest planar surface of the substrate.

[0032] In various implementations, the thinning process can produce an edge ring 8 around the wafer (like the edge ring present in the TAIKO back grinding process sold by Disco Hi-Tec America, Inc., Santa Clara, California). The edge ring is used to structurally support the wafer after thinning so that a wafer carrier is not required during subsequent processing steps. In various implementations, the thinning process can be performed after the semiconductor substrate 2 has been mounted to the back grinding tape 10. In various implementations, various back grinding tapes can be used, including those compatible with subsequent etching operations.

[0033] After the thinning process, the various tube cores 4 formed in the semiconductor substrate 2 need to be separated from each other so that they can be subsequently packaged into a semiconductor package. In various specific implementations, after the thinning process, by way of non-limiting example, a back metal layer 10 is applied to the semiconductor tube core by sputtering, evaporation, or another metal deposition process or combination of processes. In various specific implementations, the deposition process is performed while the wafer is supported by an edge ring or supported by a back grinding tape. However, in other specific implementations, the substrate can be removed from the back grinding tape and mounted to another support tape for subsequent processing steps. The separation is performed by cutting / slicing the semiconductor substrate in the tube core lane between each tube core in a plurality of tube cores using any of the various methods disclosed herein.

[0034] The total thickness 8 of the semiconductor substrate 2 is the cumulative thickness of the substrate 2 with any die 4 thereon, the thickness of the back metal 12, and the thickness of any passivation material on the back metal. In various implementations, the thickness of the back metal may vary between about 1 micrometer (µm) and about 15 µm. In a particular implementation, the thickness of the back metal may be between about 1 µm and about 3 µm. In various implementations, the total thickness of the semiconductor substrate 2 may be less than about 50 µm. In a particular implementation, the total thickness of the semiconductor substrate may be between about 25 µm and about 35 µm. In various implementations, the total thickness may be about 25 µm.

[0035] In various implementations, the substrate 2 may be thinned to a thickness of less than 50 µm. In other implementations, the substrate 2 may be thinned to a thickness of less than 30 µm. In still other implementations, the substrate 2 may be thinned to a thickness of less than 100 µm, greater than 100 µm, and in various other implementations, the substrate 2 may not be thinned. In certain implementations, the substrate 2 may be thinned to a thickness of about 25 µm, and in other certain implementations, the substrate may be thinned to a thickness of about 75 µm.

[0036] In order to separate the multiple tube cores from the substrate, the substrate must be aligned with a set of predefined physical locations where the saw or other tool used to separate the tube cores will cut into the material of the substrate. In various specific implementations, multiple alignment features can be manufactured into the substrate to guide the separation process. The alignment features can be formed in the tube core lanes located between the tube cores and formed on the first side of the substrate. In other specific implementations, the alignment features can be formed on the edges of the tube cores. The alignment features can be located in any layer of the substrate. In various specific implementations, the alignment features can be located using an infrared camera. The infrared camera may be able to penetrate layers of silicon or other materials to locate the alignment features. In other specific implementations, the alignment features may be located on the outer surface of the substrate. In some specific implementations, the alignment features can be visible with a visible light camera.

[0037] In various implementations, after the thinning process, by way of non-limiting example, the back metal layer 14 is applied to the semiconductor die by sputtering, evaporation, or another metal deposition process. In a particular implementation, the back metal layer 14 may be copper or a copper alloy. In other implementations, the back metal layer may include any other type of metal, their alloys, or combinations thereof. In various implementations, the back metal layer may be about 10µm thick. In other implementations, the back metal layer may be greater than or less than 10µm thick. The back metal layer 14 may be evaporated onto the substrate 2, however, in other implementations (including implementations with thicker substrates), another technique may be used to electroplate the back metal layer 14 onto the substrate 2 or to form it on the substrate.

[0038] See again Figure 1 , shows a semiconductor wafer 2 mounted on a back grinding belt 10. The belt 10 may be supported by a film frame 11. A method of aligning a semiconductor wafer for singulation may include providing a semiconductor wafer 2 as shown. The semiconductor wafer 2 includes a plurality of dies 4 formed on a first side of the wafer. The semiconductor wafer 2 has been thinned, leaving an edge ring 8 around the periphery of the wafer 2. In various embodiments, the wafer may be thinned by back grinding as previously described. The method may include applying a metal coating 12 to a second side of the wafer. By way of non-limiting example, the metal coating may include copper, nickel, gold, any combination thereof, alloys thereof, or other metals used in metallization processes. In a particular embodiment of the method, the metal layer may include copper having a thickness of about 15 microns. In other embodiments, the metal layer may have a thickness of less than 15 microns. The method may include applying the metal coating by sputtering, electroplating, evaporation, or one of other methods for applying back metal to a semiconductor wafer. The metal coating 12 may extend substantially over the edge ring 8. When the metal coating 12 substantially covers the edge ring, the camera 14 focused on the second side of the wafer 2 is blocked from viewing therethrough the metal coating. By way of non-limiting example, the metal layer is covered by a patterned photoresist capping layer.

[0039] See also Figure 2, showing a substrate ready to align a wafer by removing the edge ring to form an edge exclusion area 16. The edge ring can be removed by grinding the material of the metal layer and the edge ring. Grinding the ring can also include washing debris from the wafer. Various embodiments of the method can be used with substrates having thick back metal as well as thin back metal. In various embodiments, multiple alignment features can be included in the size of the edge exclusion area. In other embodiments, at least two alignment features can be formed in the edge exclusion area. In other embodiments, three or more alignment features can be formed in the edge exclusion area. The method can also include using at least two alignment features to align the wafer 20 for segmentation using a camera. In various embodiments, the camera can be an infrared camera and the wafer can be formed of silicon. The camera may be able to detect alignment features in silicon or other layered materials to align the wafer with the segmentation tool. In various embodiments, vacuum checking may not be required during the alignment process.

[0040] In various implementations, the wafer may be singulated using a saw. In other implementations, the wafer may be singulated by laser action. In some implementations, the wafer may be singulated into a plurality of dies using jet ablation. In methods that include slotting or thinning of a metal layer, a plasma may be used to singulate the wafer into a plurality of dies. In some implementations, the singulation step may be performed from a first side of the substrate or a second side of the substrate. For implementations in which singulation is performed using sawing or laser action, remote plasma healing may be performed on the singulated dies to remove sidewall damage. In various implementations, remote plasma healing may also be used to remove small amounts of redeposition.

[0041] Variations of the method may allow for active modification / adjustment of the alignment of the wafer or the segmentation process itself during the segmentation process based on visual inspection. Non-limiting examples of possible modifications may include changes in laser power, changes in laser pulses, or changes in speed. The camera 20 may also be able to monitor the need to remove back metal / remaining back metal thickness. In various specific implementations, the camera may be used to measure any thickness changes of any ablated metal and the initial thickness of the metal. Such monitoring may allow segmentation parameters to be adjusted during the segmentation process. In various specific implementations, the use of alignment features located in the edge exclusion area during the alignment process may not require the use of vacuum checks.

[0042] In a specific implementation of the methods disclosed herein, the metal layer may include copper having a thickness of 15 microns.

[0043] Specific implementations of the methods disclosed herein may also include singulating the plurality of dies using one of sawing, laser action, or plasma etching.

[0044] In specific implementations of the methods disclosed herein, grinding further includes washing debris from the semiconductor wafer.

[0045] In a specific implementation of the method disclosed herein, the metal layer includes one of gold, copper, nickel, or any combination thereof.

[0046] Specific implementations of the methods disclosed herein also include mounting the semiconductor wafer to a film frame.

[0047] In particular implementations of the methods disclosed herein, the metal coating has a thickness of at least 15 microns.

[0048] In a specific implementation of the method disclosed herein, the metal layer is applied by one of sputtering, evaporation, and electroplating.

[0049] In specific implementations of the methods disclosed herein, removing the edge ring by grinding further includes washing debris from the semiconductor wafer.

[0050] Where reference is made in the above description to specific implementations of the wafer alignment method and to implementation components, sub-components, methods and sub-methods, it should be readily apparent that various modifications may be made without departing from the essence thereof, and that these specific implementations, implementation components, sub-components, methods and sub-methods may be applied to other wafer alignment methods.

Claims

1. A semiconductor wafer, comprising: a first side surface and a second side surface, the first side surface of the semiconductor wafer comprising a plurality of dies; an edge ring surrounding a perimeter of the semiconductor wafer on the second side of the semiconductor wafer; as well as a metal layer coupled to the second side of the semiconductor wafer; The edge ring includes two or more alignment features configured to align the semiconductor wafer for singulation. 2 . The semiconductor wafer according to claim 1 , wherein a surface of the edge ring away from the first side of the semiconductor wafer is coplanar with a portion of a surface of the metal layer away from the first side of the semiconductor wafer. 3 . The semiconductor wafer of claim 1 , wherein the two or more alignment features are located on an outer surface of the edge ring. 4 . The semiconductor wafer of claim 1 , wherein the two or more alignment features are embedded within and covered by the edge ring.

5. A semiconductor wafer comprising: a first side surface and a second side surface, the first side surface of the semiconductor wafer comprising a plurality of dies; an edge ring surrounding a perimeter of the semiconductor wafer on the second side of the semiconductor wafer; as well as a metal layer coupled to the second side of the semiconductor wafer and extending over the edge ring; The edge ring includes two or more alignment features configured to align the semiconductor wafer for singulation. The semiconductor wafer of claim 5 , wherein the metal layer comprises copper having a thickness of 15 μm. 7 . The semiconductor wafer of claim 5 , wherein the two or more alignment features are embedded within and covered by the edge ring.

8. A semiconductor wafer, comprising: a first side and a second side, the first side of the semiconductor wafer comprising a plurality of dies separated by die lanes; an edge ring formed on the second side of the semiconductor wafer around a periphery of the semiconductor wafer; as well as a metal layer coupled to the second side of the semiconductor wafer and within an area defined by the edge ring; The edge ring includes two or more alignment features configured to align the semiconductor wafer for singulation. 9 . The semiconductor wafer according to claim 8 , wherein a height of the edge ring is equal to a height of the metal layer. 10 . The semiconductor wafer of claim 8 , wherein the semiconductor wafer is configured to be aligned using an infrared camera.

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